1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/gpio/gpio.h> 9 10#include "k3-j7200.dtsi" 11 12/ { 13 memory@80000000 { 14 device_type = "memory"; 15 bootph-all; 16 /* 4G RAM */ 17 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 18 <0x00000008 0x80000000 0x00000000 0x80000000>; 19 }; 20 21 reserved_memory: reserved-memory { 22 #address-cells = <2>; 23 #size-cells = <2>; 24 ranges; 25 26 secure_ddr: optee@9e800000 { 27 reg = <0x00 0x9e800000 0x00 0x01800000>; 28 alignment = <0x1000>; 29 no-map; 30 }; 31 32 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 33 compatible = "shared-dma-pool"; 34 reg = <0x00 0xa0000000 0x00 0x100000>; 35 no-map; 36 }; 37 38 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 39 compatible = "shared-dma-pool"; 40 reg = <0x00 0xa0100000 0x00 0xf00000>; 41 no-map; 42 }; 43 44 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 45 compatible = "shared-dma-pool"; 46 reg = <0x00 0xa1000000 0x00 0x100000>; 47 no-map; 48 }; 49 50 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 51 compatible = "shared-dma-pool"; 52 reg = <0x00 0xa1100000 0x00 0xf00000>; 53 no-map; 54 }; 55 56 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 57 compatible = "shared-dma-pool"; 58 reg = <0x00 0xa2000000 0x00 0x100000>; 59 no-map; 60 }; 61 62 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 63 compatible = "shared-dma-pool"; 64 reg = <0x00 0xa2100000 0x00 0xf00000>; 65 no-map; 66 }; 67 68 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 69 compatible = "shared-dma-pool"; 70 reg = <0x00 0xa3000000 0x00 0x100000>; 71 no-map; 72 }; 73 74 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 75 compatible = "shared-dma-pool"; 76 reg = <0x00 0xa3100000 0x00 0xf00000>; 77 no-map; 78 }; 79 80 rtos_ipc_memory_region: ipc-memories@a4000000 { 81 reg = <0x00 0xa4000000 0x00 0x00800000>; 82 alignment = <0x1000>; 83 no-map; 84 }; 85 }; 86 87 mux0: mux-controller-0 { 88 compatible = "gpio-mux"; 89 #mux-state-cells = <1>; 90 mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>; 91 }; 92 93 mux1: mux-controller-1 { 94 compatible = "gpio-mux"; 95 #mux-state-cells = <1>; 96 mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>; 97 }; 98 99 transceiver0: can-phy0 { 100 /* standby pin has been grounded by default */ 101 compatible = "ti,tcan1042"; 102 #phy-cells = <0>; 103 max-bitrate = <5000000>; 104 }; 105}; 106 107&wkup_pmx0 { 108 mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins { 109 pinctrl-single,pins = < 110 J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ 111 J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ 112 J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */ 113 J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */ 114 J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */ 115 J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */ 116 J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (C7) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */ 117 J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (C5) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */ 118 J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (A5) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */ 119 J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (A6) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */ 120 J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */ 121 J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ 122 J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ 123 >; 124 bootph-all; 125 }; 126 127 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { 128 pinctrl-single,pins = < 129 J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ 130 J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ 131 J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */ 132 J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */ 133 J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */ 134 J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */ 135 J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */ 136 J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */ 137 J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */ 138 J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ 139 J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ 140 >; 141 bootph-all; 142 }; 143}; 144 145&wkup_pmx2 { 146 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 147 pinctrl-single,pins = < 148 J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */ 149 J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ 150 >; 151 bootph-all; 152 }; 153}; 154 155&wkup_pmx3 { 156 pmic_irq_pins_default: pmic-irq-default-pins { 157 pinctrl-single,pins = < 158 J721E_WKUP_IOPAD(0x01c, PIN_INPUT, 7) /* (E18) WKUP_GPIO0_84 */ 159 >; 160 }; 161}; 162 163&main_pmx0 { 164 main_i2c0_pins_default: main-i2c0-default-pins { 165 pinctrl-single,pins = < 166 J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ 167 J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ 168 >; 169 }; 170 171 main_mcan0_pins_default: main-mcan0-default-pins { 172 pinctrl-single,pins = < 173 J721E_IOPAD(0x24, PIN_INPUT, 0) /* (V20) MCAN0_RX */ 174 J721E_IOPAD(0x20, PIN_OUTPUT, 0) /* (V18) MCAN0_TX */ 175 >; 176 }; 177}; 178 179&hbmc { 180 /* OSPI and HBMC are muxed inside FSS, Bootloader will enable 181 * appropriate node based on board detection 182 */ 183 status = "disabled"; 184 pinctrl-names = "default"; 185 pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; 186 ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */ 187 <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */ 188 189 flash@0,0 { 190 compatible = "cypress,hyperflash", "cfi-flash"; 191 reg = <0x00 0x00 0x4000000>; 192 bootph-all; 193 194 partitions { 195 compatible = "fixed-partitions"; 196 #address-cells = <1>; 197 #size-cells = <1>; 198 199 partition@0 { 200 label = "hbmc.tiboot3"; 201 reg = <0x0 0x100000>; 202 }; 203 204 partition@100000 { 205 label = "hbmc.tispl"; 206 reg = <0x100000 0x200000>; 207 }; 208 209 partition@300000 { 210 label = "hbmc.u-boot"; 211 reg = <0x300000 0x400000>; 212 }; 213 214 partition@700000 { 215 label = "hbmc.env"; 216 reg = <0x700000 0x40000>; 217 }; 218 219 partition@800000 { 220 label = "hbmc.rootfs"; 221 reg = <0x800000 0x3800000>; 222 }; 223 }; 224 }; 225}; 226 227&mailbox0_cluster0 { 228 status = "okay"; 229 interrupts = <436>; 230 231 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 232 ti,mbox-rx = <0 0 0>; 233 ti,mbox-tx = <1 0 0>; 234 }; 235 236 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 237 ti,mbox-rx = <2 0 0>; 238 ti,mbox-tx = <3 0 0>; 239 }; 240}; 241 242&mailbox0_cluster1 { 243 status = "okay"; 244 interrupts = <432>; 245 246 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 247 ti,mbox-rx = <0 0 0>; 248 ti,mbox-tx = <1 0 0>; 249 }; 250 251 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 252 ti,mbox-rx = <2 0 0>; 253 ti,mbox-tx = <3 0 0>; 254 }; 255}; 256 257&mcu_r5fss0_core0 { 258 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 259 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 260 <&mcu_r5fss0_core0_memory_region>; 261}; 262 263&mcu_r5fss0_core1 { 264 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 265 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 266 <&mcu_r5fss0_core1_memory_region>; 267}; 268 269&main_r5fss0 { 270 ti,cluster-mode = <0>; 271}; 272 273/* Timers are used by Remoteproc firmware */ 274&main_timer0 { 275 status = "reserved"; 276}; 277 278&main_timer1 { 279 status = "reserved"; 280}; 281 282&main_timer2 { 283 status = "reserved"; 284}; 285 286&main_r5fss0_core0 { 287 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 288 memory-region = <&main_r5fss0_core0_dma_memory_region>, 289 <&main_r5fss0_core0_memory_region>; 290}; 291 292&main_r5fss0_core1 { 293 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 294 memory-region = <&main_r5fss0_core1_dma_memory_region>, 295 <&main_r5fss0_core1_memory_region>; 296}; 297 298&main_i2c0 { 299 pinctrl-names = "default"; 300 pinctrl-0 = <&main_i2c0_pins_default>; 301 clock-frequency = <400000>; 302 303 exp_som: gpio@21 { 304 compatible = "ti,tca6408"; 305 reg = <0x21>; 306 gpio-controller; 307 #gpio-cells = <2>; 308 gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0", 309 "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1", 310 "UART/LIN_MUX_SEL", "TRC_D17/AUDIO_REFCLK_SEL", 311 "GPIO_LIN_EN", "CAN_STB"; 312 }; 313}; 314 315&wkup_i2c0 { 316 status = "okay"; 317 pinctrl-names = "default"; 318 pinctrl-0 = <&wkup_i2c0_pins_default>; 319 clock-frequency = <400000>; 320 321 eeprom@50 { 322 compatible = "atmel,24c256"; 323 reg = <0x50>; 324 }; 325 326 tps659414: pmic@48 { 327 compatible = "ti,tps6594-q1"; 328 reg = <0x48>; 329 system-power-controller; 330 pinctrl-names = "default"; 331 pinctrl-0 = <&pmic_irq_pins_default>; 332 interrupt-parent = <&wkup_gpio0>; 333 interrupts = <84 IRQ_TYPE_EDGE_FALLING>; 334 gpio-controller; 335 #gpio-cells = <2>; 336 ti,primary-pmic; 337 buck1-supply = <&vsys_3v3>; 338 buck2-supply = <&vsys_3v3>; 339 buck3-supply = <&vsys_3v3>; 340 buck4-supply = <&vsys_3v3>; 341 buck5-supply = <&vsys_3v3>; 342 ldo1-supply = <&vsys_3v3>; 343 ldo2-supply = <&vsys_3v3>; 344 ldo3-supply = <&vsys_3v3>; 345 ldo4-supply = <&vsys_3v3>; 346 347 regulators { 348 bucka1: buck1 { 349 regulator-name = "vda_mcu_1v8"; 350 regulator-min-microvolt = <1800000>; 351 regulator-max-microvolt = <1800000>; 352 regulator-boot-on; 353 regulator-always-on; 354 bootph-all; 355 }; 356 357 bucka2: buck2 { 358 regulator-name = "vdd_mcuio_1v8"; 359 regulator-min-microvolt = <1800000>; 360 regulator-max-microvolt = <1800000>; 361 regulator-boot-on; 362 regulator-always-on; 363 }; 364 365 bucka3: buck3 { 366 regulator-name = "vdd_mcu_0v85"; 367 regulator-min-microvolt = <850000>; 368 regulator-max-microvolt = <850000>; 369 regulator-boot-on; 370 regulator-always-on; 371 }; 372 373 bucka4: buck4 { 374 regulator-name = "vdd_ddr_1v1"; 375 regulator-min-microvolt = <1100000>; 376 regulator-max-microvolt = <1100000>; 377 regulator-boot-on; 378 regulator-always-on; 379 }; 380 381 bucka5: buck5 { 382 regulator-name = "vdd_phyio_1v8"; 383 regulator-min-microvolt = <1800000>; 384 regulator-max-microvolt = <1800000>; 385 regulator-boot-on; 386 regulator-always-on; 387 }; 388 389 ldoa1: ldo1 { 390 regulator-name = "vdd1_lpddr4_1v8"; 391 regulator-min-microvolt = <1800000>; 392 regulator-max-microvolt = <1800000>; 393 regulator-boot-on; 394 regulator-always-on; 395 }; 396 397 ldoa2: ldo2 { 398 regulator-name = "vda_dll_0v8"; 399 regulator-min-microvolt = <800000>; 400 regulator-max-microvolt = <800000>; 401 regulator-boot-on; 402 regulator-always-on; 403 }; 404 405 ldoa3: ldo3 { 406 regulator-name = "vdd_wk_0v8"; 407 regulator-min-microvolt = <800000>; 408 regulator-max-microvolt = <800000>; 409 regulator-boot-on; 410 regulator-always-on; 411 }; 412 413 ldoa4: ldo4 { 414 regulator-name = "vda_pll_1v8"; 415 regulator-min-microvolt = <1800000>; 416 regulator-max-microvolt = <1800000>; 417 regulator-boot-on; 418 regulator-always-on; 419 }; 420 }; 421 }; 422 423 lp876441: pmic@4c { 424 compatible = "ti,lp8764-q1"; 425 reg = <0x4c>; 426 system-power-controller; 427 interrupt-parent = <&wkup_gpio0>; 428 interrupts = <84 IRQ_TYPE_EDGE_FALLING>; 429 gpio-controller; 430 #gpio-cells = <2>; 431 buck1-supply = <&vsys_3v3>; 432 buck2-supply = <&vsys_3v3>; 433 buck3-supply = <&vsys_3v3>; 434 buck4-supply = <&vsys_3v3>; 435 436 regulators: regulators { 437 buckb1: buck1 { 438 regulator-name = "vdd_cpu_avs"; 439 regulator-min-microvolt = <600000>; 440 regulator-max-microvolt = <900000>; 441 regulator-always-on; 442 regulator-boot-on; 443 bootph-pre-ram; 444 }; 445 446 buckb2: buck2 { 447 regulator-name = "vdd_ram_0v85"; 448 regulator-min-microvolt = <850000>; 449 regulator-max-microvolt = <850000>; 450 regulator-boot-on; 451 regulator-always-on; 452 }; 453 454 buckb3: buck3 { 455 regulator-name = "vdd_core_0v85"; 456 regulator-min-microvolt = <850000>; 457 regulator-max-microvolt = <850000>; 458 regulator-boot-on; 459 regulator-always-on; 460 }; 461 462 buckb4: buck4 { 463 regulator-name = "vdd_io_1v8"; 464 regulator-min-microvolt = <1800000>; 465 regulator-max-microvolt = <1800000>; 466 regulator-boot-on; 467 regulator-always-on; 468 }; 469 }; 470 }; 471}; 472 473&ospi0 { 474 status = "okay"; 475 pinctrl-names = "default"; 476 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 477 478 flash@0 { 479 compatible = "jedec,spi-nor"; 480 reg = <0x0>; 481 spi-tx-bus-width = <8>; 482 spi-rx-bus-width = <8>; 483 spi-max-frequency = <25000000>; 484 cdns,tshsl-ns = <60>; 485 cdns,tsd2d-ns = <60>; 486 cdns,tchsh-ns = <60>; 487 cdns,tslch-ns = <60>; 488 cdns,read-delay = <4>; 489 490 partitions { 491 compatible = "fixed-partitions"; 492 #address-cells = <1>; 493 #size-cells = <1>; 494 495 partition@0 { 496 label = "ospi.tiboot3"; 497 reg = <0x0 0x100000>; 498 }; 499 500 partition@100000 { 501 label = "ospi.tispl"; 502 reg = <0x100000 0x200000>; 503 }; 504 505 partition@300000 { 506 label = "ospi.u-boot"; 507 reg = <0x300000 0x400000>; 508 }; 509 510 partition@700000 { 511 label = "ospi.env"; 512 reg = <0x700000 0x40000>; 513 }; 514 515 partition@740000 { 516 label = "ospi.env.backup"; 517 reg = <0x740000 0x40000>; 518 }; 519 520 partition@800000 { 521 label = "ospi.rootfs"; 522 reg = <0x800000 0x37c0000>; 523 }; 524 525 partition@3fc0000 { 526 label = "ospi.phypattern"; 527 reg = <0x3fc0000 0x40000>; 528 bootph-all; 529 }; 530 }; 531 }; 532}; 533 534&main_mcan0 { 535 status = "okay"; 536 pinctrl-0 = <&main_mcan0_pins_default>; 537 pinctrl-names = "default"; 538 phys = <&transceiver0>; 539}; 540