1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals 4 * 5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu_wakeup { 9 dmsc: system-controller@44083000 { 10 compatible = "ti,k2g-sci"; 11 ti,host-id = <12>; 12 13 mbox-names = "rx", "tx"; 14 15 mboxes = <&secure_proxy_main 11>, 16 <&secure_proxy_main 13>; 17 18 reg-names = "debug_messages"; 19 reg = <0x00 0x44083000 0x00 0x1000>; 20 21 k3_pds: power-controller { 22 compatible = "ti,sci-pm-domain"; 23 #power-domain-cells = <2>; 24 }; 25 26 k3_clks: clock-controller { 27 compatible = "ti,k2g-sci-clk"; 28 #clock-cells = <2>; 29 }; 30 31 k3_reset: reset-controller { 32 compatible = "ti,sci-reset"; 33 #reset-cells = <2>; 34 }; 35 }; 36 37 mcu_timer0: timer@40400000 { 38 status = "reserved"; 39 compatible = "ti,am654-timer"; 40 reg = <0x00 0x40400000 0x00 0x400>; 41 interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; 42 clocks = <&k3_clks 35 1>; 43 clock-names = "fck"; 44 assigned-clocks = <&k3_clks 35 1>; 45 assigned-clock-parents = <&k3_clks 35 2>; 46 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 47 ti,timer-pwm; 48 }; 49 50 mcu_timer1: timer@40410000 { 51 status = "reserved"; 52 compatible = "ti,am654-timer"; 53 reg = <0x00 0x40410000 0x00 0x400>; 54 interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; 55 clocks = <&k3_clks 71 1>; 56 clock-names = "fck"; 57 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>; 58 assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 308 1>; 59 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; 60 ti,timer-pwm; 61 }; 62 63 mcu_timer2: timer@40420000 { 64 status = "reserved"; 65 compatible = "ti,am654-timer"; 66 reg = <0x00 0x40420000 0x00 0x400>; 67 interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>; 68 clocks = <&k3_clks 72 1>; 69 clock-names = "fck"; 70 assigned-clocks = <&k3_clks 72 1>; 71 assigned-clock-parents = <&k3_clks 72 2>; 72 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; 73 ti,timer-pwm; 74 }; 75 76 mcu_timer3: timer@40430000 { 77 status = "reserved"; 78 compatible = "ti,am654-timer"; 79 reg = <0x00 0x40430000 0x00 0x400>; 80 interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>; 81 clocks = <&k3_clks 73 1>; 82 clock-names = "fck"; 83 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>; 84 assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 309 1>; 85 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; 86 ti,timer-pwm; 87 }; 88 89 mcu_timer4: timer@40440000 { 90 status = "reserved"; 91 compatible = "ti,am654-timer"; 92 reg = <0x00 0x40440000 0x00 0x400>; 93 interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>; 94 clocks = <&k3_clks 74 1>; 95 clock-names = "fck"; 96 assigned-clocks = <&k3_clks 74 1>; 97 assigned-clock-parents = <&k3_clks 74 2>; 98 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; 99 ti,timer-pwm; 100 }; 101 102 mcu_timer5: timer@40450000 { 103 status = "reserved"; 104 compatible = "ti,am654-timer"; 105 reg = <0x00 0x40450000 0x00 0x400>; 106 interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>; 107 clocks = <&k3_clks 75 1>; 108 clock-names = "fck"; 109 assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>; 110 assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 310 1>; 111 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 112 ti,timer-pwm; 113 }; 114 115 mcu_timer6: timer@40460000 { 116 status = "reserved"; 117 compatible = "ti,am654-timer"; 118 reg = <0x00 0x40460000 0x00 0x400>; 119 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; 120 clocks = <&k3_clks 76 1>; 121 clock-names = "fck"; 122 assigned-clocks = <&k3_clks 76 1>; 123 assigned-clock-parents = <&k3_clks 76 2>; 124 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 125 ti,timer-pwm; 126 }; 127 128 mcu_timer7: timer@40470000 { 129 status = "reserved"; 130 compatible = "ti,am654-timer"; 131 reg = <0x00 0x40470000 0x00 0x400>; 132 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; 133 clocks = <&k3_clks 77 1>; 134 clock-names = "fck"; 135 assigned-clocks = <&k3_clks 77 1>, <&k3_clks 311 0>; 136 assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 311 1>; 137 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 138 ti,timer-pwm; 139 }; 140 141 mcu_timer8: timer@40480000 { 142 status = "reserved"; 143 compatible = "ti,am654-timer"; 144 reg = <0x00 0x40480000 0x00 0x400>; 145 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; 146 clocks = <&k3_clks 78 1>; 147 clock-names = "fck"; 148 assigned-clocks = <&k3_clks 78 1>; 149 assigned-clock-parents = <&k3_clks 78 2>; 150 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 151 ti,timer-pwm; 152 }; 153 154 mcu_timer9: timer@40490000 { 155 status = "reserved"; 156 compatible = "ti,am654-timer"; 157 reg = <0x00 0x40490000 0x00 0x400>; 158 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; 159 clocks = <&k3_clks 79 1>; 160 clock-names = "fck"; 161 assigned-clocks = <&k3_clks 79 1>, <&k3_clks 312 0>; 162 assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 312 1>; 163 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; 164 ti,timer-pwm; 165 }; 166 167 mcu_conf: syscon@40f00000 { 168 compatible = "syscon", "simple-mfd"; 169 reg = <0x00 0x40f00000 0x00 0x20000>; 170 #address-cells = <1>; 171 #size-cells = <1>; 172 ranges = <0x00 0x00 0x40f00000 0x20000>; 173 174 phy_gmii_sel: phy@4040 { 175 compatible = "ti,am654-phy-gmii-sel"; 176 reg = <0x4040 0x4>; 177 #phy-cells = <1>; 178 }; 179 }; 180 181 chipid@43000014 { 182 compatible = "ti,am654-chipid"; 183 reg = <0x00 0x43000014 0x00 0x4>; 184 }; 185 186 /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ 187 mcu_timerio_input: pinctrl@40f04200 { 188 compatible = "pinctrl-single"; 189 reg = <0x0 0x40f04200 0x0 0x28>; 190 #pinctrl-cells = <1>; 191 pinctrl-single,register-width = <32>; 192 pinctrl-single,function-mask = <0x0000000F>; 193 status = "reserved"; 194 }; 195 196 /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ 197 mcu_timerio_output: pinctrl@40f04280 { 198 compatible = "pinctrl-single"; 199 reg = <0x0 0x40f04280 0x0 0x28>; 200 #pinctrl-cells = <1>; 201 pinctrl-single,register-width = <32>; 202 pinctrl-single,function-mask = <0x0000000F>; 203 status = "reserved"; 204 }; 205 206 wkup_pmx0: pinctrl@4301c000 { 207 compatible = "pinctrl-single"; 208 /* Proxy 0 addressing */ 209 reg = <0x00 0x4301c000 0x00 0x34>; 210 #pinctrl-cells = <1>; 211 pinctrl-single,register-width = <32>; 212 pinctrl-single,function-mask = <0xffffffff>; 213 }; 214 215 wkup_pmx1: pinctrl@4301c038 { 216 compatible = "pinctrl-single"; 217 /* Proxy 0 addressing */ 218 reg = <0x00 0x4301c038 0x00 0x8>; 219 #pinctrl-cells = <1>; 220 pinctrl-single,register-width = <32>; 221 pinctrl-single,function-mask = <0xffffffff>; 222 }; 223 224 wkup_pmx2: pinctrl@4301c068 { 225 compatible = "pinctrl-single"; 226 /* Proxy 0 addressing */ 227 reg = <0x00 0x4301c068 0x00 0xec>; 228 #pinctrl-cells = <1>; 229 pinctrl-single,register-width = <32>; 230 pinctrl-single,function-mask = <0xffffffff>; 231 }; 232 233 wkup_pmx3: pinctrl@4301c174 { 234 compatible = "pinctrl-single"; 235 /* Proxy 0 addressing */ 236 reg = <0x00 0x4301c174 0x00 0x20>; 237 #pinctrl-cells = <1>; 238 pinctrl-single,register-width = <32>; 239 pinctrl-single,function-mask = <0xffffffff>; 240 }; 241 242 mcu_ram: sram@41c00000 { 243 compatible = "mmio-sram"; 244 reg = <0x00 0x41c00000 0x00 0x100000>; 245 ranges = <0x00 0x00 0x41c00000 0x100000>; 246 #address-cells = <1>; 247 #size-cells = <1>; 248 }; 249 250 wkup_uart0: serial@42300000 { 251 compatible = "ti,j721e-uart", "ti,am654-uart"; 252 reg = <0x00 0x42300000 0x00 0x100>; 253 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 254 clock-frequency = <48000000>; 255 current-speed = <115200>; 256 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; 257 clocks = <&k3_clks 287 2>; 258 clock-names = "fclk"; 259 status = "disabled"; 260 }; 261 262 mcu_uart0: serial@40a00000 { 263 compatible = "ti,j721e-uart", "ti,am654-uart"; 264 reg = <0x00 0x40a00000 0x00 0x100>; 265 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 266 clock-frequency = <96000000>; 267 current-speed = <115200>; 268 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 269 clocks = <&k3_clks 149 2>; 270 clock-names = "fclk"; 271 status = "disabled"; 272 }; 273 274 wkup_gpio_intr: interrupt-controller@42200000 { 275 compatible = "ti,sci-intr"; 276 reg = <0x00 0x42200000 0x00 0x400>; 277 ti,intr-trigger-type = <1>; 278 interrupt-controller; 279 interrupt-parent = <&gic500>; 280 #interrupt-cells = <1>; 281 ti,sci = <&dmsc>; 282 ti,sci-dev-id = <137>; 283 ti,interrupt-ranges = <16 960 16>; 284 }; 285 286 wkup_gpio0: gpio@42110000 { 287 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 288 reg = <0x00 0x42110000 0x00 0x100>; 289 gpio-controller; 290 #gpio-cells = <2>; 291 interrupt-parent = <&wkup_gpio_intr>; 292 interrupts = <103>, <104>, <105>, <106>, <107>, <108>; 293 interrupt-controller; 294 #interrupt-cells = <2>; 295 ti,ngpio = <85>; 296 ti,davinci-gpio-unbanked = <0>; 297 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 298 clocks = <&k3_clks 113 0>; 299 clock-names = "gpio"; 300 status = "disabled"; 301 }; 302 303 wkup_gpio1: gpio@42100000 { 304 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 305 reg = <0x00 0x42100000 0x00 0x100>; 306 gpio-controller; 307 #gpio-cells = <2>; 308 interrupt-parent = <&wkup_gpio_intr>; 309 interrupts = <112>, <113>, <114>, <115>, <116>, <117>; 310 interrupt-controller; 311 #interrupt-cells = <2>; 312 ti,ngpio = <85>; 313 ti,davinci-gpio-unbanked = <0>; 314 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 315 clocks = <&k3_clks 114 0>; 316 clock-names = "gpio"; 317 status = "disabled"; 318 }; 319 320 mcu_navss: bus@28380000 { 321 compatible = "simple-mfd"; 322 #address-cells = <2>; 323 #size-cells = <2>; 324 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 325 dma-coherent; 326 dma-ranges; 327 ti,sci-dev-id = <232>; 328 329 mcu_ringacc: ringacc@2b800000 { 330 compatible = "ti,am654-navss-ringacc"; 331 reg = <0x00 0x2b800000 0x00 0x400000>, 332 <0x00 0x2b000000 0x00 0x400000>, 333 <0x00 0x28590000 0x00 0x100>, 334 <0x00 0x2a500000 0x00 0x40000>, 335 <0x00 0x28440000 0x00 0x40000>; 336 reg-names = "rt", "fifos", "proxy_gcfg", 337 "proxy_target", "cfg"; 338 ti,num-rings = <286>; 339 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 340 ti,sci = <&dmsc>; 341 ti,sci-dev-id = <235>; 342 msi-parent = <&main_udmass_inta>; 343 }; 344 345 mcu_udmap: dma-controller@285c0000 { 346 compatible = "ti,j721e-navss-mcu-udmap"; 347 reg = <0x00 0x285c0000 0x00 0x100>, 348 <0x00 0x2a800000 0x00 0x40000>, 349 <0x00 0x2aa00000 0x00 0x40000>; 350 reg-names = "gcfg", "rchanrt", "tchanrt"; 351 msi-parent = <&main_udmass_inta>; 352 #dma-cells = <1>; 353 354 ti,sci = <&dmsc>; 355 ti,sci-dev-id = <236>; 356 ti,ringacc = <&mcu_ringacc>; 357 358 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 359 <0x0f>; /* TX_HCHAN */ 360 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 361 <0x0b>; /* RX_HCHAN */ 362 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 363 }; 364 }; 365 366 secure_proxy_mcu: mailbox@2a480000 { 367 compatible = "ti,am654-secure-proxy"; 368 #mbox-cells = <1>; 369 reg-names = "target_data", "rt", "scfg"; 370 reg = <0x0 0x2a480000 0x0 0x80000>, 371 <0x0 0x2a380000 0x0 0x80000>, 372 <0x0 0x2a400000 0x0 0x80000>; 373 /* 374 * Marked Disabled: 375 * Node is incomplete as it is meant for bootloaders and 376 * firmware on non-MPU processors 377 */ 378 status = "disabled"; 379 }; 380 381 mcu_cpsw: ethernet@46000000 { 382 compatible = "ti,j721e-cpsw-nuss"; 383 #address-cells = <2>; 384 #size-cells = <2>; 385 reg = <0x00 0x46000000 0x00 0x200000>; 386 reg-names = "cpsw_nuss"; 387 ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>; 388 dma-coherent; 389 clocks = <&k3_clks 18 21>; 390 clock-names = "fck"; 391 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; 392 393 dmas = <&mcu_udmap 0xf000>, 394 <&mcu_udmap 0xf001>, 395 <&mcu_udmap 0xf002>, 396 <&mcu_udmap 0xf003>, 397 <&mcu_udmap 0xf004>, 398 <&mcu_udmap 0xf005>, 399 <&mcu_udmap 0xf006>, 400 <&mcu_udmap 0xf007>, 401 <&mcu_udmap 0x7000>; 402 dma-names = "tx0", "tx1", "tx2", "tx3", 403 "tx4", "tx5", "tx6", "tx7", 404 "rx"; 405 406 ethernet-ports { 407 #address-cells = <1>; 408 #size-cells = <0>; 409 410 cpsw_port1: port@1 { 411 reg = <1>; 412 ti,mac-only; 413 label = "port1"; 414 ti,syscon-efuse = <&mcu_conf 0x200>; 415 phys = <&phy_gmii_sel 1>; 416 }; 417 }; 418 419 davinci_mdio: mdio@f00 { 420 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 421 reg = <0x00 0xf00 0x00 0x100>; 422 #address-cells = <1>; 423 #size-cells = <0>; 424 clocks = <&k3_clks 18 21>; 425 clock-names = "fck"; 426 bus_freq = <1000000>; 427 }; 428 429 cpts@3d000 { 430 compatible = "ti,am65-cpts"; 431 reg = <0x00 0x3d000 0x00 0x400>; 432 clocks = <&k3_clks 18 2>; 433 clock-names = "cpts"; 434 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 435 interrupt-names = "cpts"; 436 ti,cpts-ext-ts-inputs = <4>; 437 ti,cpts-periodic-outputs = <2>; 438 }; 439 }; 440 441 mcu_i2c0: i2c@40b00000 { 442 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 443 reg = <0x00 0x40b00000 0x00 0x100>; 444 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 clock-names = "fck"; 448 clocks = <&k3_clks 194 1>; 449 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; 450 status = "disabled"; 451 }; 452 453 mcu_i2c1: i2c@40b10000 { 454 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 455 reg = <0x00 0x40b10000 0x00 0x100>; 456 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 clock-names = "fck"; 460 clocks = <&k3_clks 195 1>; 461 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; 462 status = "disabled"; 463 }; 464 465 wkup_i2c0: i2c@42120000 { 466 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 467 reg = <0x00 0x42120000 0x00 0x100>; 468 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 469 #address-cells = <1>; 470 #size-cells = <0>; 471 clock-names = "fck"; 472 clocks = <&k3_clks 197 1>; 473 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; 474 status = "disabled"; 475 }; 476 477 mcu_spi0: spi@40300000 { 478 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 479 reg = <0x00 0x040300000 0x00 0x400>; 480 interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; 481 #address-cells = <1>; 482 #size-cells = <0>; 483 power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; 484 clocks = <&k3_clks 274 0>; 485 status = "disabled"; 486 }; 487 488 mcu_spi1: spi@40310000 { 489 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 490 reg = <0x00 0x040310000 0x00 0x400>; 491 interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; 492 #address-cells = <1>; 493 #size-cells = <0>; 494 power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; 495 clocks = <&k3_clks 275 0>; 496 status = "disabled"; 497 }; 498 499 mcu_spi2: spi@40320000 { 500 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 501 reg = <0x00 0x040320000 0x00 0x400>; 502 interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 506 clocks = <&k3_clks 276 0>; 507 status = "disabled"; 508 }; 509 510 fss: syscon@47000000 { 511 compatible = "syscon", "simple-mfd"; 512 reg = <0x00 0x47000000 0x00 0x100>; 513 #address-cells = <2>; 514 #size-cells = <2>; 515 ranges; 516 517 hbmc_mux: hbmc-mux { 518 compatible = "mmio-mux"; 519 #mux-control-cells = <1>; 520 mux-reg-masks = <0x4 0x2>; /* HBMC select */ 521 }; 522 523 hbmc: hyperbus@47034000 { 524 compatible = "ti,am654-hbmc"; 525 reg = <0x00 0x47034000 0x00 0x100>, 526 <0x05 0x00000000 0x01 0x0000000>; 527 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 528 clocks = <&k3_clks 102 0>; 529 assigned-clocks = <&k3_clks 102 5>; 530 assigned-clock-rates = <333333333>; 531 #address-cells = <2>; 532 #size-cells = <1>; 533 mux-controls = <&hbmc_mux 0>; 534 }; 535 536 ospi0: spi@47040000 { 537 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 538 reg = <0x0 0x47040000 0x0 0x100>, 539 <0x5 0x00000000 0x1 0x0000000>; 540 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; 541 cdns,fifo-depth = <256>; 542 cdns,fifo-width = <4>; 543 cdns,trigger-address = <0x0>; 544 clocks = <&k3_clks 103 0>; 545 assigned-clocks = <&k3_clks 103 0>; 546 assigned-clock-parents = <&k3_clks 103 2>; 547 assigned-clock-rates = <166666666>; 548 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 status = "disabled"; 552 }; 553 }; 554 555 tscadc0: tscadc@40200000 { 556 compatible = "ti,am3359-tscadc"; 557 reg = <0x00 0x40200000 0x00 0x1000>; 558 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 559 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 560 clocks = <&k3_clks 0 1>; 561 assigned-clocks = <&k3_clks 0 3>; 562 assigned-clock-rates = <60000000>; 563 clock-names = "fck"; 564 dmas = <&main_udmap 0x7400>, 565 <&main_udmap 0x7401>; 566 dma-names = "fifo0", "fifo1"; 567 568 adc { 569 #io-channel-cells = <1>; 570 compatible = "ti,am3359-adc"; 571 }; 572 }; 573 574 mcu_r5fss0: r5fss@41000000 { 575 compatible = "ti,j7200-r5fss"; 576 ti,cluster-mode = <1>; 577 #address-cells = <1>; 578 #size-cells = <1>; 579 ranges = <0x41000000 0x00 0x41000000 0x20000>, 580 <0x41400000 0x00 0x41400000 0x20000>; 581 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 582 583 mcu_r5fss0_core0: r5f@41000000 { 584 compatible = "ti,j7200-r5f"; 585 reg = <0x41000000 0x00010000>, 586 <0x41010000 0x00010000>; 587 reg-names = "atcm", "btcm"; 588 ti,sci = <&dmsc>; 589 ti,sci-dev-id = <250>; 590 ti,sci-proc-ids = <0x01 0xff>; 591 resets = <&k3_reset 250 1>; 592 firmware-name = "j7200-mcu-r5f0_0-fw"; 593 ti,atcm-enable = <1>; 594 ti,btcm-enable = <1>; 595 ti,loczrama = <1>; 596 }; 597 598 mcu_r5fss0_core1: r5f@41400000 { 599 compatible = "ti,j7200-r5f"; 600 reg = <0x41400000 0x00008000>, 601 <0x41410000 0x00008000>; 602 reg-names = "atcm", "btcm"; 603 ti,sci = <&dmsc>; 604 ti,sci-dev-id = <251>; 605 ti,sci-proc-ids = <0x02 0xff>; 606 resets = <&k3_reset 251 1>; 607 firmware-name = "j7200-mcu-r5f0_1-fw"; 608 ti,atcm-enable = <1>; 609 ti,btcm-enable = <1>; 610 ti,loczrama = <1>; 611 }; 612 }; 613 614 mcu_crypto: crypto@40900000 { 615 compatible = "ti,j721e-sa2ul"; 616 reg = <0x00 0x40900000 0x00 0x1200>; 617 power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>; 618 #address-cells = <2>; 619 #size-cells = <2>; 620 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; 621 dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>, 622 <&mcu_udmap 0x7503>; 623 dma-names = "tx", "rx1", "rx2"; 624 625 rng: rng@40910000 { 626 compatible = "inside-secure,safexcel-eip76"; 627 reg = <0x00 0x40910000 0x00 0x7d>; 628 interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>; 629 status = "disabled"; /* Used by OP-TEE */ 630 }; 631 }; 632 633 wkup_vtm0: temperature-sensor@42040000 { 634 compatible = "ti,j7200-vtm"; 635 reg = <0x00 0x42040000 0x00 0x350>, 636 <0x00 0x42050000 0x00 0x350>; 637 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 638 #thermal-sensor-cells = <1>; 639 }; 640}; 641