1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals 4 * 5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu_wakeup { 9 dmsc: system-controller@44083000 { 10 compatible = "ti,k2g-sci"; 11 ti,host-id = <12>; 12 13 mbox-names = "rx", "tx"; 14 15 mboxes = <&secure_proxy_main 11>, 16 <&secure_proxy_main 13>; 17 18 reg-names = "debug_messages"; 19 reg = <0x00 0x44083000 0x00 0x1000>; 20 21 k3_pds: power-controller { 22 compatible = "ti,sci-pm-domain"; 23 #power-domain-cells = <2>; 24 }; 25 26 k3_clks: clock-controller { 27 compatible = "ti,k2g-sci-clk"; 28 #clock-cells = <2>; 29 }; 30 31 k3_reset: reset-controller { 32 compatible = "ti,sci-reset"; 33 #reset-cells = <2>; 34 }; 35 }; 36 37 mcu_timer0: timer@40400000 { 38 status = "reserved"; 39 compatible = "ti,am654-timer"; 40 reg = <0x00 0x40400000 0x00 0x400>; 41 interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; 42 clocks = <&k3_clks 35 1>; 43 clock-names = "fck"; 44 assigned-clocks = <&k3_clks 35 1>; 45 assigned-clock-parents = <&k3_clks 35 2>; 46 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 47 ti,timer-pwm; 48 }; 49 50 mcu_timer1: timer@40410000 { 51 status = "reserved"; 52 compatible = "ti,am654-timer"; 53 reg = <0x00 0x40410000 0x00 0x400>; 54 interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; 55 clocks = <&k3_clks 71 1>; 56 clock-names = "fck"; 57 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>; 58 assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 308 1>; 59 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; 60 ti,timer-pwm; 61 }; 62 63 mcu_timer2: timer@40420000 { 64 status = "reserved"; 65 compatible = "ti,am654-timer"; 66 reg = <0x00 0x40420000 0x00 0x400>; 67 interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>; 68 clocks = <&k3_clks 72 1>; 69 clock-names = "fck"; 70 assigned-clocks = <&k3_clks 72 1>; 71 assigned-clock-parents = <&k3_clks 72 2>; 72 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; 73 ti,timer-pwm; 74 }; 75 76 mcu_timer3: timer@40430000 { 77 status = "reserved"; 78 compatible = "ti,am654-timer"; 79 reg = <0x00 0x40430000 0x00 0x400>; 80 interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>; 81 clocks = <&k3_clks 73 1>; 82 clock-names = "fck"; 83 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>; 84 assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 309 1>; 85 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; 86 ti,timer-pwm; 87 }; 88 89 mcu_timer4: timer@40440000 { 90 status = "reserved"; 91 compatible = "ti,am654-timer"; 92 reg = <0x00 0x40440000 0x00 0x400>; 93 interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>; 94 clocks = <&k3_clks 74 1>; 95 clock-names = "fck"; 96 assigned-clocks = <&k3_clks 74 1>; 97 assigned-clock-parents = <&k3_clks 74 2>; 98 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; 99 ti,timer-pwm; 100 }; 101 102 mcu_timer5: timer@40450000 { 103 status = "reserved"; 104 compatible = "ti,am654-timer"; 105 reg = <0x00 0x40450000 0x00 0x400>; 106 interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>; 107 clocks = <&k3_clks 75 1>; 108 clock-names = "fck"; 109 assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>; 110 assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 310 1>; 111 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 112 ti,timer-pwm; 113 }; 114 115 mcu_timer6: timer@40460000 { 116 status = "reserved"; 117 compatible = "ti,am654-timer"; 118 reg = <0x00 0x40460000 0x00 0x400>; 119 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; 120 clocks = <&k3_clks 76 1>; 121 clock-names = "fck"; 122 assigned-clocks = <&k3_clks 76 1>; 123 assigned-clock-parents = <&k3_clks 76 2>; 124 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 125 ti,timer-pwm; 126 }; 127 128 mcu_timer7: timer@40470000 { 129 status = "reserved"; 130 compatible = "ti,am654-timer"; 131 reg = <0x00 0x40470000 0x00 0x400>; 132 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; 133 clocks = <&k3_clks 77 1>; 134 clock-names = "fck"; 135 assigned-clocks = <&k3_clks 77 1>, <&k3_clks 311 0>; 136 assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 311 1>; 137 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 138 ti,timer-pwm; 139 }; 140 141 mcu_timer8: timer@40480000 { 142 status = "reserved"; 143 compatible = "ti,am654-timer"; 144 reg = <0x00 0x40480000 0x00 0x400>; 145 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; 146 clocks = <&k3_clks 78 1>; 147 clock-names = "fck"; 148 assigned-clocks = <&k3_clks 78 1>; 149 assigned-clock-parents = <&k3_clks 78 2>; 150 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 151 ti,timer-pwm; 152 }; 153 154 mcu_timer9: timer@40490000 { 155 status = "reserved"; 156 compatible = "ti,am654-timer"; 157 reg = <0x00 0x40490000 0x00 0x400>; 158 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; 159 clocks = <&k3_clks 79 1>; 160 clock-names = "fck"; 161 assigned-clocks = <&k3_clks 79 1>, <&k3_clks 312 0>; 162 assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 312 1>; 163 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; 164 ti,timer-pwm; 165 }; 166 167 mcu_conf: syscon@40f00000 { 168 compatible = "syscon", "simple-mfd"; 169 reg = <0x00 0x40f00000 0x00 0x20000>; 170 #address-cells = <1>; 171 #size-cells = <1>; 172 ranges = <0x00 0x00 0x40f00000 0x20000>; 173 174 phy_gmii_sel: phy@4040 { 175 compatible = "ti,am654-phy-gmii-sel"; 176 reg = <0x4040 0x4>; 177 #phy-cells = <1>; 178 }; 179 }; 180 181 wkup_conf: bus@43000000 { 182 compatible = "simple-bus"; 183 #address-cells = <1>; 184 #size-cells = <1>; 185 ranges = <0x0 0x00 0x43000000 0x20000>; 186 187 chipid: chipid@14 { 188 compatible = "ti,am654-chipid"; 189 reg = <0x14 0x4>; 190 }; 191 }; 192 193 /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ 194 mcu_timerio_input: pinctrl@40f04200 { 195 compatible = "ti,j7200-padconf", "pinctrl-single"; 196 reg = <0x0 0x40f04200 0x0 0x28>; 197 #pinctrl-cells = <1>; 198 pinctrl-single,register-width = <32>; 199 pinctrl-single,function-mask = <0x0000000F>; 200 status = "reserved"; 201 }; 202 203 /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ 204 mcu_timerio_output: pinctrl@40f04280 { 205 compatible = "ti,j7200-padconf", "pinctrl-single"; 206 reg = <0x0 0x40f04280 0x0 0x28>; 207 #pinctrl-cells = <1>; 208 pinctrl-single,register-width = <32>; 209 pinctrl-single,function-mask = <0x0000000F>; 210 status = "reserved"; 211 }; 212 213 wkup_pmx0: pinctrl@4301c000 { 214 compatible = "ti,j7200-padconf", "pinctrl-single"; 215 /* Proxy 0 addressing */ 216 reg = <0x00 0x4301c000 0x00 0x34>; 217 #pinctrl-cells = <1>; 218 pinctrl-single,register-width = <32>; 219 pinctrl-single,function-mask = <0xffffffff>; 220 }; 221 222 wkup_pmx1: pinctrl@4301c038 { 223 compatible = "ti,j7200-padconf", "pinctrl-single"; 224 /* Proxy 0 addressing */ 225 reg = <0x00 0x4301c038 0x00 0x8>; 226 #pinctrl-cells = <1>; 227 pinctrl-single,register-width = <32>; 228 pinctrl-single,function-mask = <0xffffffff>; 229 }; 230 231 wkup_pmx2: pinctrl@4301c068 { 232 compatible = "ti,j7200-padconf", "pinctrl-single"; 233 /* Proxy 0 addressing */ 234 reg = <0x00 0x4301c068 0x00 0xec>; 235 #pinctrl-cells = <1>; 236 pinctrl-single,register-width = <32>; 237 pinctrl-single,function-mask = <0xffffffff>; 238 }; 239 240 wkup_pmx3: pinctrl@4301c174 { 241 compatible = "ti,j7200-padconf", "pinctrl-single"; 242 /* Proxy 0 addressing */ 243 reg = <0x00 0x4301c174 0x00 0x20>; 244 #pinctrl-cells = <1>; 245 pinctrl-single,register-width = <32>; 246 pinctrl-single,function-mask = <0xffffffff>; 247 }; 248 249 mcu_ram: sram@41c00000 { 250 compatible = "mmio-sram"; 251 reg = <0x00 0x41c00000 0x00 0x100000>; 252 ranges = <0x00 0x00 0x41c00000 0x100000>; 253 #address-cells = <1>; 254 #size-cells = <1>; 255 }; 256 257 wkup_uart0: serial@42300000 { 258 compatible = "ti,j721e-uart", "ti,am654-uart"; 259 reg = <0x00 0x42300000 0x00 0x100>; 260 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 261 clock-frequency = <48000000>; 262 current-speed = <115200>; 263 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; 264 clocks = <&k3_clks 287 2>; 265 clock-names = "fclk"; 266 status = "disabled"; 267 }; 268 269 mcu_uart0: serial@40a00000 { 270 compatible = "ti,j721e-uart", "ti,am654-uart"; 271 reg = <0x00 0x40a00000 0x00 0x100>; 272 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 273 clock-frequency = <96000000>; 274 current-speed = <115200>; 275 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 276 clocks = <&k3_clks 149 2>; 277 clock-names = "fclk"; 278 status = "disabled"; 279 }; 280 281 wkup_gpio_intr: interrupt-controller@42200000 { 282 compatible = "ti,sci-intr"; 283 reg = <0x00 0x42200000 0x00 0x400>; 284 ti,intr-trigger-type = <1>; 285 interrupt-controller; 286 interrupt-parent = <&gic500>; 287 #interrupt-cells = <1>; 288 ti,sci = <&dmsc>; 289 ti,sci-dev-id = <137>; 290 ti,interrupt-ranges = <16 960 16>; 291 }; 292 293 wkup_gpio0: gpio@42110000 { 294 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 295 reg = <0x00 0x42110000 0x00 0x100>; 296 gpio-controller; 297 #gpio-cells = <2>; 298 interrupt-parent = <&wkup_gpio_intr>; 299 interrupts = <103>, <104>, <105>, <106>, <107>, <108>; 300 interrupt-controller; 301 #interrupt-cells = <2>; 302 ti,ngpio = <85>; 303 ti,davinci-gpio-unbanked = <0>; 304 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 305 clocks = <&k3_clks 113 0>; 306 clock-names = "gpio"; 307 status = "disabled"; 308 }; 309 310 wkup_gpio1: gpio@42100000 { 311 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 312 reg = <0x00 0x42100000 0x00 0x100>; 313 gpio-controller; 314 #gpio-cells = <2>; 315 interrupt-parent = <&wkup_gpio_intr>; 316 interrupts = <112>, <113>, <114>, <115>, <116>, <117>; 317 interrupt-controller; 318 #interrupt-cells = <2>; 319 ti,ngpio = <85>; 320 ti,davinci-gpio-unbanked = <0>; 321 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 322 clocks = <&k3_clks 114 0>; 323 clock-names = "gpio"; 324 status = "disabled"; 325 }; 326 327 mcu_navss: bus@28380000 { 328 compatible = "simple-bus"; 329 #address-cells = <2>; 330 #size-cells = <2>; 331 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 332 dma-coherent; 333 dma-ranges; 334 ti,sci-dev-id = <232>; 335 336 mcu_ringacc: ringacc@2b800000 { 337 compatible = "ti,am654-navss-ringacc"; 338 reg = <0x00 0x2b800000 0x00 0x400000>, 339 <0x00 0x2b000000 0x00 0x400000>, 340 <0x00 0x28590000 0x00 0x100>, 341 <0x00 0x2a500000 0x00 0x40000>, 342 <0x00 0x28440000 0x00 0x40000>; 343 reg-names = "rt", "fifos", "proxy_gcfg", 344 "proxy_target", "cfg"; 345 ti,num-rings = <286>; 346 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 347 ti,sci = <&dmsc>; 348 ti,sci-dev-id = <235>; 349 msi-parent = <&main_udmass_inta>; 350 }; 351 352 mcu_udmap: dma-controller@285c0000 { 353 compatible = "ti,j721e-navss-mcu-udmap"; 354 reg = <0x00 0x285c0000 0x00 0x100>, 355 <0x00 0x2a800000 0x00 0x40000>, 356 <0x00 0x2aa00000 0x00 0x40000>, 357 <0x00 0x284a0000 0x00 0x4000>, 358 <0x00 0x284c0000 0x00 0x4000>, 359 <0x00 0x28400000 0x00 0x2000>; 360 reg-names = "gcfg", "rchanrt", "tchanrt", 361 "tchan", "rchan", "rflow"; 362 msi-parent = <&main_udmass_inta>; 363 #dma-cells = <1>; 364 365 ti,sci = <&dmsc>; 366 ti,sci-dev-id = <236>; 367 ti,ringacc = <&mcu_ringacc>; 368 369 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 370 <0x0f>; /* TX_HCHAN */ 371 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 372 <0x0b>; /* RX_HCHAN */ 373 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 374 }; 375 }; 376 377 secure_proxy_mcu: mailbox@2a480000 { 378 compatible = "ti,am654-secure-proxy"; 379 #mbox-cells = <1>; 380 reg-names = "target_data", "rt", "scfg"; 381 reg = <0x0 0x2a480000 0x0 0x80000>, 382 <0x0 0x2a380000 0x0 0x80000>, 383 <0x0 0x2a400000 0x0 0x80000>; 384 /* 385 * Marked Disabled: 386 * Node is incomplete as it is meant for bootloaders and 387 * firmware on non-MPU processors 388 */ 389 status = "disabled"; 390 }; 391 392 mcu_cpsw: ethernet@46000000 { 393 compatible = "ti,j721e-cpsw-nuss"; 394 #address-cells = <2>; 395 #size-cells = <2>; 396 reg = <0x00 0x46000000 0x00 0x200000>; 397 reg-names = "cpsw_nuss"; 398 ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>; 399 dma-coherent; 400 clocks = <&k3_clks 18 21>; 401 clock-names = "fck"; 402 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; 403 404 dmas = <&mcu_udmap 0xf000>, 405 <&mcu_udmap 0xf001>, 406 <&mcu_udmap 0xf002>, 407 <&mcu_udmap 0xf003>, 408 <&mcu_udmap 0xf004>, 409 <&mcu_udmap 0xf005>, 410 <&mcu_udmap 0xf006>, 411 <&mcu_udmap 0xf007>, 412 <&mcu_udmap 0x7000>; 413 dma-names = "tx0", "tx1", "tx2", "tx3", 414 "tx4", "tx5", "tx6", "tx7", 415 "rx"; 416 417 ethernet-ports { 418 #address-cells = <1>; 419 #size-cells = <0>; 420 421 cpsw_port1: port@1 { 422 reg = <1>; 423 ti,mac-only; 424 label = "port1"; 425 ti,syscon-efuse = <&mcu_conf 0x200>; 426 phys = <&phy_gmii_sel 1>; 427 }; 428 }; 429 430 davinci_mdio: mdio@f00 { 431 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 432 reg = <0x00 0xf00 0x00 0x100>; 433 #address-cells = <1>; 434 #size-cells = <0>; 435 clocks = <&k3_clks 18 21>; 436 clock-names = "fck"; 437 bus_freq = <1000000>; 438 }; 439 440 cpts@3d000 { 441 compatible = "ti,am65-cpts"; 442 reg = <0x00 0x3d000 0x00 0x400>; 443 clocks = <&k3_clks 18 2>; 444 clock-names = "cpts"; 445 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 446 interrupt-names = "cpts"; 447 ti,cpts-ext-ts-inputs = <4>; 448 ti,cpts-periodic-outputs = <2>; 449 }; 450 }; 451 452 mcu_i2c0: i2c@40b00000 { 453 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 454 reg = <0x00 0x40b00000 0x00 0x100>; 455 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 456 #address-cells = <1>; 457 #size-cells = <0>; 458 clock-names = "fck"; 459 clocks = <&k3_clks 194 1>; 460 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; 461 status = "disabled"; 462 }; 463 464 mcu_i2c1: i2c@40b10000 { 465 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 466 reg = <0x00 0x40b10000 0x00 0x100>; 467 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; 468 #address-cells = <1>; 469 #size-cells = <0>; 470 clock-names = "fck"; 471 clocks = <&k3_clks 195 1>; 472 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; 473 status = "disabled"; 474 }; 475 476 wkup_i2c0: i2c@42120000 { 477 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 478 reg = <0x00 0x42120000 0x00 0x100>; 479 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 480 #address-cells = <1>; 481 #size-cells = <0>; 482 clock-names = "fck"; 483 clocks = <&k3_clks 197 1>; 484 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; 485 status = "disabled"; 486 }; 487 488 mcu_spi0: spi@40300000 { 489 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 490 reg = <0x00 0x040300000 0x00 0x400>; 491 interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; 492 #address-cells = <1>; 493 #size-cells = <0>; 494 power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; 495 clocks = <&k3_clks 274 0>; 496 status = "disabled"; 497 }; 498 499 mcu_spi1: spi@40310000 { 500 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 501 reg = <0x00 0x040310000 0x00 0x400>; 502 interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; 506 clocks = <&k3_clks 275 0>; 507 status = "disabled"; 508 }; 509 510 mcu_spi2: spi@40320000 { 511 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 512 reg = <0x00 0x040320000 0x00 0x400>; 513 interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 517 clocks = <&k3_clks 276 0>; 518 status = "disabled"; 519 }; 520 521 fss: bus@47000000 { 522 compatible = "simple-bus"; 523 reg = <0x00 0x47000000 0x00 0x100>; 524 #address-cells = <2>; 525 #size-cells = <2>; 526 ranges; 527 528 hbmc_mux: mux-controller@47000004 { 529 compatible = "reg-mux"; 530 reg = <0x00 0x47000004 0x00 0x4>; 531 #mux-control-cells = <1>; 532 mux-reg-masks = <0x0 0x2>; /* HBMC select */ 533 }; 534 535 hbmc: hyperbus@47034000 { 536 compatible = "ti,am654-hbmc"; 537 reg = <0x00 0x47034000 0x00 0x100>, 538 <0x05 0x00000000 0x01 0x0000000>; 539 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 540 clocks = <&k3_clks 102 0>; 541 assigned-clocks = <&k3_clks 102 5>; 542 assigned-clock-rates = <333333333>; 543 #address-cells = <2>; 544 #size-cells = <1>; 545 mux-controls = <&hbmc_mux 0>; 546 }; 547 548 ospi0: spi@47040000 { 549 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 550 reg = <0x0 0x47040000 0x0 0x100>, 551 <0x5 0x00000000 0x1 0x0000000>; 552 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; 553 cdns,fifo-depth = <256>; 554 cdns,fifo-width = <4>; 555 cdns,trigger-address = <0x0>; 556 clocks = <&k3_clks 103 0>; 557 assigned-clocks = <&k3_clks 103 0>; 558 assigned-clock-parents = <&k3_clks 103 2>; 559 assigned-clock-rates = <166666666>; 560 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 561 #address-cells = <1>; 562 #size-cells = <0>; 563 status = "disabled"; 564 }; 565 }; 566 567 tscadc0: tscadc@40200000 { 568 compatible = "ti,am3359-tscadc"; 569 reg = <0x00 0x40200000 0x00 0x1000>; 570 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 571 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 572 clocks = <&k3_clks 0 1>; 573 assigned-clocks = <&k3_clks 0 3>; 574 assigned-clock-rates = <60000000>; 575 clock-names = "fck"; 576 dmas = <&main_udmap 0x7400>, 577 <&main_udmap 0x7401>; 578 dma-names = "fifo0", "fifo1"; 579 580 adc { 581 #io-channel-cells = <1>; 582 compatible = "ti,am3359-adc"; 583 }; 584 }; 585 586 mcu_r5fss0: r5fss@41000000 { 587 compatible = "ti,j7200-r5fss"; 588 ti,cluster-mode = <1>; 589 #address-cells = <1>; 590 #size-cells = <1>; 591 ranges = <0x41000000 0x00 0x41000000 0x20000>, 592 <0x41400000 0x00 0x41400000 0x20000>; 593 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 594 595 mcu_r5fss0_core0: r5f@41000000 { 596 compatible = "ti,j7200-r5f"; 597 reg = <0x41000000 0x00010000>, 598 <0x41010000 0x00010000>; 599 reg-names = "atcm", "btcm"; 600 ti,sci = <&dmsc>; 601 ti,sci-dev-id = <250>; 602 ti,sci-proc-ids = <0x01 0xff>; 603 resets = <&k3_reset 250 1>; 604 firmware-name = "j7200-mcu-r5f0_0-fw"; 605 ti,atcm-enable = <1>; 606 ti,btcm-enable = <1>; 607 ti,loczrama = <1>; 608 }; 609 610 mcu_r5fss0_core1: r5f@41400000 { 611 compatible = "ti,j7200-r5f"; 612 reg = <0x41400000 0x00008000>, 613 <0x41410000 0x00008000>; 614 reg-names = "atcm", "btcm"; 615 ti,sci = <&dmsc>; 616 ti,sci-dev-id = <251>; 617 ti,sci-proc-ids = <0x02 0xff>; 618 resets = <&k3_reset 251 1>; 619 firmware-name = "j7200-mcu-r5f0_1-fw"; 620 ti,atcm-enable = <1>; 621 ti,btcm-enable = <1>; 622 ti,loczrama = <1>; 623 }; 624 }; 625 626 mcu_crypto: crypto@40900000 { 627 compatible = "ti,j721e-sa2ul"; 628 reg = <0x00 0x40900000 0x00 0x1200>; 629 power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>; 630 #address-cells = <2>; 631 #size-cells = <2>; 632 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; 633 dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>, 634 <&mcu_udmap 0x7503>; 635 dma-names = "tx", "rx1", "rx2"; 636 637 rng: rng@40910000 { 638 compatible = "inside-secure,safexcel-eip76"; 639 reg = <0x00 0x40910000 0x00 0x7d>; 640 interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>; 641 status = "disabled"; /* Used by OP-TEE */ 642 }; 643 }; 644 645 wkup_vtm0: temperature-sensor@42040000 { 646 compatible = "ti,j7200-vtm"; 647 reg = <0x00 0x42040000 0x00 0x350>, 648 <0x00 0x42050000 0x00 0x350>; 649 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 650 #thermal-sensor-cells = <1>; 651 }; 652 653 mcu_esm: esm@40800000 { 654 compatible = "ti,j721e-esm"; 655 reg = <0x00 0x40800000 0x00 0x1000>; 656 ti,esm-pins = <95>; 657 bootph-pre-ram; 658 }; 659 660 mcu_mcan0: can@40528000 { 661 compatible = "bosch,m_can"; 662 reg = <0x00 0x40528000 0x00 0x200>, 663 <0x00 0x40500000 0x00 0x8000>; 664 reg-names = "m_can", "message_ram"; 665 power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>; 666 clocks = <&k3_clks 172 0>, <&k3_clks 172 2>; 667 clock-names = "hclk", "cclk"; 668 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 670 interrupt-names = "int0", "int1"; 671 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 672 status = "disabled"; 673 }; 674 675 mcu_mcan1: can@40568000 { 676 compatible = "bosch,m_can"; 677 reg = <0x00 0x40568000 0x00 0x200>, 678 <0x00 0x40540000 0x00 0x8000>; 679 reg-names = "m_can", "message_ram"; 680 power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>; 681 clocks = <&k3_clks 173 0>, <&k3_clks 173 2>; 682 clock-names = "hclk", "cclk"; 683 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 685 interrupt-names = "int0", "int1"; 686 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 687 status = "disabled"; 688 }; 689}; 690