1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals 4 * 5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu_wakeup { 9 dmsc: system-controller@44083000 { 10 compatible = "ti,k2g-sci"; 11 ti,host-id = <12>; 12 13 mbox-names = "rx", "tx"; 14 15 mboxes = <&secure_proxy_main 11>, 16 <&secure_proxy_main 13>; 17 18 reg-names = "debug_messages"; 19 reg = <0x00 0x44083000 0x00 0x1000>; 20 21 k3_pds: power-controller { 22 compatible = "ti,sci-pm-domain"; 23 #power-domain-cells = <2>; 24 bootph-all; 25 }; 26 27 k3_clks: clock-controller { 28 compatible = "ti,k2g-sci-clk"; 29 #clock-cells = <2>; 30 bootph-all; 31 }; 32 33 k3_reset: reset-controller { 34 compatible = "ti,sci-reset"; 35 #reset-cells = <2>; 36 bootph-all; 37 }; 38 }; 39 40 mcu_timer0: timer@40400000 { 41 status = "reserved"; 42 compatible = "ti,am654-timer"; 43 reg = <0x00 0x40400000 0x00 0x400>; 44 interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; 45 clocks = <&k3_clks 35 1>; 46 clock-names = "fck"; 47 assigned-clocks = <&k3_clks 35 1>; 48 assigned-clock-parents = <&k3_clks 35 2>; 49 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 50 bootph-pre-ram; 51 ti,timer-pwm; 52 }; 53 54 mcu_timer1: timer@40410000 { 55 status = "reserved"; 56 compatible = "ti,am654-timer"; 57 reg = <0x00 0x40410000 0x00 0x400>; 58 interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; 59 clocks = <&k3_clks 71 1>; 60 clock-names = "fck"; 61 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>; 62 assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 308 1>; 63 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; 64 ti,timer-pwm; 65 }; 66 67 mcu_timer2: timer@40420000 { 68 status = "reserved"; 69 compatible = "ti,am654-timer"; 70 reg = <0x00 0x40420000 0x00 0x400>; 71 interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>; 72 clocks = <&k3_clks 72 1>; 73 clock-names = "fck"; 74 assigned-clocks = <&k3_clks 72 1>; 75 assigned-clock-parents = <&k3_clks 72 2>; 76 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; 77 ti,timer-pwm; 78 }; 79 80 mcu_timer3: timer@40430000 { 81 status = "reserved"; 82 compatible = "ti,am654-timer"; 83 reg = <0x00 0x40430000 0x00 0x400>; 84 interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>; 85 clocks = <&k3_clks 73 1>; 86 clock-names = "fck"; 87 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>; 88 assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 309 1>; 89 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; 90 ti,timer-pwm; 91 }; 92 93 mcu_timer4: timer@40440000 { 94 status = "reserved"; 95 compatible = "ti,am654-timer"; 96 reg = <0x00 0x40440000 0x00 0x400>; 97 interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>; 98 clocks = <&k3_clks 74 1>; 99 clock-names = "fck"; 100 assigned-clocks = <&k3_clks 74 1>; 101 assigned-clock-parents = <&k3_clks 74 2>; 102 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; 103 ti,timer-pwm; 104 }; 105 106 mcu_timer5: timer@40450000 { 107 status = "reserved"; 108 compatible = "ti,am654-timer"; 109 reg = <0x00 0x40450000 0x00 0x400>; 110 interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>; 111 clocks = <&k3_clks 75 1>; 112 clock-names = "fck"; 113 assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>; 114 assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 310 1>; 115 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 116 ti,timer-pwm; 117 }; 118 119 mcu_timer6: timer@40460000 { 120 status = "reserved"; 121 compatible = "ti,am654-timer"; 122 reg = <0x00 0x40460000 0x00 0x400>; 123 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; 124 clocks = <&k3_clks 76 1>; 125 clock-names = "fck"; 126 assigned-clocks = <&k3_clks 76 1>; 127 assigned-clock-parents = <&k3_clks 76 2>; 128 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 129 ti,timer-pwm; 130 }; 131 132 mcu_timer7: timer@40470000 { 133 status = "reserved"; 134 compatible = "ti,am654-timer"; 135 reg = <0x00 0x40470000 0x00 0x400>; 136 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; 137 clocks = <&k3_clks 77 1>; 138 clock-names = "fck"; 139 assigned-clocks = <&k3_clks 77 1>, <&k3_clks 311 0>; 140 assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 311 1>; 141 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 142 ti,timer-pwm; 143 }; 144 145 mcu_timer8: timer@40480000 { 146 status = "reserved"; 147 compatible = "ti,am654-timer"; 148 reg = <0x00 0x40480000 0x00 0x400>; 149 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; 150 clocks = <&k3_clks 78 1>; 151 clock-names = "fck"; 152 assigned-clocks = <&k3_clks 78 1>; 153 assigned-clock-parents = <&k3_clks 78 2>; 154 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 155 ti,timer-pwm; 156 }; 157 158 mcu_timer9: timer@40490000 { 159 status = "reserved"; 160 compatible = "ti,am654-timer"; 161 reg = <0x00 0x40490000 0x00 0x400>; 162 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; 163 clocks = <&k3_clks 79 1>; 164 clock-names = "fck"; 165 assigned-clocks = <&k3_clks 79 1>, <&k3_clks 312 0>; 166 assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 312 1>; 167 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; 168 ti,timer-pwm; 169 }; 170 171 mcu_conf: bus@40f00000 { 172 compatible = "simple-bus"; 173 #address-cells = <1>; 174 #size-cells = <1>; 175 ranges = <0x0 0x0 0x40f00000 0x20000>; 176 177 cpsw_mac_syscon: ethernet-mac-syscon@200 { 178 compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; 179 reg = <0x200 0x8>; 180 }; 181 182 phy_gmii_sel: phy@4040 { 183 compatible = "ti,am654-phy-gmii-sel"; 184 reg = <0x4040 0x4>; 185 #phy-cells = <1>; 186 }; 187 }; 188 189 wkup_conf: bus@43000000 { 190 compatible = "simple-bus"; 191 #address-cells = <1>; 192 #size-cells = <1>; 193 ranges = <0x0 0x00 0x43000000 0x20000>; 194 195 chipid: chipid@14 { 196 compatible = "ti,am654-chipid"; 197 reg = <0x14 0x4>; 198 bootph-all; 199 }; 200 }; 201 202 /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ 203 mcu_timerio_input: pinctrl@40f04200 { 204 compatible = "ti,j7200-padconf", "pinctrl-single"; 205 reg = <0x0 0x40f04200 0x0 0x28>; 206 #pinctrl-cells = <1>; 207 pinctrl-single,register-width = <32>; 208 pinctrl-single,function-mask = <0x0000000F>; 209 status = "reserved"; 210 }; 211 212 /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ 213 mcu_timerio_output: pinctrl@40f04280 { 214 compatible = "ti,j7200-padconf", "pinctrl-single"; 215 reg = <0x0 0x40f04280 0x0 0x28>; 216 #pinctrl-cells = <1>; 217 pinctrl-single,register-width = <32>; 218 pinctrl-single,function-mask = <0x0000000F>; 219 status = "reserved"; 220 }; 221 222 wkup_pmx0: pinctrl@4301c000 { 223 compatible = "ti,j7200-padconf", "pinctrl-single"; 224 /* Proxy 0 addressing */ 225 reg = <0x00 0x4301c000 0x00 0x34>; 226 #pinctrl-cells = <1>; 227 pinctrl-single,register-width = <32>; 228 pinctrl-single,function-mask = <0xffffffff>; 229 }; 230 231 wkup_pmx1: pinctrl@4301c038 { 232 compatible = "ti,j7200-padconf", "pinctrl-single"; 233 /* Proxy 0 addressing */ 234 reg = <0x00 0x4301c038 0x00 0x8>; 235 #pinctrl-cells = <1>; 236 pinctrl-single,register-width = <32>; 237 pinctrl-single,function-mask = <0xffffffff>; 238 }; 239 240 wkup_pmx2: pinctrl@4301c068 { 241 compatible = "ti,j7200-padconf", "pinctrl-single"; 242 /* Proxy 0 addressing */ 243 reg = <0x00 0x4301c068 0x00 0xec>; 244 #pinctrl-cells = <1>; 245 pinctrl-single,register-width = <32>; 246 pinctrl-single,function-mask = <0xffffffff>; 247 }; 248 249 wkup_pmx3: pinctrl@4301c174 { 250 compatible = "ti,j7200-padconf", "pinctrl-single"; 251 /* Proxy 0 addressing */ 252 reg = <0x00 0x4301c174 0x00 0x20>; 253 #pinctrl-cells = <1>; 254 pinctrl-single,register-width = <32>; 255 pinctrl-single,function-mask = <0xffffffff>; 256 }; 257 258 mcu_ram: sram@41c00000 { 259 compatible = "mmio-sram"; 260 reg = <0x00 0x41c00000 0x00 0x100000>; 261 ranges = <0x00 0x00 0x41c00000 0x100000>; 262 #address-cells = <1>; 263 #size-cells = <1>; 264 }; 265 266 wkup_uart0: serial@42300000 { 267 compatible = "ti,j721e-uart", "ti,am654-uart"; 268 reg = <0x00 0x42300000 0x00 0x100>; 269 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 270 clock-frequency = <48000000>; 271 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; 272 clocks = <&k3_clks 287 2>; 273 clock-names = "fclk"; 274 status = "disabled"; 275 }; 276 277 mcu_uart0: serial@40a00000 { 278 compatible = "ti,j721e-uart", "ti,am654-uart"; 279 reg = <0x00 0x40a00000 0x00 0x100>; 280 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 281 clock-frequency = <96000000>; 282 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 283 clocks = <&k3_clks 149 2>; 284 clock-names = "fclk"; 285 status = "disabled"; 286 }; 287 288 wkup_gpio_intr: interrupt-controller@42200000 { 289 compatible = "ti,sci-intr"; 290 reg = <0x00 0x42200000 0x00 0x400>; 291 ti,intr-trigger-type = <1>; 292 interrupt-controller; 293 interrupt-parent = <&gic500>; 294 #interrupt-cells = <1>; 295 ti,sci = <&dmsc>; 296 ti,sci-dev-id = <137>; 297 ti,interrupt-ranges = <16 960 16>; 298 }; 299 300 wkup_gpio0: gpio@42110000 { 301 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 302 reg = <0x00 0x42110000 0x00 0x100>; 303 gpio-controller; 304 #gpio-cells = <2>; 305 interrupt-parent = <&wkup_gpio_intr>; 306 interrupts = <103>, <104>, <105>, <106>, <107>, <108>; 307 interrupt-controller; 308 #interrupt-cells = <2>; 309 ti,ngpio = <85>; 310 ti,davinci-gpio-unbanked = <0>; 311 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 312 clocks = <&k3_clks 113 0>; 313 clock-names = "gpio"; 314 status = "disabled"; 315 }; 316 317 wkup_gpio1: gpio@42100000 { 318 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 319 reg = <0x00 0x42100000 0x00 0x100>; 320 gpio-controller; 321 #gpio-cells = <2>; 322 interrupt-parent = <&wkup_gpio_intr>; 323 interrupts = <112>, <113>, <114>, <115>, <116>, <117>; 324 interrupt-controller; 325 #interrupt-cells = <2>; 326 ti,ngpio = <85>; 327 ti,davinci-gpio-unbanked = <0>; 328 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 329 clocks = <&k3_clks 114 0>; 330 clock-names = "gpio"; 331 status = "disabled"; 332 }; 333 334 mcu_navss: bus@28380000 { 335 compatible = "simple-bus"; 336 #address-cells = <2>; 337 #size-cells = <2>; 338 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 339 dma-coherent; 340 dma-ranges; 341 ti,sci-dev-id = <232>; 342 343 mcu_ringacc: ringacc@2b800000 { 344 compatible = "ti,am654-navss-ringacc"; 345 reg = <0x00 0x2b800000 0x00 0x400000>, 346 <0x00 0x2b000000 0x00 0x400000>, 347 <0x00 0x28590000 0x00 0x100>, 348 <0x00 0x2a500000 0x00 0x40000>, 349 <0x00 0x28440000 0x00 0x40000>; 350 reg-names = "rt", "fifos", "proxy_gcfg", 351 "proxy_target", "cfg"; 352 bootph-all; 353 ti,num-rings = <286>; 354 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 355 ti,sci = <&dmsc>; 356 ti,sci-dev-id = <235>; 357 msi-parent = <&main_udmass_inta>; 358 }; 359 360 mcu_udmap: dma-controller@285c0000 { 361 compatible = "ti,j721e-navss-mcu-udmap"; 362 reg = <0x00 0x285c0000 0x00 0x100>, 363 <0x00 0x2a800000 0x00 0x40000>, 364 <0x00 0x2aa00000 0x00 0x40000>, 365 <0x00 0x284a0000 0x00 0x4000>, 366 <0x00 0x284c0000 0x00 0x4000>, 367 <0x00 0x28400000 0x00 0x2000>; 368 reg-names = "gcfg", "rchanrt", "tchanrt", 369 "tchan", "rchan", "rflow"; 370 msi-parent = <&main_udmass_inta>; 371 #dma-cells = <1>; 372 bootph-all; 373 374 ti,sci = <&dmsc>; 375 ti,sci-dev-id = <236>; 376 ti,ringacc = <&mcu_ringacc>; 377 378 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 379 <0x0f>; /* TX_HCHAN */ 380 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 381 <0x0b>; /* RX_HCHAN */ 382 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 383 }; 384 }; 385 386 secure_proxy_mcu: mailbox@2a480000 { 387 compatible = "ti,am654-secure-proxy"; 388 #mbox-cells = <1>; 389 reg-names = "target_data", "rt", "scfg"; 390 reg = <0x0 0x2a480000 0x0 0x80000>, 391 <0x0 0x2a380000 0x0 0x80000>, 392 <0x0 0x2a400000 0x0 0x80000>; 393 bootph-pre-ram; 394 395 /* 396 * Marked Disabled: 397 * Node is incomplete as it is meant for bootloaders and 398 * firmware on non-MPU processors 399 */ 400 status = "disabled"; 401 }; 402 403 mcu_cpsw: ethernet@46000000 { 404 compatible = "ti,j721e-cpsw-nuss"; 405 #address-cells = <2>; 406 #size-cells = <2>; 407 reg = <0x00 0x46000000 0x00 0x200000>; 408 reg-names = "cpsw_nuss"; 409 ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>; 410 dma-coherent; 411 clocks = <&k3_clks 18 21>; 412 clock-names = "fck"; 413 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; 414 415 dmas = <&mcu_udmap 0xf000>, 416 <&mcu_udmap 0xf001>, 417 <&mcu_udmap 0xf002>, 418 <&mcu_udmap 0xf003>, 419 <&mcu_udmap 0xf004>, 420 <&mcu_udmap 0xf005>, 421 <&mcu_udmap 0xf006>, 422 <&mcu_udmap 0xf007>, 423 <&mcu_udmap 0x7000>; 424 dma-names = "tx0", "tx1", "tx2", "tx3", 425 "tx4", "tx5", "tx6", "tx7", 426 "rx"; 427 428 ethernet-ports { 429 #address-cells = <1>; 430 #size-cells = <0>; 431 432 cpsw_port1: port@1 { 433 reg = <1>; 434 ti,mac-only; 435 label = "port1"; 436 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; 437 phys = <&phy_gmii_sel 1>; 438 }; 439 }; 440 441 davinci_mdio: mdio@f00 { 442 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 443 reg = <0x00 0xf00 0x00 0x100>; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 clocks = <&k3_clks 18 21>; 447 clock-names = "fck"; 448 bus_freq = <1000000>; 449 }; 450 451 cpts@3d000 { 452 compatible = "ti,am65-cpts"; 453 reg = <0x00 0x3d000 0x00 0x400>; 454 clocks = <&k3_clks 18 2>; 455 clock-names = "cpts"; 456 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 457 interrupt-names = "cpts"; 458 ti,cpts-ext-ts-inputs = <4>; 459 ti,cpts-periodic-outputs = <2>; 460 }; 461 }; 462 463 mcu_i2c0: i2c@40b00000 { 464 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 465 reg = <0x00 0x40b00000 0x00 0x100>; 466 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 clock-names = "fck"; 470 clocks = <&k3_clks 194 1>; 471 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; 472 status = "disabled"; 473 }; 474 475 mcu_i2c1: i2c@40b10000 { 476 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 477 reg = <0x00 0x40b10000 0x00 0x100>; 478 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 clock-names = "fck"; 482 clocks = <&k3_clks 195 1>; 483 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; 484 status = "disabled"; 485 }; 486 487 wkup_i2c0: i2c@42120000 { 488 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 489 reg = <0x00 0x42120000 0x00 0x100>; 490 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 clock-names = "fck"; 494 clocks = <&k3_clks 197 1>; 495 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; 496 status = "disabled"; 497 }; 498 499 mcu_spi0: spi@40300000 { 500 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 501 reg = <0x00 0x040300000 0x00 0x400>; 502 interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; 506 clocks = <&k3_clks 274 4>; 507 status = "disabled"; 508 }; 509 510 mcu_spi1: spi@40310000 { 511 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 512 reg = <0x00 0x040310000 0x00 0x400>; 513 interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; 517 clocks = <&k3_clks 275 4>; 518 status = "disabled"; 519 }; 520 521 mcu_spi2: spi@40320000 { 522 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 523 reg = <0x00 0x040320000 0x00 0x400>; 524 interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; 525 #address-cells = <1>; 526 #size-cells = <0>; 527 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 528 clocks = <&k3_clks 276 2>; 529 status = "disabled"; 530 }; 531 532 fss: bus@47000000 { 533 compatible = "simple-bus"; 534 #address-cells = <2>; 535 #size-cells = <2>; 536 ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x100>, /* FSS Control */ 537 <0x0 0x47034000 0x0 0x47040000 0x0 0x100>, /* HBMC Control */ 538 <0x0 0x47040000 0x0 0x47040000 0x0 0x100>, /* OSPI0 Control */ 539 <0x5 0x00000000 0x5 0x00000000 0x1 0x0000000>; /* HBMC/OSPI0 Memory */ 540 541 hbmc_mux: mux-controller@47000004 { 542 compatible = "reg-mux"; 543 reg = <0x00 0x47000004 0x00 0x4>; 544 #mux-control-cells = <1>; 545 mux-reg-masks = <0x0 0x2>; /* HBMC select */ 546 bootph-all; 547 }; 548 549 hbmc: hyperbus@47034000 { 550 compatible = "ti,am654-hbmc"; 551 reg = <0x00 0x47034000 0x00 0x100>, 552 <0x05 0x00000000 0x01 0x0000000>; 553 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 554 clocks = <&k3_clks 102 0>; 555 assigned-clocks = <&k3_clks 102 5>; 556 assigned-clock-rates = <333333333>; 557 #address-cells = <2>; 558 #size-cells = <1>; 559 mux-controls = <&hbmc_mux 0>; 560 }; 561 562 ospi0: spi@47040000 { 563 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 564 reg = <0x0 0x47040000 0x0 0x100>, 565 <0x5 0x00000000 0x1 0x0000000>; 566 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; 567 cdns,fifo-depth = <256>; 568 cdns,fifo-width = <4>; 569 cdns,trigger-address = <0x0>; 570 clocks = <&k3_clks 103 0>; 571 assigned-clocks = <&k3_clks 103 0>; 572 assigned-clock-parents = <&k3_clks 103 2>; 573 assigned-clock-rates = <166666666>; 574 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 status = "disabled"; 578 }; 579 }; 580 581 tscadc0: tscadc@40200000 { 582 compatible = "ti,am3359-tscadc"; 583 reg = <0x00 0x40200000 0x00 0x1000>; 584 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 585 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 586 clocks = <&k3_clks 0 1>; 587 assigned-clocks = <&k3_clks 0 3>; 588 assigned-clock-rates = <60000000>; 589 clock-names = "fck"; 590 dmas = <&main_udmap 0x7400>, 591 <&main_udmap 0x7401>; 592 dma-names = "fifo0", "fifo1"; 593 594 adc { 595 #io-channel-cells = <1>; 596 compatible = "ti,am3359-adc"; 597 }; 598 }; 599 600 mcu_r5fss0: r5fss@41000000 { 601 compatible = "ti,j7200-r5fss"; 602 ti,cluster-mode = <1>; 603 #address-cells = <1>; 604 #size-cells = <1>; 605 ranges = <0x41000000 0x00 0x41000000 0x20000>, 606 <0x41400000 0x00 0x41400000 0x20000>; 607 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 608 609 mcu_r5fss0_core0: r5f@41000000 { 610 compatible = "ti,j7200-r5f"; 611 reg = <0x41000000 0x00010000>, 612 <0x41010000 0x00010000>; 613 reg-names = "atcm", "btcm"; 614 ti,sci = <&dmsc>; 615 ti,sci-dev-id = <250>; 616 ti,sci-proc-ids = <0x01 0xff>; 617 resets = <&k3_reset 250 1>; 618 firmware-name = "j7200-mcu-r5f0_0-fw"; 619 ti,atcm-enable = <1>; 620 ti,btcm-enable = <1>; 621 ti,loczrama = <1>; 622 }; 623 624 mcu_r5fss0_core1: r5f@41400000 { 625 compatible = "ti,j7200-r5f"; 626 reg = <0x41400000 0x00008000>, 627 <0x41410000 0x00008000>; 628 reg-names = "atcm", "btcm"; 629 ti,sci = <&dmsc>; 630 ti,sci-dev-id = <251>; 631 ti,sci-proc-ids = <0x02 0xff>; 632 resets = <&k3_reset 251 1>; 633 firmware-name = "j7200-mcu-r5f0_1-fw"; 634 ti,atcm-enable = <1>; 635 ti,btcm-enable = <1>; 636 ti,loczrama = <1>; 637 }; 638 }; 639 640 mcu_crypto: crypto@40900000 { 641 compatible = "ti,j721e-sa2ul"; 642 reg = <0x00 0x40900000 0x00 0x1200>; 643 power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>; 644 #address-cells = <2>; 645 #size-cells = <2>; 646 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; 647 dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>, 648 <&mcu_udmap 0x7503>; 649 dma-names = "tx", "rx1", "rx2"; 650 651 rng: rng@40910000 { 652 compatible = "inside-secure,safexcel-eip76"; 653 reg = <0x00 0x40910000 0x00 0x7d>; 654 interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>; 655 status = "disabled"; /* Used by OP-TEE */ 656 }; 657 }; 658 659 wkup_vtm0: temperature-sensor@42040000 { 660 compatible = "ti,j7200-vtm"; 661 reg = <0x00 0x42040000 0x00 0x350>, 662 <0x00 0x42050000 0x00 0x350>; 663 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 664 #thermal-sensor-cells = <1>; 665 bootph-pre-ram; 666 }; 667 668 mcu_esm: esm@40800000 { 669 compatible = "ti,j721e-esm"; 670 reg = <0x00 0x40800000 0x00 0x1000>; 671 ti,esm-pins = <95>; 672 bootph-pre-ram; 673 }; 674 675 mcu_mcan0: can@40528000 { 676 compatible = "bosch,m_can"; 677 reg = <0x00 0x40528000 0x00 0x200>, 678 <0x00 0x40500000 0x00 0x8000>; 679 reg-names = "m_can", "message_ram"; 680 power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>; 681 clocks = <&k3_clks 172 0>, <&k3_clks 172 2>; 682 clock-names = "hclk", "cclk"; 683 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 685 interrupt-names = "int0", "int1"; 686 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 687 status = "disabled"; 688 }; 689 690 mcu_mcan1: can@40568000 { 691 compatible = "bosch,m_can"; 692 reg = <0x00 0x40568000 0x00 0x200>, 693 <0x00 0x40540000 0x00 0x8000>; 694 reg-names = "m_can", "message_ram"; 695 power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>; 696 clocks = <&k3_clks 173 0>, <&k3_clks 173 2>; 697 clock-names = "hclk", "cclk"; 698 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 700 interrupt-names = "int0", "int1"; 701 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 702 status = "disabled"; 703 }; 704}; 705