1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J7200 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8/ { 9 serdes_refclk: serdes-refclk { 10 #clock-cells = <0>; 11 compatible = "fixed-clock"; 12 }; 13}; 14 15&cbass_main { 16 msmc_ram: sram@70000000 { 17 compatible = "mmio-sram"; 18 reg = <0x00 0x70000000 0x00 0x100000>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x00 0x00 0x70000000 0x100000>; 22 23 atf-sram@0 { 24 reg = <0x00 0x20000>; 25 }; 26 }; 27 28 scm_conf: scm-conf@100000 { 29 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 30 reg = <0x00 0x00100000 0x00 0x1c000>; 31 #address-cells = <1>; 32 #size-cells = <1>; 33 ranges = <0x00 0x00 0x00100000 0x1c000>; 34 35 serdes_ln_ctrl: mux-controller@4080 { 36 compatible = "mmio-mux"; 37 #mux-control-cells = <1>; 38 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 39 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ 40 }; 41 42 cpsw0_phy_gmii_sel: phy@4044 { 43 compatible = "ti,j7200-cpsw5g-phy-gmii-sel"; 44 ti,qsgmii-main-ports = <1>; 45 reg = <0x4044 0x10>; 46 #phy-cells = <1>; 47 }; 48 49 usb_serdes_mux: mux-controller@4000 { 50 compatible = "mmio-mux"; 51 #mux-control-cells = <1>; 52 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ 53 }; 54 }; 55 56 gic500: interrupt-controller@1800000 { 57 compatible = "arm,gic-v3"; 58 #address-cells = <2>; 59 #size-cells = <2>; 60 ranges; 61 #interrupt-cells = <3>; 62 interrupt-controller; 63 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 64 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 65 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 66 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 67 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 68 69 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 70 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 71 72 gic_its: msi-controller@1820000 { 73 compatible = "arm,gic-v3-its"; 74 reg = <0x00 0x01820000 0x00 0x10000>; 75 socionext,synquacer-pre-its = <0x1000000 0x400000>; 76 msi-controller; 77 #msi-cells = <1>; 78 }; 79 }; 80 81 main_gpio_intr: interrupt-controller@a00000 { 82 compatible = "ti,sci-intr"; 83 reg = <0x00 0x00a00000 0x00 0x800>; 84 ti,intr-trigger-type = <1>; 85 interrupt-controller; 86 interrupt-parent = <&gic500>; 87 #interrupt-cells = <1>; 88 ti,sci = <&dmsc>; 89 ti,sci-dev-id = <131>; 90 ti,interrupt-ranges = <8 392 56>; 91 }; 92 93 main_navss: bus@30000000 { 94 compatible = "simple-mfd"; 95 #address-cells = <2>; 96 #size-cells = <2>; 97 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 98 ti,sci-dev-id = <199>; 99 dma-coherent; 100 dma-ranges; 101 102 main_navss_intr: interrupt-controller@310e0000 { 103 compatible = "ti,sci-intr"; 104 reg = <0x00 0x310e0000 0x00 0x4000>; 105 ti,intr-trigger-type = <4>; 106 interrupt-controller; 107 interrupt-parent = <&gic500>; 108 #interrupt-cells = <1>; 109 ti,sci = <&dmsc>; 110 ti,sci-dev-id = <213>; 111 ti,interrupt-ranges = <0 64 64>, 112 <64 448 64>, 113 <128 672 64>; 114 }; 115 116 main_udmass_inta: msi-controller@33d00000 { 117 compatible = "ti,sci-inta"; 118 reg = <0x00 0x33d00000 0x00 0x100000>; 119 interrupt-controller; 120 #interrupt-cells = <0>; 121 interrupt-parent = <&main_navss_intr>; 122 msi-controller; 123 ti,sci = <&dmsc>; 124 ti,sci-dev-id = <209>; 125 ti,interrupt-ranges = <0 0 256>; 126 }; 127 128 secure_proxy_main: mailbox@32c00000 { 129 compatible = "ti,am654-secure-proxy"; 130 #mbox-cells = <1>; 131 reg-names = "target_data", "rt", "scfg"; 132 reg = <0x00 0x32c00000 0x00 0x100000>, 133 <0x00 0x32400000 0x00 0x100000>, 134 <0x00 0x32800000 0x00 0x100000>; 135 interrupt-names = "rx_011"; 136 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 137 }; 138 139 hwspinlock: spinlock@30e00000 { 140 compatible = "ti,am654-hwspinlock"; 141 reg = <0x00 0x30e00000 0x00 0x1000>; 142 #hwlock-cells = <1>; 143 }; 144 145 mailbox0_cluster0: mailbox@31f80000 { 146 compatible = "ti,am654-mailbox"; 147 reg = <0x00 0x31f80000 0x00 0x200>; 148 #mbox-cells = <1>; 149 ti,mbox-num-users = <4>; 150 ti,mbox-num-fifos = <16>; 151 interrupt-parent = <&main_navss_intr>; 152 status = "disabled"; 153 }; 154 155 mailbox0_cluster1: mailbox@31f81000 { 156 compatible = "ti,am654-mailbox"; 157 reg = <0x00 0x31f81000 0x00 0x200>; 158 #mbox-cells = <1>; 159 ti,mbox-num-users = <4>; 160 ti,mbox-num-fifos = <16>; 161 interrupt-parent = <&main_navss_intr>; 162 status = "disabled"; 163 }; 164 165 mailbox0_cluster2: mailbox@31f82000 { 166 compatible = "ti,am654-mailbox"; 167 reg = <0x00 0x31f82000 0x00 0x200>; 168 #mbox-cells = <1>; 169 ti,mbox-num-users = <4>; 170 ti,mbox-num-fifos = <16>; 171 interrupt-parent = <&main_navss_intr>; 172 status = "disabled"; 173 }; 174 175 mailbox0_cluster3: mailbox@31f83000 { 176 compatible = "ti,am654-mailbox"; 177 reg = <0x00 0x31f83000 0x00 0x200>; 178 #mbox-cells = <1>; 179 ti,mbox-num-users = <4>; 180 ti,mbox-num-fifos = <16>; 181 interrupt-parent = <&main_navss_intr>; 182 status = "disabled"; 183 }; 184 185 mailbox0_cluster4: mailbox@31f84000 { 186 compatible = "ti,am654-mailbox"; 187 reg = <0x00 0x31f84000 0x00 0x200>; 188 #mbox-cells = <1>; 189 ti,mbox-num-users = <4>; 190 ti,mbox-num-fifos = <16>; 191 interrupt-parent = <&main_navss_intr>; 192 status = "disabled"; 193 }; 194 195 mailbox0_cluster5: mailbox@31f85000 { 196 compatible = "ti,am654-mailbox"; 197 reg = <0x00 0x31f85000 0x00 0x200>; 198 #mbox-cells = <1>; 199 ti,mbox-num-users = <4>; 200 ti,mbox-num-fifos = <16>; 201 interrupt-parent = <&main_navss_intr>; 202 status = "disabled"; 203 }; 204 205 mailbox0_cluster6: mailbox@31f86000 { 206 compatible = "ti,am654-mailbox"; 207 reg = <0x00 0x31f86000 0x00 0x200>; 208 #mbox-cells = <1>; 209 ti,mbox-num-users = <4>; 210 ti,mbox-num-fifos = <16>; 211 interrupt-parent = <&main_navss_intr>; 212 status = "disabled"; 213 }; 214 215 mailbox0_cluster7: mailbox@31f87000 { 216 compatible = "ti,am654-mailbox"; 217 reg = <0x00 0x31f87000 0x00 0x200>; 218 #mbox-cells = <1>; 219 ti,mbox-num-users = <4>; 220 ti,mbox-num-fifos = <16>; 221 interrupt-parent = <&main_navss_intr>; 222 status = "disabled"; 223 }; 224 225 mailbox0_cluster8: mailbox@31f88000 { 226 compatible = "ti,am654-mailbox"; 227 reg = <0x00 0x31f88000 0x00 0x200>; 228 #mbox-cells = <1>; 229 ti,mbox-num-users = <4>; 230 ti,mbox-num-fifos = <16>; 231 interrupt-parent = <&main_navss_intr>; 232 status = "disabled"; 233 }; 234 235 mailbox0_cluster9: mailbox@31f89000 { 236 compatible = "ti,am654-mailbox"; 237 reg = <0x00 0x31f89000 0x00 0x200>; 238 #mbox-cells = <1>; 239 ti,mbox-num-users = <4>; 240 ti,mbox-num-fifos = <16>; 241 interrupt-parent = <&main_navss_intr>; 242 status = "disabled"; 243 }; 244 245 mailbox0_cluster10: mailbox@31f8a000 { 246 compatible = "ti,am654-mailbox"; 247 reg = <0x00 0x31f8a000 0x00 0x200>; 248 #mbox-cells = <1>; 249 ti,mbox-num-users = <4>; 250 ti,mbox-num-fifos = <16>; 251 interrupt-parent = <&main_navss_intr>; 252 status = "disabled"; 253 }; 254 255 mailbox0_cluster11: mailbox@31f8b000 { 256 compatible = "ti,am654-mailbox"; 257 reg = <0x00 0x31f8b000 0x00 0x200>; 258 #mbox-cells = <1>; 259 ti,mbox-num-users = <4>; 260 ti,mbox-num-fifos = <16>; 261 interrupt-parent = <&main_navss_intr>; 262 status = "disabled"; 263 }; 264 265 main_ringacc: ringacc@3c000000 { 266 compatible = "ti,am654-navss-ringacc"; 267 reg = <0x00 0x3c000000 0x00 0x400000>, 268 <0x00 0x38000000 0x00 0x400000>, 269 <0x00 0x31120000 0x00 0x100>, 270 <0x00 0x33000000 0x00 0x40000>, 271 <0x00 0x31080000 0x00 0x40000>; 272 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 273 ti,num-rings = <1024>; 274 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 275 ti,sci = <&dmsc>; 276 ti,sci-dev-id = <211>; 277 msi-parent = <&main_udmass_inta>; 278 }; 279 280 main_udmap: dma-controller@31150000 { 281 compatible = "ti,j721e-navss-main-udmap"; 282 reg = <0x00 0x31150000 0x00 0x100>, 283 <0x00 0x34000000 0x00 0x100000>, 284 <0x00 0x35000000 0x00 0x100000>; 285 reg-names = "gcfg", "rchanrt", "tchanrt"; 286 msi-parent = <&main_udmass_inta>; 287 #dma-cells = <1>; 288 289 ti,sci = <&dmsc>; 290 ti,sci-dev-id = <212>; 291 ti,ringacc = <&main_ringacc>; 292 293 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 294 <0x0f>, /* TX_HCHAN */ 295 <0x10>; /* TX_UHCHAN */ 296 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 297 <0x0b>, /* RX_HCHAN */ 298 <0x0c>; /* RX_UHCHAN */ 299 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 300 }; 301 302 cpts@310d0000 { 303 compatible = "ti,j721e-cpts"; 304 reg = <0x00 0x310d0000 0x00 0x400>; 305 reg-names = "cpts"; 306 clocks = <&k3_clks 201 1>; 307 clock-names = "cpts"; 308 interrupts-extended = <&main_navss_intr 391>; 309 interrupt-names = "cpts"; 310 ti,cpts-periodic-outputs = <6>; 311 ti,cpts-ext-ts-inputs = <8>; 312 }; 313 }; 314 315 cpsw0: ethernet@c000000 { 316 compatible = "ti,j7200-cpswxg-nuss"; 317 #address-cells = <2>; 318 #size-cells = <2>; 319 reg = <0x00 0xc000000 0x00 0x200000>; 320 reg-names = "cpsw_nuss"; 321 ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>; 322 clocks = <&k3_clks 19 33>; 323 clock-names = "fck"; 324 power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; 325 326 dmas = <&main_udmap 0xca00>, 327 <&main_udmap 0xca01>, 328 <&main_udmap 0xca02>, 329 <&main_udmap 0xca03>, 330 <&main_udmap 0xca04>, 331 <&main_udmap 0xca05>, 332 <&main_udmap 0xca06>, 333 <&main_udmap 0xca07>, 334 <&main_udmap 0x4a00>; 335 dma-names = "tx0", "tx1", "tx2", "tx3", 336 "tx4", "tx5", "tx6", "tx7", 337 "rx"; 338 339 status = "disabled"; 340 341 ethernet-ports { 342 #address-cells = <1>; 343 #size-cells = <0>; 344 cpsw0_port1: port@1 { 345 reg = <1>; 346 ti,mac-only; 347 label = "port1"; 348 status = "disabled"; 349 }; 350 351 cpsw0_port2: port@2 { 352 reg = <2>; 353 ti,mac-only; 354 label = "port2"; 355 status = "disabled"; 356 }; 357 358 cpsw0_port3: port@3 { 359 reg = <3>; 360 ti,mac-only; 361 label = "port3"; 362 status = "disabled"; 363 }; 364 365 cpsw0_port4: port@4 { 366 reg = <4>; 367 ti,mac-only; 368 label = "port4"; 369 status = "disabled"; 370 }; 371 }; 372 373 cpsw5g_mdio: mdio@f00 { 374 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 375 reg = <0x00 0xf00 0x00 0x100>; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 clocks = <&k3_clks 19 33>; 379 clock-names = "fck"; 380 bus_freq = <1000000>; 381 status = "disabled"; 382 }; 383 384 cpts@3d000 { 385 compatible = "ti,j721e-cpts"; 386 reg = <0x00 0x3d000 0x00 0x400>; 387 clocks = <&k3_clks 19 16>; 388 clock-names = "cpts"; 389 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 390 interrupt-names = "cpts"; 391 ti,cpts-ext-ts-inputs = <4>; 392 ti,cpts-periodic-outputs = <2>; 393 }; 394 }; 395 396 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 397 main_timerio_input: pinctrl@104200 { 398 compatible = "pinctrl-single"; 399 reg = <0x0 0x104200 0x0 0x50>; 400 #pinctrl-cells = <1>; 401 pinctrl-single,register-width = <32>; 402 pinctrl-single,function-mask = <0x000001ff>; 403 }; 404 405 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 406 main_timerio_output: pinctrl@104280 { 407 compatible = "pinctrl-single"; 408 reg = <0x0 0x104280 0x0 0x20>; 409 #pinctrl-cells = <1>; 410 pinctrl-single,register-width = <32>; 411 pinctrl-single,function-mask = <0x0000001f>; 412 }; 413 414 main_pmx0: pinctrl@11c000 { 415 compatible = "pinctrl-single"; 416 /* Proxy 0 addressing */ 417 reg = <0x00 0x11c000 0x00 0x10c>; 418 #pinctrl-cells = <1>; 419 pinctrl-single,register-width = <32>; 420 pinctrl-single,function-mask = <0xffffffff>; 421 }; 422 423 main_pmx1: pinctrl@11c11c { 424 compatible = "pinctrl-single"; 425 /* Proxy 0 addressing */ 426 reg = <0x00 0x11c11c 0x00 0xc>; 427 #pinctrl-cells = <1>; 428 pinctrl-single,register-width = <32>; 429 pinctrl-single,function-mask = <0xffffffff>; 430 }; 431 432 main_uart0: serial@2800000 { 433 compatible = "ti,j721e-uart", "ti,am654-uart"; 434 reg = <0x00 0x02800000 0x00 0x100>; 435 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 436 clock-frequency = <48000000>; 437 current-speed = <115200>; 438 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 439 clocks = <&k3_clks 146 2>; 440 clock-names = "fclk"; 441 status = "disabled"; 442 }; 443 444 main_uart1: serial@2810000 { 445 compatible = "ti,j721e-uart", "ti,am654-uart"; 446 reg = <0x00 0x02810000 0x00 0x100>; 447 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 448 clock-frequency = <48000000>; 449 current-speed = <115200>; 450 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 451 clocks = <&k3_clks 278 2>; 452 clock-names = "fclk"; 453 status = "disabled"; 454 }; 455 456 main_uart2: serial@2820000 { 457 compatible = "ti,j721e-uart", "ti,am654-uart"; 458 reg = <0x00 0x02820000 0x00 0x100>; 459 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 460 clock-frequency = <48000000>; 461 current-speed = <115200>; 462 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 463 clocks = <&k3_clks 279 2>; 464 clock-names = "fclk"; 465 status = "disabled"; 466 }; 467 468 main_uart3: serial@2830000 { 469 compatible = "ti,j721e-uart", "ti,am654-uart"; 470 reg = <0x00 0x02830000 0x00 0x100>; 471 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 472 clock-frequency = <48000000>; 473 current-speed = <115200>; 474 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 475 clocks = <&k3_clks 280 2>; 476 clock-names = "fclk"; 477 status = "disabled"; 478 }; 479 480 main_uart4: serial@2840000 { 481 compatible = "ti,j721e-uart", "ti,am654-uart"; 482 reg = <0x00 0x02840000 0x00 0x100>; 483 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 484 clock-frequency = <48000000>; 485 current-speed = <115200>; 486 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 487 clocks = <&k3_clks 281 2>; 488 clock-names = "fclk"; 489 status = "disabled"; 490 }; 491 492 main_uart5: serial@2850000 { 493 compatible = "ti,j721e-uart", "ti,am654-uart"; 494 reg = <0x00 0x02850000 0x00 0x100>; 495 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 496 clock-frequency = <48000000>; 497 current-speed = <115200>; 498 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 499 clocks = <&k3_clks 282 2>; 500 clock-names = "fclk"; 501 status = "disabled"; 502 }; 503 504 main_uart6: serial@2860000 { 505 compatible = "ti,j721e-uart", "ti,am654-uart"; 506 reg = <0x00 0x02860000 0x00 0x100>; 507 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 508 clock-frequency = <48000000>; 509 current-speed = <115200>; 510 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 511 clocks = <&k3_clks 283 2>; 512 clock-names = "fclk"; 513 status = "disabled"; 514 }; 515 516 main_uart7: serial@2870000 { 517 compatible = "ti,j721e-uart", "ti,am654-uart"; 518 reg = <0x00 0x02870000 0x00 0x100>; 519 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 520 clock-frequency = <48000000>; 521 current-speed = <115200>; 522 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 523 clocks = <&k3_clks 284 2>; 524 clock-names = "fclk"; 525 status = "disabled"; 526 }; 527 528 main_uart8: serial@2880000 { 529 compatible = "ti,j721e-uart", "ti,am654-uart"; 530 reg = <0x00 0x02880000 0x00 0x100>; 531 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 532 clock-frequency = <48000000>; 533 current-speed = <115200>; 534 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 535 clocks = <&k3_clks 285 2>; 536 clock-names = "fclk"; 537 status = "disabled"; 538 }; 539 540 main_uart9: serial@2890000 { 541 compatible = "ti,j721e-uart", "ti,am654-uart"; 542 reg = <0x00 0x02890000 0x00 0x100>; 543 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 544 clock-frequency = <48000000>; 545 current-speed = <115200>; 546 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 547 clocks = <&k3_clks 286 2>; 548 clock-names = "fclk"; 549 status = "disabled"; 550 }; 551 552 main_i2c0: i2c@2000000 { 553 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 554 reg = <0x00 0x2000000 0x00 0x100>; 555 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 clock-names = "fck"; 559 clocks = <&k3_clks 187 1>; 560 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 561 status = "disabled"; 562 }; 563 564 main_i2c1: i2c@2010000 { 565 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 566 reg = <0x00 0x2010000 0x00 0x100>; 567 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 clock-names = "fck"; 571 clocks = <&k3_clks 188 1>; 572 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 573 status = "disabled"; 574 }; 575 576 main_i2c2: i2c@2020000 { 577 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 578 reg = <0x00 0x2020000 0x00 0x100>; 579 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 580 #address-cells = <1>; 581 #size-cells = <0>; 582 clock-names = "fck"; 583 clocks = <&k3_clks 189 1>; 584 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 585 status = "disabled"; 586 }; 587 588 main_i2c3: i2c@2030000 { 589 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 590 reg = <0x00 0x2030000 0x00 0x100>; 591 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 592 #address-cells = <1>; 593 #size-cells = <0>; 594 clock-names = "fck"; 595 clocks = <&k3_clks 190 1>; 596 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 597 status = "disabled"; 598 }; 599 600 main_i2c4: i2c@2040000 { 601 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 602 reg = <0x00 0x2040000 0x00 0x100>; 603 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 604 #address-cells = <1>; 605 #size-cells = <0>; 606 clock-names = "fck"; 607 clocks = <&k3_clks 191 1>; 608 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 609 status = "disabled"; 610 }; 611 612 main_i2c5: i2c@2050000 { 613 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 614 reg = <0x00 0x2050000 0x00 0x100>; 615 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 616 #address-cells = <1>; 617 #size-cells = <0>; 618 clock-names = "fck"; 619 clocks = <&k3_clks 192 1>; 620 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 621 status = "disabled"; 622 }; 623 624 main_i2c6: i2c@2060000 { 625 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 626 reg = <0x00 0x2060000 0x00 0x100>; 627 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 628 #address-cells = <1>; 629 #size-cells = <0>; 630 clock-names = "fck"; 631 clocks = <&k3_clks 193 1>; 632 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 633 status = "disabled"; 634 }; 635 636 main_sdhci0: mmc@4f80000 { 637 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit"; 638 reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; 639 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 640 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 641 clock-names = "clk_ahb", "clk_xin"; 642 clocks = <&k3_clks 91 0>, <&k3_clks 91 3>; 643 ti,otap-del-sel-legacy = <0x0>; 644 ti,otap-del-sel-mmc-hs = <0x0>; 645 ti,otap-del-sel-ddr52 = <0x6>; 646 ti,otap-del-sel-hs200 = <0x8>; 647 ti,otap-del-sel-hs400 = <0x5>; 648 ti,itap-del-sel-legacy = <0x10>; 649 ti,itap-del-sel-mmc-hs = <0xa>; 650 ti,strobe-sel = <0x77>; 651 ti,clkbuf-sel = <0x7>; 652 ti,trm-icp = <0x8>; 653 bus-width = <8>; 654 mmc-ddr-1_8v; 655 mmc-hs200-1_8v; 656 mmc-hs400-1_8v; 657 dma-coherent; 658 status = "disabled"; 659 }; 660 661 main_sdhci1: mmc@4fb0000 { 662 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit"; 663 reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; 664 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 665 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 666 clock-names = "clk_ahb", "clk_xin"; 667 clocks = <&k3_clks 92 1>, <&k3_clks 92 2>; 668 ti,otap-del-sel-legacy = <0x0>; 669 ti,otap-del-sel-sd-hs = <0x0>; 670 ti,otap-del-sel-sdr12 = <0xf>; 671 ti,otap-del-sel-sdr25 = <0xf>; 672 ti,otap-del-sel-sdr50 = <0xc>; 673 ti,otap-del-sel-sdr104 = <0x5>; 674 ti,otap-del-sel-ddr50 = <0xc>; 675 ti,itap-del-sel-legacy = <0x0>; 676 ti,itap-del-sel-sd-hs = <0x0>; 677 ti,itap-del-sel-sdr12 = <0x0>; 678 ti,itap-del-sel-sdr25 = <0x0>; 679 ti,clkbuf-sel = <0x7>; 680 ti,trm-icp = <0x8>; 681 dma-coherent; 682 status = "disabled"; 683 }; 684 685 serdes_wiz0: wiz@5060000 { 686 compatible = "ti,j721e-wiz-10g"; 687 #address-cells = <1>; 688 #size-cells = <1>; 689 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 690 clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>; 691 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 692 num-lanes = <4>; 693 #reset-cells = <1>; 694 ranges = <0x5060000 0x0 0x5060000 0x10000>; 695 696 assigned-clocks = <&k3_clks 292 85>; 697 assigned-clock-parents = <&k3_clks 292 89>; 698 699 wiz0_pll0_refclk: pll0-refclk { 700 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 701 clock-output-names = "wiz0_pll0_refclk"; 702 #clock-cells = <0>; 703 assigned-clocks = <&wiz0_pll0_refclk>; 704 assigned-clock-parents = <&k3_clks 292 85>; 705 }; 706 707 wiz0_pll1_refclk: pll1-refclk { 708 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 709 clock-output-names = "wiz0_pll1_refclk"; 710 #clock-cells = <0>; 711 assigned-clocks = <&wiz0_pll1_refclk>; 712 assigned-clock-parents = <&k3_clks 292 85>; 713 }; 714 715 wiz0_refclk_dig: refclk-dig { 716 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 717 clock-output-names = "wiz0_refclk_dig"; 718 #clock-cells = <0>; 719 assigned-clocks = <&wiz0_refclk_dig>; 720 assigned-clock-parents = <&k3_clks 292 85>; 721 }; 722 723 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 724 clocks = <&wiz0_refclk_dig>; 725 #clock-cells = <0>; 726 }; 727 728 serdes0: serdes@5060000 { 729 compatible = "ti,j721e-serdes-10g"; 730 reg = <0x05060000 0x00010000>; 731 reg-names = "torrent_phy"; 732 resets = <&serdes_wiz0 0>; 733 reset-names = "torrent_reset"; 734 clocks = <&wiz0_pll0_refclk>; 735 clock-names = "refclk"; 736 #address-cells = <1>; 737 #size-cells = <0>; 738 }; 739 }; 740 741 pcie1_rc: pcie@2910000 { 742 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; 743 reg = <0x00 0x02910000 0x00 0x1000>, 744 <0x00 0x02917000 0x00 0x400>, 745 <0x00 0x0d800000 0x00 0x00800000>, 746 <0x00 0x18000000 0x00 0x00001000>; 747 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 748 interrupt-names = "link_state"; 749 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 750 device_type = "pci"; 751 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 752 max-link-speed = <3>; 753 num-lanes = <4>; 754 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 755 clocks = <&k3_clks 240 6>; 756 clock-names = "fck"; 757 #address-cells = <3>; 758 #size-cells = <2>; 759 bus-range = <0x0 0xff>; 760 cdns,no-bar-match-nbits = <64>; 761 vendor-id = <0x104c>; 762 device-id = <0xb00f>; 763 msi-map = <0x0 &gic_its 0x0 0x10000>; 764 dma-coherent; 765 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, 766 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; 767 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 768 }; 769 770 pcie1_ep: pcie-ep@2910000 { 771 compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; 772 reg = <0x00 0x02910000 0x00 0x1000>, 773 <0x00 0x02917000 0x00 0x400>, 774 <0x00 0x0d800000 0x00 0x00800000>, 775 <0x00 0x18000000 0x00 0x08000000>; 776 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 777 interrupt-names = "link_state"; 778 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 779 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 780 max-link-speed = <3>; 781 num-lanes = <4>; 782 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 783 clocks = <&k3_clks 240 6>; 784 clock-names = "fck"; 785 max-functions = /bits/ 8 <6>; 786 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 787 dma-coherent; 788 }; 789 790 usbss0: cdns-usb@4104000 { 791 compatible = "ti,j721e-usb"; 792 reg = <0x00 0x4104000 0x00 0x100>; 793 dma-coherent; 794 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 795 clocks = <&k3_clks 288 12>, <&k3_clks 288 3>; 796 clock-names = "ref", "lpm"; 797 assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */ 798 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */ 799 #address-cells = <2>; 800 #size-cells = <2>; 801 ranges; 802 803 usb0: usb@6000000 { 804 compatible = "cdns,usb3"; 805 reg = <0x00 0x6000000 0x00 0x10000>, 806 <0x00 0x6010000 0x00 0x10000>, 807 <0x00 0x6020000 0x00 0x10000>; 808 reg-names = "otg", "xhci", "dev"; 809 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 810 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 811 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 812 interrupt-names = "host", 813 "peripheral", 814 "otg"; 815 maximum-speed = "super-speed"; 816 dr_mode = "otg"; 817 cdns,phyrst-a-enable; 818 }; 819 }; 820 821 main_gpio0: gpio@600000 { 822 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 823 reg = <0x00 0x00600000 0x00 0x100>; 824 gpio-controller; 825 #gpio-cells = <2>; 826 interrupt-parent = <&main_gpio_intr>; 827 interrupts = <145>, <146>, <147>, <148>, 828 <149>; 829 interrupt-controller; 830 #interrupt-cells = <2>; 831 ti,ngpio = <69>; 832 ti,davinci-gpio-unbanked = <0>; 833 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 834 clocks = <&k3_clks 105 0>; 835 clock-names = "gpio"; 836 status = "disabled"; 837 }; 838 839 main_gpio2: gpio@610000 { 840 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 841 reg = <0x00 0x00610000 0x00 0x100>; 842 gpio-controller; 843 #gpio-cells = <2>; 844 interrupt-parent = <&main_gpio_intr>; 845 interrupts = <154>, <155>, <156>, <157>, 846 <158>; 847 interrupt-controller; 848 #interrupt-cells = <2>; 849 ti,ngpio = <69>; 850 ti,davinci-gpio-unbanked = <0>; 851 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 852 clocks = <&k3_clks 107 0>; 853 clock-names = "gpio"; 854 status = "disabled"; 855 }; 856 857 main_gpio4: gpio@620000 { 858 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 859 reg = <0x00 0x00620000 0x00 0x100>; 860 gpio-controller; 861 #gpio-cells = <2>; 862 interrupt-parent = <&main_gpio_intr>; 863 interrupts = <163>, <164>, <165>, <166>, 864 <167>; 865 interrupt-controller; 866 #interrupt-cells = <2>; 867 ti,ngpio = <69>; 868 ti,davinci-gpio-unbanked = <0>; 869 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 870 clocks = <&k3_clks 109 0>; 871 clock-names = "gpio"; 872 status = "disabled"; 873 }; 874 875 main_gpio6: gpio@630000 { 876 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 877 reg = <0x00 0x00630000 0x00 0x100>; 878 gpio-controller; 879 #gpio-cells = <2>; 880 interrupt-parent = <&main_gpio_intr>; 881 interrupts = <172>, <173>, <174>, <175>, 882 <176>; 883 interrupt-controller; 884 #interrupt-cells = <2>; 885 ti,ngpio = <69>; 886 ti,davinci-gpio-unbanked = <0>; 887 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 888 clocks = <&k3_clks 111 0>; 889 clock-names = "gpio"; 890 status = "disabled"; 891 }; 892 893 main_spi0: spi@2100000 { 894 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 895 reg = <0x00 0x02100000 0x00 0x400>; 896 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 897 #address-cells = <1>; 898 #size-cells = <0>; 899 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; 900 clocks = <&k3_clks 266 1>; 901 status = "disabled"; 902 }; 903 904 main_spi1: spi@2110000 { 905 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 906 reg = <0x00 0x02110000 0x00 0x400>; 907 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 908 #address-cells = <1>; 909 #size-cells = <0>; 910 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; 911 clocks = <&k3_clks 267 1>; 912 status = "disabled"; 913 }; 914 915 main_spi2: spi@2120000 { 916 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 917 reg = <0x00 0x02120000 0x00 0x400>; 918 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 919 #address-cells = <1>; 920 #size-cells = <0>; 921 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; 922 clocks = <&k3_clks 268 1>; 923 status = "disabled"; 924 }; 925 926 main_spi3: spi@2130000 { 927 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 928 reg = <0x00 0x02130000 0x00 0x400>; 929 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 930 #address-cells = <1>; 931 #size-cells = <0>; 932 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; 933 clocks = <&k3_clks 269 1>; 934 status = "disabled"; 935 }; 936 937 main_spi4: spi@2140000 { 938 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 939 reg = <0x00 0x02140000 0x00 0x400>; 940 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 941 #address-cells = <1>; 942 #size-cells = <0>; 943 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; 944 clocks = <&k3_clks 270 1>; 945 status = "disabled"; 946 }; 947 948 main_spi5: spi@2150000 { 949 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 950 reg = <0x00 0x02150000 0x00 0x400>; 951 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 952 #address-cells = <1>; 953 #size-cells = <0>; 954 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; 955 clocks = <&k3_clks 271 1>; 956 status = "disabled"; 957 }; 958 959 main_spi6: spi@2160000 { 960 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 961 reg = <0x00 0x02160000 0x00 0x400>; 962 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 963 #address-cells = <1>; 964 #size-cells = <0>; 965 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; 966 clocks = <&k3_clks 272 1>; 967 status = "disabled"; 968 }; 969 970 main_spi7: spi@2170000 { 971 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 972 reg = <0x00 0x02170000 0x00 0x400>; 973 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 974 #address-cells = <1>; 975 #size-cells = <0>; 976 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; 977 clocks = <&k3_clks 273 1>; 978 status = "disabled"; 979 }; 980 981 watchdog0: watchdog@2200000 { 982 compatible = "ti,j7-rti-wdt"; 983 reg = <0x0 0x2200000 0x0 0x100>; 984 clocks = <&k3_clks 252 1>; 985 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 986 assigned-clocks = <&k3_clks 252 1>; 987 assigned-clock-parents = <&k3_clks 252 5>; 988 }; 989 990 watchdog1: watchdog@2210000 { 991 compatible = "ti,j7-rti-wdt"; 992 reg = <0x0 0x2210000 0x0 0x100>; 993 clocks = <&k3_clks 253 1>; 994 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 995 assigned-clocks = <&k3_clks 253 1>; 996 assigned-clock-parents = <&k3_clks 253 5>; 997 }; 998 999 main_timer0: timer@2400000 { 1000 compatible = "ti,am654-timer"; 1001 reg = <0x00 0x2400000 0x00 0x400>; 1002 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 1003 clocks = <&k3_clks 49 1>; 1004 clock-names = "fck"; 1005 assigned-clocks = <&k3_clks 49 1>; 1006 assigned-clock-parents = <&k3_clks 49 2>; 1007 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; 1008 ti,timer-pwm; 1009 }; 1010 1011 main_timer1: timer@2410000 { 1012 compatible = "ti,am654-timer"; 1013 reg = <0x00 0x2410000 0x00 0x400>; 1014 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1015 clocks = <&k3_clks 50 1>; 1016 clock-names = "fck"; 1017 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>; 1018 assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 313 1>; 1019 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; 1020 ti,timer-pwm; 1021 }; 1022 1023 main_timer2: timer@2420000 { 1024 compatible = "ti,am654-timer"; 1025 reg = <0x00 0x2420000 0x00 0x400>; 1026 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1027 clocks = <&k3_clks 51 1>; 1028 clock-names = "fck"; 1029 assigned-clocks = <&k3_clks 51 1>; 1030 assigned-clock-parents = <&k3_clks 51 2>; 1031 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; 1032 ti,timer-pwm; 1033 }; 1034 1035 main_timer3: timer@2430000 { 1036 compatible = "ti,am654-timer"; 1037 reg = <0x00 0x2430000 0x00 0x400>; 1038 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 1039 clocks = <&k3_clks 52 1>; 1040 clock-names = "fck"; 1041 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>; 1042 assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 314 1>; 1043 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 1044 ti,timer-pwm; 1045 }; 1046 1047 main_timer4: timer@2440000 { 1048 compatible = "ti,am654-timer"; 1049 reg = <0x00 0x2440000 0x00 0x400>; 1050 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 1051 clocks = <&k3_clks 53 1>; 1052 clock-names = "fck"; 1053 assigned-clocks = <&k3_clks 53 1>; 1054 assigned-clock-parents = <&k3_clks 53 2>; 1055 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 1056 ti,timer-pwm; 1057 }; 1058 1059 main_timer5: timer@2450000 { 1060 compatible = "ti,am654-timer"; 1061 reg = <0x00 0x2450000 0x00 0x400>; 1062 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 1063 clocks = <&k3_clks 54 1>; 1064 clock-names = "fck"; 1065 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>; 1066 assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 315 1>; 1067 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; 1068 ti,timer-pwm; 1069 }; 1070 1071 main_timer6: timer@2460000 { 1072 compatible = "ti,am654-timer"; 1073 reg = <0x00 0x2460000 0x00 0x400>; 1074 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 1075 clocks = <&k3_clks 55 1>; 1076 clock-names = "fck"; 1077 assigned-clocks = <&k3_clks 55 1>; 1078 assigned-clock-parents = <&k3_clks 55 2>; 1079 power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>; 1080 ti,timer-pwm; 1081 }; 1082 1083 main_timer7: timer@2470000 { 1084 compatible = "ti,am654-timer"; 1085 reg = <0x00 0x2470000 0x00 0x400>; 1086 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 1087 clocks = <&k3_clks 57 1>; 1088 clock-names = "fck"; 1089 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>; 1090 assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 316 1>; 1091 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 1092 ti,timer-pwm; 1093 }; 1094 1095 main_timer8: timer@2480000 { 1096 compatible = "ti,am654-timer"; 1097 reg = <0x00 0x2480000 0x00 0x400>; 1098 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 1099 clocks = <&k3_clks 58 1>; 1100 clock-names = "fck"; 1101 assigned-clocks = <&k3_clks 58 1>; 1102 assigned-clock-parents = <&k3_clks 58 2>; 1103 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 1104 ti,timer-pwm; 1105 }; 1106 1107 main_timer9: timer@2490000 { 1108 compatible = "ti,am654-timer"; 1109 reg = <0x00 0x2490000 0x00 0x400>; 1110 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 1111 clocks = <&k3_clks 59 1>; 1112 clock-names = "fck"; 1113 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>; 1114 assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 317 1>; 1115 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; 1116 ti,timer-pwm; 1117 }; 1118 1119 main_timer10: timer@24a0000 { 1120 compatible = "ti,am654-timer"; 1121 reg = <0x00 0x24a0000 0x00 0x400>; 1122 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 1123 clocks = <&k3_clks 60 1>; 1124 clock-names = "fck"; 1125 assigned-clocks = <&k3_clks 60 1>; 1126 assigned-clock-parents = <&k3_clks 60 2>; 1127 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; 1128 ti,timer-pwm; 1129 }; 1130 1131 main_timer11: timer@24b0000 { 1132 compatible = "ti,am654-timer"; 1133 reg = <0x00 0x24b0000 0x00 0x400>; 1134 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 1135 clocks = <&k3_clks 62 1>; 1136 clock-names = "fck"; 1137 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>; 1138 assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 318 1>; 1139 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 1140 ti,timer-pwm; 1141 }; 1142 1143 main_timer12: timer@24c0000 { 1144 compatible = "ti,am654-timer"; 1145 reg = <0x00 0x24c0000 0x00 0x400>; 1146 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 1147 clocks = <&k3_clks 63 1>; 1148 clock-names = "fck"; 1149 assigned-clocks = <&k3_clks 63 1>; 1150 assigned-clock-parents = <&k3_clks 63 2>; 1151 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 1152 ti,timer-pwm; 1153 }; 1154 1155 main_timer13: timer@24d0000 { 1156 compatible = "ti,am654-timer"; 1157 reg = <0x00 0x24d0000 0x00 0x400>; 1158 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 1159 clocks = <&k3_clks 64 1>; 1160 clock-names = "fck"; 1161 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>; 1162 assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 319 1>; 1163 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 1164 ti,timer-pwm; 1165 }; 1166 1167 main_timer14: timer@24e0000 { 1168 compatible = "ti,am654-timer"; 1169 reg = <0x00 0x24e0000 0x00 0x400>; 1170 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1171 clocks = <&k3_clks 65 1>; 1172 clock-names = "fck"; 1173 assigned-clocks = <&k3_clks 65 1>; 1174 assigned-clock-parents = <&k3_clks 65 2>; 1175 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; 1176 ti,timer-pwm; 1177 }; 1178 1179 main_timer15: timer@24f0000 { 1180 compatible = "ti,am654-timer"; 1181 reg = <0x00 0x24f0000 0x00 0x400>; 1182 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1183 clocks = <&k3_clks 66 1>; 1184 clock-names = "fck"; 1185 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>; 1186 assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 320 1>; 1187 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; 1188 ti,timer-pwm; 1189 }; 1190 1191 main_timer16: timer@2500000 { 1192 compatible = "ti,am654-timer"; 1193 reg = <0x00 0x2500000 0x00 0x400>; 1194 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1195 clocks = <&k3_clks 67 1>; 1196 clock-names = "fck"; 1197 assigned-clocks = <&k3_clks 67 1>; 1198 assigned-clock-parents = <&k3_clks 67 2>; 1199 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 1200 ti,timer-pwm; 1201 }; 1202 1203 main_timer17: timer@2510000 { 1204 compatible = "ti,am654-timer"; 1205 reg = <0x00 0x2510000 0x00 0x400>; 1206 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1207 clocks = <&k3_clks 68 1>; 1208 clock-names = "fck"; 1209 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>; 1210 assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 321 1>; 1211 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; 1212 ti,timer-pwm; 1213 }; 1214 1215 main_timer18: timer@2520000 { 1216 compatible = "ti,am654-timer"; 1217 reg = <0x00 0x2520000 0x00 0x400>; 1218 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1219 clocks = <&k3_clks 69 1>; 1220 clock-names = "fck"; 1221 assigned-clocks = <&k3_clks 69 1>; 1222 assigned-clock-parents = <&k3_clks 69 2>; 1223 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; 1224 ti,timer-pwm; 1225 }; 1226 1227 main_timer19: timer@2530000 { 1228 compatible = "ti,am654-timer"; 1229 reg = <0x00 0x2530000 0x00 0x400>; 1230 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1231 clocks = <&k3_clks 70 1>; 1232 clock-names = "fck"; 1233 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>; 1234 assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 322 1>; 1235 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; 1236 ti,timer-pwm; 1237 }; 1238 1239 main_r5fss0: r5fss@5c00000 { 1240 compatible = "ti,j7200-r5fss"; 1241 ti,cluster-mode = <1>; 1242 #address-cells = <1>; 1243 #size-cells = <1>; 1244 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 1245 <0x5d00000 0x00 0x5d00000 0x20000>; 1246 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; 1247 1248 main_r5fss0_core0: r5f@5c00000 { 1249 compatible = "ti,j7200-r5f"; 1250 reg = <0x5c00000 0x00010000>, 1251 <0x5c10000 0x00010000>; 1252 reg-names = "atcm", "btcm"; 1253 ti,sci = <&dmsc>; 1254 ti,sci-dev-id = <245>; 1255 ti,sci-proc-ids = <0x06 0xff>; 1256 resets = <&k3_reset 245 1>; 1257 firmware-name = "j7200-main-r5f0_0-fw"; 1258 ti,atcm-enable = <1>; 1259 ti,btcm-enable = <1>; 1260 ti,loczrama = <1>; 1261 }; 1262 1263 main_r5fss0_core1: r5f@5d00000 { 1264 compatible = "ti,j7200-r5f"; 1265 reg = <0x5d00000 0x00008000>, 1266 <0x5d10000 0x00008000>; 1267 reg-names = "atcm", "btcm"; 1268 ti,sci = <&dmsc>; 1269 ti,sci-dev-id = <246>; 1270 ti,sci-proc-ids = <0x07 0xff>; 1271 resets = <&k3_reset 246 1>; 1272 firmware-name = "j7200-main-r5f0_1-fw"; 1273 ti,atcm-enable = <1>; 1274 ti,btcm-enable = <1>; 1275 ti,loczrama = <1>; 1276 }; 1277 }; 1278 1279 main_esm: esm@700000 { 1280 compatible = "ti,j721e-esm"; 1281 reg = <0x0 0x700000 0x0 0x1000>; 1282 ti,esm-pins = <656>, <657>; 1283 }; 1284}; 1285