1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J7200 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8/ { 9 serdes_refclk: serdes-refclk { 10 #clock-cells = <0>; 11 compatible = "fixed-clock"; 12 }; 13}; 14 15&cbass_main { 16 msmc_ram: sram@70000000 { 17 compatible = "mmio-sram"; 18 reg = <0x00 0x70000000 0x00 0x100000>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x00 0x00 0x70000000 0x100000>; 22 23 atf-sram@0 { 24 reg = <0x00 0x20000>; 25 }; 26 }; 27 28 scm_conf: scm-conf@100000 { 29 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 30 reg = <0x00 0x00100000 0x00 0x1c000>; 31 #address-cells = <1>; 32 #size-cells = <1>; 33 ranges = <0x00 0x00 0x00100000 0x1c000>; 34 35 serdes_ln_ctrl: mux-controller@4080 { 36 compatible = "reg-mux"; 37 reg = <0x4080 0x20>; 38 #mux-control-cells = <1>; 39 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ 40 <0x8 0x3>, <0xc 0x3>; /* SERDES0 lane2/3 select */ 41 }; 42 43 cpsw0_phy_gmii_sel: phy@4044 { 44 compatible = "ti,j7200-cpsw5g-phy-gmii-sel"; 45 ti,qsgmii-main-ports = <1>; 46 reg = <0x4044 0x10>; 47 #phy-cells = <1>; 48 }; 49 50 usb_serdes_mux: mux-controller@4000 { 51 compatible = "reg-mux"; 52 reg = <0x4000 0x4>; 53 #mux-control-cells = <1>; 54 mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ 55 }; 56 }; 57 58 gic500: interrupt-controller@1800000 { 59 compatible = "arm,gic-v3"; 60 #address-cells = <2>; 61 #size-cells = <2>; 62 ranges; 63 #interrupt-cells = <3>; 64 interrupt-controller; 65 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 66 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 67 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 68 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 69 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 70 71 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 72 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 73 74 gic_its: msi-controller@1820000 { 75 compatible = "arm,gic-v3-its"; 76 reg = <0x00 0x01820000 0x00 0x10000>; 77 socionext,synquacer-pre-its = <0x1000000 0x400000>; 78 msi-controller; 79 #msi-cells = <1>; 80 }; 81 }; 82 83 main_gpio_intr: interrupt-controller@a00000 { 84 compatible = "ti,sci-intr"; 85 reg = <0x00 0x00a00000 0x00 0x800>; 86 ti,intr-trigger-type = <1>; 87 interrupt-controller; 88 interrupt-parent = <&gic500>; 89 #interrupt-cells = <1>; 90 ti,sci = <&dmsc>; 91 ti,sci-dev-id = <131>; 92 ti,interrupt-ranges = <8 392 56>; 93 }; 94 95 main_navss: bus@30000000 { 96 compatible = "simple-bus"; 97 #address-cells = <2>; 98 #size-cells = <2>; 99 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 100 ti,sci-dev-id = <199>; 101 dma-coherent; 102 dma-ranges; 103 104 main_navss_intr: interrupt-controller@310e0000 { 105 compatible = "ti,sci-intr"; 106 reg = <0x00 0x310e0000 0x00 0x4000>; 107 ti,intr-trigger-type = <4>; 108 interrupt-controller; 109 interrupt-parent = <&gic500>; 110 #interrupt-cells = <1>; 111 ti,sci = <&dmsc>; 112 ti,sci-dev-id = <213>; 113 ti,interrupt-ranges = <0 64 64>, 114 <64 448 64>, 115 <128 672 64>; 116 }; 117 118 main_udmass_inta: msi-controller@33d00000 { 119 compatible = "ti,sci-inta"; 120 reg = <0x00 0x33d00000 0x00 0x100000>; 121 interrupt-controller; 122 #interrupt-cells = <0>; 123 interrupt-parent = <&main_navss_intr>; 124 msi-controller; 125 ti,sci = <&dmsc>; 126 ti,sci-dev-id = <209>; 127 ti,interrupt-ranges = <0 0 256>; 128 }; 129 130 secure_proxy_main: mailbox@32c00000 { 131 compatible = "ti,am654-secure-proxy"; 132 #mbox-cells = <1>; 133 reg-names = "target_data", "rt", "scfg"; 134 reg = <0x00 0x32c00000 0x00 0x100000>, 135 <0x00 0x32400000 0x00 0x100000>, 136 <0x00 0x32800000 0x00 0x100000>; 137 interrupt-names = "rx_011"; 138 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 139 bootph-all; 140 }; 141 142 hwspinlock: spinlock@30e00000 { 143 compatible = "ti,am654-hwspinlock"; 144 reg = <0x00 0x30e00000 0x00 0x1000>; 145 #hwlock-cells = <1>; 146 }; 147 148 mailbox0_cluster0: mailbox@31f80000 { 149 compatible = "ti,am654-mailbox"; 150 reg = <0x00 0x31f80000 0x00 0x200>; 151 #mbox-cells = <1>; 152 ti,mbox-num-users = <4>; 153 ti,mbox-num-fifos = <16>; 154 interrupt-parent = <&main_navss_intr>; 155 status = "disabled"; 156 }; 157 158 mailbox0_cluster1: mailbox@31f81000 { 159 compatible = "ti,am654-mailbox"; 160 reg = <0x00 0x31f81000 0x00 0x200>; 161 #mbox-cells = <1>; 162 ti,mbox-num-users = <4>; 163 ti,mbox-num-fifos = <16>; 164 interrupt-parent = <&main_navss_intr>; 165 status = "disabled"; 166 }; 167 168 mailbox0_cluster2: mailbox@31f82000 { 169 compatible = "ti,am654-mailbox"; 170 reg = <0x00 0x31f82000 0x00 0x200>; 171 #mbox-cells = <1>; 172 ti,mbox-num-users = <4>; 173 ti,mbox-num-fifos = <16>; 174 interrupt-parent = <&main_navss_intr>; 175 status = "disabled"; 176 }; 177 178 mailbox0_cluster3: mailbox@31f83000 { 179 compatible = "ti,am654-mailbox"; 180 reg = <0x00 0x31f83000 0x00 0x200>; 181 #mbox-cells = <1>; 182 ti,mbox-num-users = <4>; 183 ti,mbox-num-fifos = <16>; 184 interrupt-parent = <&main_navss_intr>; 185 status = "disabled"; 186 }; 187 188 mailbox0_cluster4: mailbox@31f84000 { 189 compatible = "ti,am654-mailbox"; 190 reg = <0x00 0x31f84000 0x00 0x200>; 191 #mbox-cells = <1>; 192 ti,mbox-num-users = <4>; 193 ti,mbox-num-fifos = <16>; 194 interrupt-parent = <&main_navss_intr>; 195 status = "disabled"; 196 }; 197 198 mailbox0_cluster5: mailbox@31f85000 { 199 compatible = "ti,am654-mailbox"; 200 reg = <0x00 0x31f85000 0x00 0x200>; 201 #mbox-cells = <1>; 202 ti,mbox-num-users = <4>; 203 ti,mbox-num-fifos = <16>; 204 interrupt-parent = <&main_navss_intr>; 205 status = "disabled"; 206 }; 207 208 mailbox0_cluster6: mailbox@31f86000 { 209 compatible = "ti,am654-mailbox"; 210 reg = <0x00 0x31f86000 0x00 0x200>; 211 #mbox-cells = <1>; 212 ti,mbox-num-users = <4>; 213 ti,mbox-num-fifos = <16>; 214 interrupt-parent = <&main_navss_intr>; 215 status = "disabled"; 216 }; 217 218 mailbox0_cluster7: mailbox@31f87000 { 219 compatible = "ti,am654-mailbox"; 220 reg = <0x00 0x31f87000 0x00 0x200>; 221 #mbox-cells = <1>; 222 ti,mbox-num-users = <4>; 223 ti,mbox-num-fifos = <16>; 224 interrupt-parent = <&main_navss_intr>; 225 status = "disabled"; 226 }; 227 228 mailbox0_cluster8: mailbox@31f88000 { 229 compatible = "ti,am654-mailbox"; 230 reg = <0x00 0x31f88000 0x00 0x200>; 231 #mbox-cells = <1>; 232 ti,mbox-num-users = <4>; 233 ti,mbox-num-fifos = <16>; 234 interrupt-parent = <&main_navss_intr>; 235 status = "disabled"; 236 }; 237 238 mailbox0_cluster9: mailbox@31f89000 { 239 compatible = "ti,am654-mailbox"; 240 reg = <0x00 0x31f89000 0x00 0x200>; 241 #mbox-cells = <1>; 242 ti,mbox-num-users = <4>; 243 ti,mbox-num-fifos = <16>; 244 interrupt-parent = <&main_navss_intr>; 245 status = "disabled"; 246 }; 247 248 mailbox0_cluster10: mailbox@31f8a000 { 249 compatible = "ti,am654-mailbox"; 250 reg = <0x00 0x31f8a000 0x00 0x200>; 251 #mbox-cells = <1>; 252 ti,mbox-num-users = <4>; 253 ti,mbox-num-fifos = <16>; 254 interrupt-parent = <&main_navss_intr>; 255 status = "disabled"; 256 }; 257 258 mailbox0_cluster11: mailbox@31f8b000 { 259 compatible = "ti,am654-mailbox"; 260 reg = <0x00 0x31f8b000 0x00 0x200>; 261 #mbox-cells = <1>; 262 ti,mbox-num-users = <4>; 263 ti,mbox-num-fifos = <16>; 264 interrupt-parent = <&main_navss_intr>; 265 status = "disabled"; 266 }; 267 268 main_ringacc: ringacc@3c000000 { 269 compatible = "ti,am654-navss-ringacc"; 270 reg = <0x00 0x3c000000 0x00 0x400000>, 271 <0x00 0x38000000 0x00 0x400000>, 272 <0x00 0x31120000 0x00 0x100>, 273 <0x00 0x33000000 0x00 0x40000>, 274 <0x00 0x31080000 0x00 0x40000>; 275 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 276 ti,num-rings = <1024>; 277 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 278 ti,sci = <&dmsc>; 279 ti,sci-dev-id = <211>; 280 msi-parent = <&main_udmass_inta>; 281 }; 282 283 main_udmap: dma-controller@31150000 { 284 compatible = "ti,j721e-navss-main-udmap"; 285 reg = <0x00 0x31150000 0x00 0x100>, 286 <0x00 0x34000000 0x00 0x100000>, 287 <0x00 0x35000000 0x00 0x100000>, 288 <0x00 0x30b00000 0x00 0x4000>, 289 <0x00 0x30c00000 0x00 0x4000>, 290 <0x00 0x30d00000 0x00 0x4000>; 291 reg-names = "gcfg", "rchanrt", "tchanrt", 292 "tchan", "rchan", "rflow"; 293 msi-parent = <&main_udmass_inta>; 294 #dma-cells = <1>; 295 296 ti,sci = <&dmsc>; 297 ti,sci-dev-id = <212>; 298 ti,ringacc = <&main_ringacc>; 299 300 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 301 <0x0f>, /* TX_HCHAN */ 302 <0x10>; /* TX_UHCHAN */ 303 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 304 <0x0b>, /* RX_HCHAN */ 305 <0x0c>; /* RX_UHCHAN */ 306 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 307 }; 308 309 cpts@310d0000 { 310 compatible = "ti,j721e-cpts"; 311 reg = <0x00 0x310d0000 0x00 0x400>; 312 reg-names = "cpts"; 313 clocks = <&k3_clks 201 1>; 314 clock-names = "cpts"; 315 interrupts-extended = <&main_navss_intr 391>; 316 interrupt-names = "cpts"; 317 ti,cpts-periodic-outputs = <6>; 318 ti,cpts-ext-ts-inputs = <8>; 319 }; 320 }; 321 322 cpsw0: ethernet@c000000 { 323 compatible = "ti,j7200-cpswxg-nuss"; 324 #address-cells = <2>; 325 #size-cells = <2>; 326 reg = <0x00 0xc000000 0x00 0x200000>; 327 reg-names = "cpsw_nuss"; 328 ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>; 329 clocks = <&k3_clks 19 33>; 330 clock-names = "fck"; 331 power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; 332 333 dmas = <&main_udmap 0xca00>, 334 <&main_udmap 0xca01>, 335 <&main_udmap 0xca02>, 336 <&main_udmap 0xca03>, 337 <&main_udmap 0xca04>, 338 <&main_udmap 0xca05>, 339 <&main_udmap 0xca06>, 340 <&main_udmap 0xca07>, 341 <&main_udmap 0x4a00>; 342 dma-names = "tx0", "tx1", "tx2", "tx3", 343 "tx4", "tx5", "tx6", "tx7", 344 "rx"; 345 346 status = "disabled"; 347 348 ethernet-ports { 349 #address-cells = <1>; 350 #size-cells = <0>; 351 cpsw0_port1: port@1 { 352 reg = <1>; 353 ti,mac-only; 354 label = "port1"; 355 status = "disabled"; 356 }; 357 358 cpsw0_port2: port@2 { 359 reg = <2>; 360 ti,mac-only; 361 label = "port2"; 362 status = "disabled"; 363 }; 364 365 cpsw0_port3: port@3 { 366 reg = <3>; 367 ti,mac-only; 368 label = "port3"; 369 status = "disabled"; 370 }; 371 372 cpsw0_port4: port@4 { 373 reg = <4>; 374 ti,mac-only; 375 label = "port4"; 376 status = "disabled"; 377 }; 378 }; 379 380 cpsw5g_mdio: mdio@f00 { 381 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 382 reg = <0x00 0xf00 0x00 0x100>; 383 #address-cells = <1>; 384 #size-cells = <0>; 385 clocks = <&k3_clks 19 33>; 386 clock-names = "fck"; 387 bus_freq = <1000000>; 388 status = "disabled"; 389 }; 390 391 cpts@3d000 { 392 compatible = "ti,j721e-cpts"; 393 reg = <0x00 0x3d000 0x00 0x400>; 394 clocks = <&k3_clks 19 16>; 395 clock-names = "cpts"; 396 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 397 interrupt-names = "cpts"; 398 ti,cpts-ext-ts-inputs = <4>; 399 ti,cpts-periodic-outputs = <2>; 400 }; 401 }; 402 403 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 404 main_timerio_input: pinctrl@104200 { 405 compatible = "ti,j7200-padconf", "pinctrl-single"; 406 reg = <0x0 0x104200 0x0 0x50>; 407 #pinctrl-cells = <1>; 408 pinctrl-single,register-width = <32>; 409 pinctrl-single,function-mask = <0x000001ff>; 410 }; 411 412 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 413 main_timerio_output: pinctrl@104280 { 414 compatible = "ti,j7200-padconf", "pinctrl-single"; 415 reg = <0x0 0x104280 0x0 0x20>; 416 #pinctrl-cells = <1>; 417 pinctrl-single,register-width = <32>; 418 pinctrl-single,function-mask = <0x0000001f>; 419 }; 420 421 main_pmx0: pinctrl@11c000 { 422 compatible = "ti,j7200-padconf", "pinctrl-single"; 423 /* Proxy 0 addressing */ 424 reg = <0x00 0x11c000 0x00 0x10c>; 425 #pinctrl-cells = <1>; 426 pinctrl-single,register-width = <32>; 427 pinctrl-single,function-mask = <0xffffffff>; 428 }; 429 430 main_pmx1: pinctrl@11c110 { 431 compatible = "ti,j7200-padconf", "pinctrl-single"; 432 /* Proxy 0 addressing */ 433 reg = <0x00 0x11c110 0x00 0x004>; 434 #pinctrl-cells = <1>; 435 pinctrl-single,register-width = <32>; 436 pinctrl-single,function-mask = <0xffffffff>; 437 }; 438 439 main_pmx2: pinctrl@11c11c { 440 compatible = "ti,j7200-padconf", "pinctrl-single"; 441 /* Proxy 0 addressing */ 442 reg = <0x00 0x11c11c 0x00 0x00c>; 443 #pinctrl-cells = <1>; 444 pinctrl-single,register-width = <32>; 445 pinctrl-single,function-mask = <0xffffffff>; 446 }; 447 448 main_pmx3: pinctrl@11c164 { 449 compatible = "ti,j7200-padconf", "pinctrl-single"; 450 /* Proxy 0 addressing */ 451 reg = <0x00 0x11c164 0x00 0x008>; 452 #pinctrl-cells = <1>; 453 pinctrl-single,register-width = <32>; 454 pinctrl-single,function-mask = <0xffffffff>; 455 }; 456 457 main_uart0: serial@2800000 { 458 compatible = "ti,j721e-uart", "ti,am654-uart"; 459 reg = <0x00 0x02800000 0x00 0x100>; 460 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 461 clock-frequency = <48000000>; 462 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 463 clocks = <&k3_clks 146 2>; 464 clock-names = "fclk"; 465 status = "disabled"; 466 }; 467 468 main_uart1: serial@2810000 { 469 compatible = "ti,j721e-uart", "ti,am654-uart"; 470 reg = <0x00 0x02810000 0x00 0x100>; 471 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 472 clock-frequency = <48000000>; 473 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 474 clocks = <&k3_clks 278 2>; 475 clock-names = "fclk"; 476 status = "disabled"; 477 }; 478 479 main_uart2: serial@2820000 { 480 compatible = "ti,j721e-uart", "ti,am654-uart"; 481 reg = <0x00 0x02820000 0x00 0x100>; 482 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 483 clock-frequency = <48000000>; 484 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 485 clocks = <&k3_clks 279 2>; 486 clock-names = "fclk"; 487 status = "disabled"; 488 }; 489 490 main_uart3: serial@2830000 { 491 compatible = "ti,j721e-uart", "ti,am654-uart"; 492 reg = <0x00 0x02830000 0x00 0x100>; 493 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 494 clock-frequency = <48000000>; 495 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 496 clocks = <&k3_clks 280 2>; 497 clock-names = "fclk"; 498 status = "disabled"; 499 }; 500 501 main_uart4: serial@2840000 { 502 compatible = "ti,j721e-uart", "ti,am654-uart"; 503 reg = <0x00 0x02840000 0x00 0x100>; 504 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 505 clock-frequency = <48000000>; 506 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 507 clocks = <&k3_clks 281 2>; 508 clock-names = "fclk"; 509 status = "disabled"; 510 }; 511 512 main_uart5: serial@2850000 { 513 compatible = "ti,j721e-uart", "ti,am654-uart"; 514 reg = <0x00 0x02850000 0x00 0x100>; 515 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 516 clock-frequency = <48000000>; 517 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 518 clocks = <&k3_clks 282 2>; 519 clock-names = "fclk"; 520 status = "disabled"; 521 }; 522 523 main_uart6: serial@2860000 { 524 compatible = "ti,j721e-uart", "ti,am654-uart"; 525 reg = <0x00 0x02860000 0x00 0x100>; 526 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 527 clock-frequency = <48000000>; 528 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 529 clocks = <&k3_clks 283 2>; 530 clock-names = "fclk"; 531 status = "disabled"; 532 }; 533 534 main_uart7: serial@2870000 { 535 compatible = "ti,j721e-uart", "ti,am654-uart"; 536 reg = <0x00 0x02870000 0x00 0x100>; 537 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 538 clock-frequency = <48000000>; 539 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 540 clocks = <&k3_clks 284 2>; 541 clock-names = "fclk"; 542 status = "disabled"; 543 }; 544 545 main_uart8: serial@2880000 { 546 compatible = "ti,j721e-uart", "ti,am654-uart"; 547 reg = <0x00 0x02880000 0x00 0x100>; 548 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 549 clock-frequency = <48000000>; 550 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 551 clocks = <&k3_clks 285 2>; 552 clock-names = "fclk"; 553 status = "disabled"; 554 }; 555 556 main_uart9: serial@2890000 { 557 compatible = "ti,j721e-uart", "ti,am654-uart"; 558 reg = <0x00 0x02890000 0x00 0x100>; 559 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 560 clock-frequency = <48000000>; 561 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 562 clocks = <&k3_clks 286 2>; 563 clock-names = "fclk"; 564 status = "disabled"; 565 }; 566 567 main_i2c0: i2c@2000000 { 568 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 569 reg = <0x00 0x2000000 0x00 0x100>; 570 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 571 #address-cells = <1>; 572 #size-cells = <0>; 573 clock-names = "fck"; 574 clocks = <&k3_clks 187 1>; 575 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 576 status = "disabled"; 577 }; 578 579 main_i2c1: i2c@2010000 { 580 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 581 reg = <0x00 0x2010000 0x00 0x100>; 582 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 583 #address-cells = <1>; 584 #size-cells = <0>; 585 clock-names = "fck"; 586 clocks = <&k3_clks 188 1>; 587 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 588 status = "disabled"; 589 }; 590 591 main_i2c2: i2c@2020000 { 592 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 593 reg = <0x00 0x2020000 0x00 0x100>; 594 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 595 #address-cells = <1>; 596 #size-cells = <0>; 597 clock-names = "fck"; 598 clocks = <&k3_clks 189 1>; 599 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 600 status = "disabled"; 601 }; 602 603 main_i2c3: i2c@2030000 { 604 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 605 reg = <0x00 0x2030000 0x00 0x100>; 606 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 607 #address-cells = <1>; 608 #size-cells = <0>; 609 clock-names = "fck"; 610 clocks = <&k3_clks 190 1>; 611 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 612 status = "disabled"; 613 }; 614 615 main_i2c4: i2c@2040000 { 616 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 617 reg = <0x00 0x2040000 0x00 0x100>; 618 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 619 #address-cells = <1>; 620 #size-cells = <0>; 621 clock-names = "fck"; 622 clocks = <&k3_clks 191 1>; 623 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 624 status = "disabled"; 625 }; 626 627 main_i2c5: i2c@2050000 { 628 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 629 reg = <0x00 0x2050000 0x00 0x100>; 630 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 631 #address-cells = <1>; 632 #size-cells = <0>; 633 clock-names = "fck"; 634 clocks = <&k3_clks 192 1>; 635 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 636 status = "disabled"; 637 }; 638 639 main_i2c6: i2c@2060000 { 640 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 641 reg = <0x00 0x2060000 0x00 0x100>; 642 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 643 #address-cells = <1>; 644 #size-cells = <0>; 645 clock-names = "fck"; 646 clocks = <&k3_clks 193 1>; 647 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 648 status = "disabled"; 649 }; 650 651 main_sdhci0: mmc@4f80000 { 652 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit"; 653 reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; 654 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 655 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 656 clock-names = "clk_ahb", "clk_xin"; 657 clocks = <&k3_clks 91 0>, <&k3_clks 91 3>; 658 ti,otap-del-sel-legacy = <0x0>; 659 ti,otap-del-sel-mmc-hs = <0x0>; 660 ti,otap-del-sel-ddr52 = <0x6>; 661 ti,otap-del-sel-hs200 = <0x8>; 662 ti,otap-del-sel-hs400 = <0x5>; 663 ti,itap-del-sel-legacy = <0x10>; 664 ti,itap-del-sel-mmc-hs = <0xa>; 665 ti,itap-del-sel-ddr52 = <0x3>; 666 ti,strobe-sel = <0x77>; 667 ti,clkbuf-sel = <0x7>; 668 ti,trm-icp = <0x8>; 669 bus-width = <8>; 670 mmc-ddr-1_8v; 671 mmc-hs200-1_8v; 672 mmc-hs400-1_8v; 673 dma-coherent; 674 status = "disabled"; 675 }; 676 677 main_sdhci1: mmc@4fb0000 { 678 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit"; 679 reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; 680 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 681 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 682 clock-names = "clk_ahb", "clk_xin"; 683 clocks = <&k3_clks 92 1>, <&k3_clks 92 2>; 684 ti,otap-del-sel-legacy = <0x0>; 685 ti,otap-del-sel-sd-hs = <0x0>; 686 ti,otap-del-sel-sdr12 = <0xf>; 687 ti,otap-del-sel-sdr25 = <0xf>; 688 ti,otap-del-sel-sdr50 = <0xc>; 689 ti,otap-del-sel-sdr104 = <0x5>; 690 ti,otap-del-sel-ddr50 = <0xc>; 691 ti,itap-del-sel-legacy = <0x0>; 692 ti,itap-del-sel-sd-hs = <0x0>; 693 ti,itap-del-sel-sdr12 = <0x0>; 694 ti,itap-del-sel-sdr25 = <0x0>; 695 ti,clkbuf-sel = <0x7>; 696 ti,trm-icp = <0x8>; 697 dma-coherent; 698 status = "disabled"; 699 }; 700 701 serdes_wiz0: wiz@5060000 { 702 compatible = "ti,j721e-wiz-10g"; 703 #address-cells = <1>; 704 #size-cells = <1>; 705 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 706 clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>; 707 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 708 num-lanes = <4>; 709 #reset-cells = <1>; 710 ranges = <0x5060000 0x0 0x5060000 0x10000>; 711 712 assigned-clocks = <&k3_clks 292 85>; 713 assigned-clock-parents = <&k3_clks 292 89>; 714 715 wiz0_pll0_refclk: pll0-refclk { 716 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 717 clock-output-names = "wiz0_pll0_refclk"; 718 #clock-cells = <0>; 719 assigned-clocks = <&wiz0_pll0_refclk>; 720 assigned-clock-parents = <&k3_clks 292 85>; 721 }; 722 723 wiz0_pll1_refclk: pll1-refclk { 724 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 725 clock-output-names = "wiz0_pll1_refclk"; 726 #clock-cells = <0>; 727 assigned-clocks = <&wiz0_pll1_refclk>; 728 assigned-clock-parents = <&k3_clks 292 85>; 729 }; 730 731 wiz0_refclk_dig: refclk-dig { 732 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 733 clock-output-names = "wiz0_refclk_dig"; 734 #clock-cells = <0>; 735 assigned-clocks = <&wiz0_refclk_dig>; 736 assigned-clock-parents = <&k3_clks 292 85>; 737 }; 738 739 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 740 clocks = <&wiz0_refclk_dig>; 741 #clock-cells = <0>; 742 }; 743 744 serdes0: serdes@5060000 { 745 compatible = "ti,j721e-serdes-10g"; 746 reg = <0x05060000 0x00010000>; 747 reg-names = "torrent_phy"; 748 resets = <&serdes_wiz0 0>; 749 reset-names = "torrent_reset"; 750 clocks = <&wiz0_pll0_refclk>; 751 clock-names = "refclk"; 752 #address-cells = <1>; 753 #size-cells = <0>; 754 }; 755 }; 756 757 pcie1_rc: pcie@2910000 { 758 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; 759 reg = <0x00 0x02910000 0x00 0x1000>, 760 <0x00 0x02917000 0x00 0x400>, 761 <0x00 0x0d800000 0x00 0x00800000>, 762 <0x00 0x18000000 0x00 0x00001000>; 763 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 764 interrupt-names = "link_state"; 765 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 766 device_type = "pci"; 767 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 768 max-link-speed = <3>; 769 num-lanes = <4>; 770 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 771 clocks = <&k3_clks 240 6>; 772 clock-names = "fck"; 773 #address-cells = <3>; 774 #size-cells = <2>; 775 bus-range = <0x0 0xff>; 776 cdns,no-bar-match-nbits = <64>; 777 vendor-id = <0x104c>; 778 device-id = <0xb00f>; 779 msi-map = <0x0 &gic_its 0x0 0x10000>; 780 dma-coherent; 781 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, 782 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; 783 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 784 status = "disabled"; 785 }; 786 787 usbss0: cdns-usb@4104000 { 788 compatible = "ti,j721e-usb"; 789 reg = <0x00 0x4104000 0x00 0x100>; 790 dma-coherent; 791 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 792 clocks = <&k3_clks 288 12>, <&k3_clks 288 3>; 793 clock-names = "ref", "lpm"; 794 assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */ 795 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */ 796 #address-cells = <2>; 797 #size-cells = <2>; 798 ranges; 799 800 usb0: usb@6000000 { 801 compatible = "cdns,usb3"; 802 reg = <0x00 0x6000000 0x00 0x10000>, 803 <0x00 0x6010000 0x00 0x10000>, 804 <0x00 0x6020000 0x00 0x10000>; 805 reg-names = "otg", "xhci", "dev"; 806 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 807 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 808 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 809 interrupt-names = "host", 810 "peripheral", 811 "otg"; 812 maximum-speed = "super-speed"; 813 dr_mode = "otg"; 814 cdns,phyrst-a-enable; 815 }; 816 }; 817 818 main_gpio0: gpio@600000 { 819 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 820 reg = <0x00 0x00600000 0x00 0x100>; 821 gpio-controller; 822 #gpio-cells = <2>; 823 interrupt-parent = <&main_gpio_intr>; 824 interrupts = <145>, <146>, <147>, <148>, 825 <149>; 826 interrupt-controller; 827 #interrupt-cells = <2>; 828 ti,ngpio = <69>; 829 ti,davinci-gpio-unbanked = <0>; 830 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 831 clocks = <&k3_clks 105 0>; 832 clock-names = "gpio"; 833 status = "disabled"; 834 }; 835 836 main_gpio2: gpio@610000 { 837 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 838 reg = <0x00 0x00610000 0x00 0x100>; 839 gpio-controller; 840 #gpio-cells = <2>; 841 interrupt-parent = <&main_gpio_intr>; 842 interrupts = <154>, <155>, <156>, <157>, 843 <158>; 844 interrupt-controller; 845 #interrupt-cells = <2>; 846 ti,ngpio = <69>; 847 ti,davinci-gpio-unbanked = <0>; 848 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 849 clocks = <&k3_clks 107 0>; 850 clock-names = "gpio"; 851 status = "disabled"; 852 }; 853 854 main_gpio4: gpio@620000 { 855 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 856 reg = <0x00 0x00620000 0x00 0x100>; 857 gpio-controller; 858 #gpio-cells = <2>; 859 interrupt-parent = <&main_gpio_intr>; 860 interrupts = <163>, <164>, <165>, <166>, 861 <167>; 862 interrupt-controller; 863 #interrupt-cells = <2>; 864 ti,ngpio = <69>; 865 ti,davinci-gpio-unbanked = <0>; 866 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 867 clocks = <&k3_clks 109 0>; 868 clock-names = "gpio"; 869 status = "disabled"; 870 }; 871 872 main_gpio6: gpio@630000 { 873 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 874 reg = <0x00 0x00630000 0x00 0x100>; 875 gpio-controller; 876 #gpio-cells = <2>; 877 interrupt-parent = <&main_gpio_intr>; 878 interrupts = <172>, <173>, <174>, <175>, 879 <176>; 880 interrupt-controller; 881 #interrupt-cells = <2>; 882 ti,ngpio = <69>; 883 ti,davinci-gpio-unbanked = <0>; 884 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 885 clocks = <&k3_clks 111 0>; 886 clock-names = "gpio"; 887 status = "disabled"; 888 }; 889 890 main_mcan0: can@2701000 { 891 compatible = "bosch,m_can"; 892 reg = <0x00 0x02701000 0x00 0x200>, 893 <0x00 0x02708000 0x00 0x8000>; 894 reg-names = "m_can", "message_ram"; 895 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 896 clocks = <&k3_clks 156 0>, <&k3_clks 156 2>; 897 clock-names = "hclk", "cclk"; 898 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 900 interrupt-names = "int0", "int1"; 901 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 902 status = "disabled"; 903 }; 904 905 main_mcan1: can@2711000 { 906 compatible = "bosch,m_can"; 907 reg = <0x00 0x02711000 0x00 0x200>, 908 <0x00 0x02718000 0x00 0x8000>; 909 reg-names = "m_can", "message_ram"; 910 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 911 clocks = <&k3_clks 158 0>, <&k3_clks 158 2>; 912 clock-names = "hclk", "cclk"; 913 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 915 interrupt-names = "int0", "int1"; 916 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 917 status = "disabled"; 918 }; 919 920 main_mcan2: can@2721000 { 921 compatible = "bosch,m_can"; 922 reg = <0x00 0x02721000 0x00 0x200>, 923 <0x00 0x02728000 0x00 0x8000>; 924 reg-names = "m_can", "message_ram"; 925 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; 926 clocks = <&k3_clks 160 0>, <&k3_clks 160 2>; 927 clock-names = "hclk", "cclk"; 928 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 930 interrupt-names = "int0", "int1"; 931 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 932 status = "disabled"; 933 }; 934 935 main_mcan3: can@2731000 { 936 compatible = "bosch,m_can"; 937 reg = <0x00 0x02731000 0x00 0x200>, 938 <0x00 0x02738000 0x00 0x8000>; 939 reg-names = "m_can", "message_ram"; 940 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 941 clocks = <&k3_clks 161 0>, <&k3_clks 161 2>; 942 clock-names = "hclk", "cclk"; 943 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 945 interrupt-names = "int0", "int1"; 946 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 947 status = "disabled"; 948 }; 949 950 main_mcan4: can@2741000 { 951 compatible = "bosch,m_can"; 952 reg = <0x00 0x02741000 0x00 0x200>, 953 <0x00 0x02748000 0x00 0x8000>; 954 reg-names = "m_can", "message_ram"; 955 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 956 clocks = <&k3_clks 162 0>, <&k3_clks 162 2>; 957 clock-names = "hclk", "cclk"; 958 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 960 interrupt-names = "int0", "int1"; 961 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 962 status = "disabled"; 963 }; 964 965 main_mcan5: can@2751000 { 966 compatible = "bosch,m_can"; 967 reg = <0x00 0x02751000 0x00 0x200>, 968 <0x00 0x02758000 0x00 0x8000>; 969 reg-names = "m_can", "message_ram"; 970 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; 971 clocks = <&k3_clks 163 0>, <&k3_clks 163 2>; 972 clock-names = "hclk", "cclk"; 973 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 975 interrupt-names = "int0", "int1"; 976 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 977 status = "disabled"; 978 }; 979 980 main_mcan6: can@2761000 { 981 compatible = "bosch,m_can"; 982 reg = <0x00 0x02761000 0x00 0x200>, 983 <0x00 0x02768000 0x00 0x8000>; 984 reg-names = "m_can", "message_ram"; 985 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; 986 clocks = <&k3_clks 164 0>, <&k3_clks 164 2>; 987 clock-names = "hclk", "cclk"; 988 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 990 interrupt-names = "int0", "int1"; 991 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 992 status = "disabled"; 993 }; 994 995 main_mcan7: can@2771000 { 996 compatible = "bosch,m_can"; 997 reg = <0x00 0x02771000 0x00 0x200>, 998 <0x00 0x02778000 0x00 0x8000>; 999 reg-names = "m_can", "message_ram"; 1000 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; 1001 clocks = <&k3_clks 165 0>, <&k3_clks 165 2>; 1002 clock-names = "hclk", "cclk"; 1003 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1004 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1005 interrupt-names = "int0", "int1"; 1006 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1007 status = "disabled"; 1008 }; 1009 1010 main_mcan8: can@2781000 { 1011 compatible = "bosch,m_can"; 1012 reg = <0x00 0x02781000 0x00 0x200>, 1013 <0x00 0x02788000 0x00 0x8000>; 1014 reg-names = "m_can", "message_ram"; 1015 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; 1016 clocks = <&k3_clks 166 0>, <&k3_clks 166 2>; 1017 clock-names = "hclk", "cclk"; 1018 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 1019 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 1020 interrupt-names = "int0", "int1"; 1021 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1022 status = "disabled"; 1023 }; 1024 1025 main_mcan9: can@2791000 { 1026 compatible = "bosch,m_can"; 1027 reg = <0x00 0x02791000 0x00 0x200>, 1028 <0x00 0x02798000 0x00 0x8000>; 1029 reg-names = "m_can", "message_ram"; 1030 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>; 1031 clocks = <&k3_clks 167 0>, <&k3_clks 167 2>; 1032 clock-names = "hclk", "cclk"; 1033 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, 1034 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 1035 interrupt-names = "int0", "int1"; 1036 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1037 status = "disabled"; 1038 }; 1039 1040 main_mcan10: can@27a1000 { 1041 compatible = "bosch,m_can"; 1042 reg = <0x00 0x027a1000 0x00 0x200>, 1043 <0x00 0x027a8000 0x00 0x8000>; 1044 reg-names = "m_can", "message_ram"; 1045 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>; 1046 clocks = <&k3_clks 168 0>, <&k3_clks 168 2>; 1047 clock-names = "hclk", "cclk"; 1048 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, 1049 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1050 interrupt-names = "int0", "int1"; 1051 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1052 status = "disabled"; 1053 }; 1054 1055 main_mcan11: can@27b1000 { 1056 compatible = "bosch,m_can"; 1057 reg = <0x00 0x027b1000 0x00 0x200>, 1058 <0x00 0x027b8000 0x00 0x8000>; 1059 reg-names = "m_can", "message_ram"; 1060 power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>; 1061 clocks = <&k3_clks 169 0>, <&k3_clks 169 2>; 1062 clock-names = "hclk", "cclk"; 1063 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1065 interrupt-names = "int0", "int1"; 1066 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1067 status = "disabled"; 1068 }; 1069 1070 main_mcan12: can@27c1000 { 1071 compatible = "bosch,m_can"; 1072 reg = <0x00 0x027c1000 0x00 0x200>, 1073 <0x00 0x027c8000 0x00 0x8000>; 1074 reg-names = "m_can", "message_ram"; 1075 power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>; 1076 clocks = <&k3_clks 170 0>, <&k3_clks 170 2>; 1077 clock-names = "hclk", "cclk"; 1078 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 1080 interrupt-names = "int0", "int1"; 1081 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1082 status = "disabled"; 1083 }; 1084 1085 main_mcan13: can@27d1000 { 1086 compatible = "bosch,m_can"; 1087 reg = <0x00 0x027d1000 0x00 0x200>, 1088 <0x00 0x027d8000 0x00 0x8000>; 1089 reg-names = "m_can", "message_ram"; 1090 power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>; 1091 clocks = <&k3_clks 171 0>, <&k3_clks 171 2>; 1092 clock-names = "hclk", "cclk"; 1093 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1094 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 1095 interrupt-names = "int0", "int1"; 1096 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1097 status = "disabled"; 1098 }; 1099 1100 main_mcan14: can@2681000 { 1101 compatible = "bosch,m_can"; 1102 reg = <0x00 0x02681000 0x00 0x200>, 1103 <0x00 0x02688000 0x00 0x8000>; 1104 reg-names = "m_can", "message_ram"; 1105 power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>; 1106 clocks = <&k3_clks 150 0>, <&k3_clks 150 2>; 1107 clock-names = "hclk", "cclk"; 1108 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>; 1110 interrupt-names = "int0", "int1"; 1111 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1112 status = "disabled"; 1113 }; 1114 1115 main_mcan15: can@2691000 { 1116 compatible = "bosch,m_can"; 1117 reg = <0x00 0x02691000 0x00 0x200>, 1118 <0x00 0x02698000 0x00 0x8000>; 1119 reg-names = "m_can", "message_ram"; 1120 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; 1121 clocks = <&k3_clks 151 0>, <&k3_clks 151 2>; 1122 clock-names = "hclk", "cclk"; 1123 interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; 1125 interrupt-names = "int0", "int1"; 1126 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1127 status = "disabled"; 1128 }; 1129 1130 main_mcan16: can@26a1000 { 1131 compatible = "bosch,m_can"; 1132 reg = <0x00 0x026a1000 0x00 0x200>, 1133 <0x00 0x026a8000 0x00 0x8000>; 1134 reg-names = "m_can", "message_ram"; 1135 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 1136 clocks = <&k3_clks 152 0>, <&k3_clks 152 2>; 1137 clock-names = "hclk", "cclk"; 1138 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1139 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 1140 interrupt-names = "int0", "int1"; 1141 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1142 status = "disabled"; 1143 }; 1144 1145 main_mcan17: can@26b1000 { 1146 compatible = "bosch,m_can"; 1147 reg = <0x00 0x026b1000 0x00 0x200>, 1148 <0x00 0x026b8000 0x00 0x8000>; 1149 reg-names = "m_can", "message_ram"; 1150 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 1151 clocks = <&k3_clks 153 0>, <&k3_clks 153 2>; 1152 clock-names = "hclk", "cclk"; 1153 interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 1154 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>; 1155 interrupt-names = "int0", "int1"; 1156 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1157 status = "disabled"; 1158 }; 1159 1160 main_spi0: spi@2100000 { 1161 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1162 reg = <0x00 0x02100000 0x00 0x400>; 1163 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1164 #address-cells = <1>; 1165 #size-cells = <0>; 1166 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; 1167 clocks = <&k3_clks 266 4>; 1168 status = "disabled"; 1169 }; 1170 1171 main_spi1: spi@2110000 { 1172 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1173 reg = <0x00 0x02110000 0x00 0x400>; 1174 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; 1178 clocks = <&k3_clks 267 4>; 1179 status = "disabled"; 1180 }; 1181 1182 main_spi2: spi@2120000 { 1183 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1184 reg = <0x00 0x02120000 0x00 0x400>; 1185 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1186 #address-cells = <1>; 1187 #size-cells = <0>; 1188 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; 1189 clocks = <&k3_clks 268 4>; 1190 status = "disabled"; 1191 }; 1192 1193 main_spi3: spi@2130000 { 1194 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1195 reg = <0x00 0x02130000 0x00 0x400>; 1196 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; 1200 clocks = <&k3_clks 269 4>; 1201 status = "disabled"; 1202 }; 1203 1204 main_spi4: spi@2140000 { 1205 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1206 reg = <0x00 0x02140000 0x00 0x400>; 1207 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1208 #address-cells = <1>; 1209 #size-cells = <0>; 1210 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; 1211 clocks = <&k3_clks 270 2>; 1212 status = "disabled"; 1213 }; 1214 1215 main_spi5: spi@2150000 { 1216 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1217 reg = <0x00 0x02150000 0x00 0x400>; 1218 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; 1222 clocks = <&k3_clks 271 4>; 1223 status = "disabled"; 1224 }; 1225 1226 main_spi6: spi@2160000 { 1227 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1228 reg = <0x00 0x02160000 0x00 0x400>; 1229 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1230 #address-cells = <1>; 1231 #size-cells = <0>; 1232 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; 1233 clocks = <&k3_clks 272 4>; 1234 status = "disabled"; 1235 }; 1236 1237 main_spi7: spi@2170000 { 1238 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1239 reg = <0x00 0x02170000 0x00 0x400>; 1240 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; 1244 clocks = <&k3_clks 273 4>; 1245 status = "disabled"; 1246 }; 1247 1248 watchdog0: watchdog@2200000 { 1249 compatible = "ti,j7-rti-wdt"; 1250 reg = <0x0 0x2200000 0x0 0x100>; 1251 clocks = <&k3_clks 252 1>; 1252 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 1253 assigned-clocks = <&k3_clks 252 1>; 1254 assigned-clock-parents = <&k3_clks 252 5>; 1255 }; 1256 1257 watchdog1: watchdog@2210000 { 1258 compatible = "ti,j7-rti-wdt"; 1259 reg = <0x0 0x2210000 0x0 0x100>; 1260 clocks = <&k3_clks 253 1>; 1261 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 1262 assigned-clocks = <&k3_clks 253 1>; 1263 assigned-clock-parents = <&k3_clks 253 5>; 1264 }; 1265 1266 main_timer0: timer@2400000 { 1267 compatible = "ti,am654-timer"; 1268 reg = <0x00 0x2400000 0x00 0x400>; 1269 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 1270 clocks = <&k3_clks 49 1>; 1271 clock-names = "fck"; 1272 assigned-clocks = <&k3_clks 49 1>; 1273 assigned-clock-parents = <&k3_clks 49 2>; 1274 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; 1275 ti,timer-pwm; 1276 }; 1277 1278 main_timer1: timer@2410000 { 1279 compatible = "ti,am654-timer"; 1280 reg = <0x00 0x2410000 0x00 0x400>; 1281 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1282 clocks = <&k3_clks 50 1>; 1283 clock-names = "fck"; 1284 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>; 1285 assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 313 1>; 1286 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; 1287 ti,timer-pwm; 1288 }; 1289 1290 main_timer2: timer@2420000 { 1291 compatible = "ti,am654-timer"; 1292 reg = <0x00 0x2420000 0x00 0x400>; 1293 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1294 clocks = <&k3_clks 51 1>; 1295 clock-names = "fck"; 1296 assigned-clocks = <&k3_clks 51 1>; 1297 assigned-clock-parents = <&k3_clks 51 2>; 1298 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; 1299 ti,timer-pwm; 1300 }; 1301 1302 main_timer3: timer@2430000 { 1303 compatible = "ti,am654-timer"; 1304 reg = <0x00 0x2430000 0x00 0x400>; 1305 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 1306 clocks = <&k3_clks 52 1>; 1307 clock-names = "fck"; 1308 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>; 1309 assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 314 1>; 1310 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 1311 ti,timer-pwm; 1312 }; 1313 1314 main_timer4: timer@2440000 { 1315 compatible = "ti,am654-timer"; 1316 reg = <0x00 0x2440000 0x00 0x400>; 1317 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 1318 clocks = <&k3_clks 53 1>; 1319 clock-names = "fck"; 1320 assigned-clocks = <&k3_clks 53 1>; 1321 assigned-clock-parents = <&k3_clks 53 2>; 1322 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 1323 ti,timer-pwm; 1324 }; 1325 1326 main_timer5: timer@2450000 { 1327 compatible = "ti,am654-timer"; 1328 reg = <0x00 0x2450000 0x00 0x400>; 1329 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 1330 clocks = <&k3_clks 54 1>; 1331 clock-names = "fck"; 1332 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>; 1333 assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 315 1>; 1334 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; 1335 ti,timer-pwm; 1336 }; 1337 1338 main_timer6: timer@2460000 { 1339 compatible = "ti,am654-timer"; 1340 reg = <0x00 0x2460000 0x00 0x400>; 1341 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 1342 clocks = <&k3_clks 55 1>; 1343 clock-names = "fck"; 1344 assigned-clocks = <&k3_clks 55 1>; 1345 assigned-clock-parents = <&k3_clks 55 2>; 1346 power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>; 1347 ti,timer-pwm; 1348 }; 1349 1350 main_timer7: timer@2470000 { 1351 compatible = "ti,am654-timer"; 1352 reg = <0x00 0x2470000 0x00 0x400>; 1353 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 1354 clocks = <&k3_clks 57 1>; 1355 clock-names = "fck"; 1356 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>; 1357 assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 316 1>; 1358 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 1359 ti,timer-pwm; 1360 }; 1361 1362 main_timer8: timer@2480000 { 1363 compatible = "ti,am654-timer"; 1364 reg = <0x00 0x2480000 0x00 0x400>; 1365 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 1366 clocks = <&k3_clks 58 1>; 1367 clock-names = "fck"; 1368 assigned-clocks = <&k3_clks 58 1>; 1369 assigned-clock-parents = <&k3_clks 58 2>; 1370 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 1371 ti,timer-pwm; 1372 }; 1373 1374 main_timer9: timer@2490000 { 1375 compatible = "ti,am654-timer"; 1376 reg = <0x00 0x2490000 0x00 0x400>; 1377 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 1378 clocks = <&k3_clks 59 1>; 1379 clock-names = "fck"; 1380 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>; 1381 assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 317 1>; 1382 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; 1383 ti,timer-pwm; 1384 }; 1385 1386 main_timer10: timer@24a0000 { 1387 compatible = "ti,am654-timer"; 1388 reg = <0x00 0x24a0000 0x00 0x400>; 1389 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 1390 clocks = <&k3_clks 60 1>; 1391 clock-names = "fck"; 1392 assigned-clocks = <&k3_clks 60 1>; 1393 assigned-clock-parents = <&k3_clks 60 2>; 1394 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; 1395 ti,timer-pwm; 1396 }; 1397 1398 main_timer11: timer@24b0000 { 1399 compatible = "ti,am654-timer"; 1400 reg = <0x00 0x24b0000 0x00 0x400>; 1401 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 1402 clocks = <&k3_clks 62 1>; 1403 clock-names = "fck"; 1404 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>; 1405 assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 318 1>; 1406 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 1407 ti,timer-pwm; 1408 }; 1409 1410 main_timer12: timer@24c0000 { 1411 compatible = "ti,am654-timer"; 1412 reg = <0x00 0x24c0000 0x00 0x400>; 1413 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 1414 clocks = <&k3_clks 63 1>; 1415 clock-names = "fck"; 1416 assigned-clocks = <&k3_clks 63 1>; 1417 assigned-clock-parents = <&k3_clks 63 2>; 1418 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 1419 ti,timer-pwm; 1420 }; 1421 1422 main_timer13: timer@24d0000 { 1423 compatible = "ti,am654-timer"; 1424 reg = <0x00 0x24d0000 0x00 0x400>; 1425 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 1426 clocks = <&k3_clks 64 1>; 1427 clock-names = "fck"; 1428 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>; 1429 assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 319 1>; 1430 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 1431 ti,timer-pwm; 1432 }; 1433 1434 main_timer14: timer@24e0000 { 1435 compatible = "ti,am654-timer"; 1436 reg = <0x00 0x24e0000 0x00 0x400>; 1437 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1438 clocks = <&k3_clks 65 1>; 1439 clock-names = "fck"; 1440 assigned-clocks = <&k3_clks 65 1>; 1441 assigned-clock-parents = <&k3_clks 65 2>; 1442 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; 1443 ti,timer-pwm; 1444 }; 1445 1446 main_timer15: timer@24f0000 { 1447 compatible = "ti,am654-timer"; 1448 reg = <0x00 0x24f0000 0x00 0x400>; 1449 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1450 clocks = <&k3_clks 66 1>; 1451 clock-names = "fck"; 1452 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>; 1453 assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 320 1>; 1454 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; 1455 ti,timer-pwm; 1456 }; 1457 1458 main_timer16: timer@2500000 { 1459 compatible = "ti,am654-timer"; 1460 reg = <0x00 0x2500000 0x00 0x400>; 1461 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1462 clocks = <&k3_clks 67 1>; 1463 clock-names = "fck"; 1464 assigned-clocks = <&k3_clks 67 1>; 1465 assigned-clock-parents = <&k3_clks 67 2>; 1466 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 1467 ti,timer-pwm; 1468 }; 1469 1470 main_timer17: timer@2510000 { 1471 compatible = "ti,am654-timer"; 1472 reg = <0x00 0x2510000 0x00 0x400>; 1473 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1474 clocks = <&k3_clks 68 1>; 1475 clock-names = "fck"; 1476 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>; 1477 assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 321 1>; 1478 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; 1479 ti,timer-pwm; 1480 }; 1481 1482 main_timer18: timer@2520000 { 1483 compatible = "ti,am654-timer"; 1484 reg = <0x00 0x2520000 0x00 0x400>; 1485 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1486 clocks = <&k3_clks 69 1>; 1487 clock-names = "fck"; 1488 assigned-clocks = <&k3_clks 69 1>; 1489 assigned-clock-parents = <&k3_clks 69 2>; 1490 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; 1491 ti,timer-pwm; 1492 }; 1493 1494 main_timer19: timer@2530000 { 1495 compatible = "ti,am654-timer"; 1496 reg = <0x00 0x2530000 0x00 0x400>; 1497 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1498 clocks = <&k3_clks 70 1>; 1499 clock-names = "fck"; 1500 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>; 1501 assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 322 1>; 1502 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; 1503 ti,timer-pwm; 1504 }; 1505 1506 main_r5fss0: r5fss@5c00000 { 1507 compatible = "ti,j7200-r5fss"; 1508 ti,cluster-mode = <1>; 1509 #address-cells = <1>; 1510 #size-cells = <1>; 1511 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 1512 <0x5d00000 0x00 0x5d00000 0x20000>; 1513 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; 1514 1515 main_r5fss0_core0: r5f@5c00000 { 1516 compatible = "ti,j7200-r5f"; 1517 reg = <0x5c00000 0x00010000>, 1518 <0x5c10000 0x00010000>; 1519 reg-names = "atcm", "btcm"; 1520 ti,sci = <&dmsc>; 1521 ti,sci-dev-id = <245>; 1522 ti,sci-proc-ids = <0x06 0xff>; 1523 resets = <&k3_reset 245 1>; 1524 firmware-name = "j7200-main-r5f0_0-fw"; 1525 ti,atcm-enable = <1>; 1526 ti,btcm-enable = <1>; 1527 ti,loczrama = <1>; 1528 }; 1529 1530 main_r5fss0_core1: r5f@5d00000 { 1531 compatible = "ti,j7200-r5f"; 1532 reg = <0x5d00000 0x00008000>, 1533 <0x5d10000 0x00008000>; 1534 reg-names = "atcm", "btcm"; 1535 ti,sci = <&dmsc>; 1536 ti,sci-dev-id = <246>; 1537 ti,sci-proc-ids = <0x07 0xff>; 1538 resets = <&k3_reset 246 1>; 1539 firmware-name = "j7200-main-r5f0_1-fw"; 1540 ti,atcm-enable = <1>; 1541 ti,btcm-enable = <1>; 1542 ti,loczrama = <1>; 1543 }; 1544 }; 1545 1546 main_esm: esm@700000 { 1547 compatible = "ti,j721e-esm"; 1548 reg = <0x0 0x700000 0x0 0x1000>; 1549 bootph-pre-ram; 1550 ti,esm-pins = <656>, <657>; 1551 }; 1552}; 1553