1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include "k3-j7200-som-p0.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/net/ti-dp83867.h> 11#include <dt-bindings/phy/phy.h> 12 13#include "k3-serdes.h" 14 15/ { 16 compatible = "ti,j7200-evm", "ti,j7200"; 17 model = "Texas Instruments J7200 EVM"; 18 19 aliases { 20 serial0 = &wkup_uart0; 21 serial1 = &mcu_uart0; 22 serial2 = &main_uart0; 23 serial3 = &main_uart1; 24 serial5 = &main_uart3; 25 mmc0 = &main_sdhci0; 26 mmc1 = &main_sdhci1; 27 }; 28 29 chosen { 30 stdout-path = "serial2:115200n8"; 31 }; 32 33 evm_12v0: fixedregulator-evm12v0 { 34 /* main supply */ 35 compatible = "regulator-fixed"; 36 regulator-name = "evm_12v0"; 37 regulator-min-microvolt = <12000000>; 38 regulator-max-microvolt = <12000000>; 39 regulator-always-on; 40 regulator-boot-on; 41 }; 42 43 vsys_3v3: fixedregulator-vsys3v3 { 44 /* Output of LM5140 */ 45 compatible = "regulator-fixed"; 46 regulator-name = "vsys_3v3"; 47 regulator-min-microvolt = <3300000>; 48 regulator-max-microvolt = <3300000>; 49 vin-supply = <&evm_12v0>; 50 regulator-always-on; 51 regulator-boot-on; 52 }; 53 54 vsys_5v0: fixedregulator-vsys5v0 { 55 /* Output of LM5140 */ 56 compatible = "regulator-fixed"; 57 regulator-name = "vsys_5v0"; 58 regulator-min-microvolt = <5000000>; 59 regulator-max-microvolt = <5000000>; 60 vin-supply = <&evm_12v0>; 61 regulator-always-on; 62 regulator-boot-on; 63 }; 64 65 vdd_mmc1: fixedregulator-sd { 66 /* Output of TPS22918 */ 67 compatible = "regulator-fixed"; 68 regulator-name = "vdd_mmc1"; 69 regulator-min-microvolt = <3300000>; 70 regulator-max-microvolt = <3300000>; 71 regulator-boot-on; 72 enable-active-high; 73 vin-supply = <&vsys_3v3>; 74 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; 75 }; 76 77 vdd_sd_dv: gpio-regulator-TLV71033 { 78 /* Output of TLV71033 */ 79 compatible = "regulator-gpio"; 80 regulator-name = "tlv71033"; 81 pinctrl-names = "default"; 82 pinctrl-0 = <&vdd_sd_dv_pins_default>; 83 regulator-min-microvolt = <1800000>; 84 regulator-max-microvolt = <3300000>; 85 regulator-boot-on; 86 vin-supply = <&vsys_5v0>; 87 gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>; 88 states = <1800000 0x0>, 89 <3300000 0x1>; 90 }; 91 92 transceiver1: can-phy1 { 93 compatible = "ti,tcan1043"; 94 #phy-cells = <0>; 95 max-bitrate = <5000000>; 96 pinctrl-names = "default"; 97 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; 98 standby-gpios = <&wkup_gpio0 58 GPIO_ACTIVE_LOW>; 99 enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>; 100 }; 101 102 transceiver2: can-phy2 { 103 compatible = "ti,tcan1042"; 104 #phy-cells = <0>; 105 max-bitrate = <5000000>; 106 pinctrl-names = "default"; 107 pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; 108 standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; 109 }; 110 111 transceiver3: can-phy3 { 112 compatible = "ti,tcan1043"; 113 #phy-cells = <0>; 114 max-bitrate = <5000000>; 115 standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>; 116 enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>; 117 mux-states = <&mux0 1>; 118 }; 119}; 120 121&wkup_pmx0 { 122}; 123 124&wkup_pmx2 { 125 mcu_uart0_pins_default: mcu-uart0-default-pins { 126 pinctrl-single,pins = < 127 J721E_WKUP_IOPAD(0x90, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */ 128 J721E_WKUP_IOPAD(0x94, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */ 129 J721E_WKUP_IOPAD(0x8c, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ 130 J721E_WKUP_IOPAD(0x88, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ 131 >; 132 bootph-all; 133 }; 134 135 wkup_uart0_pins_default: wkup-uart0-default-pins { 136 pinctrl-single,pins = < 137 J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ 138 J721E_WKUP_IOPAD(0x4c, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ 139 >; 140 bootph-all; 141 }; 142 143 mcu_cpsw_pins_default: mcu-cpsw-default-pins { 144 pinctrl-single,pins = < 145 J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ 146 J721E_WKUP_IOPAD(0x0004, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ 147 J721E_WKUP_IOPAD(0x0008, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ 148 J721E_WKUP_IOPAD(0x000c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ 149 J721E_WKUP_IOPAD(0x0010, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ 150 J721E_WKUP_IOPAD(0x0014, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ 151 J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ 152 J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ 153 J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ 154 J721E_WKUP_IOPAD(0x002c, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ 155 J721E_WKUP_IOPAD(0x0018, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ 156 J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ 157 >; 158 }; 159 160 wkup_gpio_pins_default: wkup-gpio-default-pins { 161 pinctrl-single,pins = < 162 J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */ 163 >; 164 }; 165 166 mcu_mdio_pins_default: mcu-mdio1-default-pins { 167 pinctrl-single,pins = < 168 J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ 169 J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ 170 >; 171 }; 172 173 mcu_mcan0_pins_default: mcu-mcan0-default-pins { 174 pinctrl-single,pins = < 175 J721E_WKUP_IOPAD(0x54, PIN_INPUT, 0) /* (A17) MCU_MCAN0_RX */ 176 J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (A16) MCU_MCAN0_TX */ 177 >; 178 }; 179 180 mcu_mcan1_pins_default: mcu-mcan1-default-pins { 181 pinctrl-single,pins = < 182 J721E_WKUP_IOPAD(0x6c, PIN_INPUT, 0) /* (B16) WKUP_GPIO0_5.MCU_MCAN1_RX */ 183 J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (D13) WKUP_GPIO0_4.MCU_MCAN1_TX */ 184 >; 185 }; 186 187 mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { 188 pinctrl-single,pins = < 189 J721E_WKUP_IOPAD(0x58, PIN_INPUT, 7) /* (B18) WKUP_GPIO0_0 */ 190 J721E_WKUP_IOPAD(0x40, PIN_INPUT, 7) /* (B17) MCU_SPI0_D1 */ 191 >; 192 }; 193 194 mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { 195 pinctrl-single,pins = < 196 J721E_WKUP_IOPAD(0x60, PIN_INPUT, 7) /* (D14) WKUP_GPIO0_2 */ 197 >; 198 }; 199}; 200 201&main_pmx0 { 202 main_uart0_pins_default: main-uart0-default-pins { 203 pinctrl-single,pins = < 204 J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */ 205 J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */ 206 J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */ 207 J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */ 208 >; 209 bootph-all; 210 }; 211 212 main_uart1_pins_default: main-uart1-default-pins { 213 pinctrl-single,pins = < 214 J721E_IOPAD(0xb8, PIN_INPUT, 0) /* (T18) UART1_RXD */ 215 J721E_IOPAD(0xbc, PIN_INPUT, 0) /* (T20) UART1_TXD */ 216 >; 217 }; 218 219 main_uart3_pins_default: main-uart3-default-pins { 220 pinctrl-single,pins = < 221 J721E_IOPAD(0x60, PIN_INPUT, 11) /* (T15) MCAN8_TX.UART3_CTSn */ 222 J721E_IOPAD(0x30, PIN_INPUT, 11) /* (Y18) MCAN2_TX.UART3_RXD */ 223 >; 224 }; 225 226 main_i2c1_pins_default: main-i2c1-default-pins { 227 pinctrl-single,pins = < 228 J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */ 229 J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */ 230 >; 231 }; 232 233 main_mmc1_pins_default: main-mmc1-default-pins { 234 pinctrl-single,pins = < 235 J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */ 236 J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */ 237 J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ 238 J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */ 239 J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */ 240 J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */ 241 J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */ 242 J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */ 243 >; 244 bootph-all; 245 }; 246 247 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { 248 pinctrl-single,pins = < 249 J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */ 250 >; 251 }; 252 253 main_mcan3_pins_default: main-mcan3-default-pins { 254 pinctrl-single,pins = < 255 J721E_IOPAD(0x3c, PIN_INPUT, 0) /* (W16) MCAN3_RX */ 256 J721E_IOPAD(0x38, PIN_OUTPUT, 0) /* (Y21) MCAN3_TX */ 257 >; 258 }; 259}; 260 261&main_pmx2 { 262 main_usbss0_pins_default: main-usbss0-default-pins { 263 pinctrl-single,pins = < 264 J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ 265 >; 266 bootph-all; 267 }; 268}; 269 270&wkup_uart0 { 271 /* Wakeup UART is used by System firmware */ 272 status = "reserved"; 273 pinctrl-names = "default"; 274 pinctrl-0 = <&wkup_uart0_pins_default>; 275 bootph-all; 276}; 277 278&mcu_uart0 { 279 status = "okay"; 280 pinctrl-names = "default"; 281 pinctrl-0 = <&mcu_uart0_pins_default>; 282 bootph-all; 283}; 284 285&main_uart0 { 286 status = "okay"; 287 /* Shared with ATF on this platform */ 288 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 289 pinctrl-names = "default"; 290 pinctrl-0 = <&main_uart0_pins_default>; 291 bootph-all; 292}; 293 294&main_uart1 { 295 status = "okay"; 296 /* Default pinmux */ 297 pinctrl-names = "default"; 298 pinctrl-0 = <&main_uart1_pins_default>; 299}; 300 301&main_uart2 { 302 /* MAIN UART 2 is used by R5F firmware */ 303 status = "reserved"; 304}; 305 306&main_uart3 { 307 /* Shared with MCAN Interface */ 308 status = "okay"; 309 pinctrl-names = "default"; 310 pinctrl-0 = <&main_uart3_pins_default>; 311}; 312 313&main_gpio0 { 314 status = "okay"; 315}; 316 317&wkup_gpio0 { 318 status = "okay"; 319 pinctrl-names = "default"; 320 pinctrl-0 = <&wkup_gpio_pins_default>; 321}; 322 323&mcu_cpsw { 324 pinctrl-names = "default"; 325 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; 326}; 327 328&davinci_mdio { 329 phy0: ethernet-phy@0 { 330 reg = <0>; 331 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 332 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 333 }; 334}; 335 336&cpsw_port1 { 337 phy-mode = "rgmii-rxid"; 338 phy-handle = <&phy0>; 339}; 340 341&main_i2c0 { 342 status = "okay"; 343 pinctrl-names = "default"; 344 pinctrl-0 = <&main_i2c0_pins_default>; 345 clock-frequency = <400000>; 346 347 exp1: gpio@20 { 348 compatible = "ti,tca6416"; 349 reg = <0x20>; 350 gpio-controller; 351 #gpio-cells = <2>; 352 }; 353 354 exp2: gpio@22 { 355 compatible = "ti,tca6424"; 356 reg = <0x22>; 357 gpio-controller; 358 #gpio-cells = <2>; 359 }; 360}; 361 362/* 363 * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be 364 * swapped on the CPB. 365 * 366 * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3. 367 * The i2c1 of the CPB (as it is labeled) is not connected to j7200. 368 */ 369&main_i2c1 { 370 status = "okay"; 371 pinctrl-names = "default"; 372 pinctrl-0 = <&main_i2c1_pins_default>; 373 clock-frequency = <400000>; 374 375 exp3: gpio@20 { 376 compatible = "ti,tca6408"; 377 reg = <0x20>; 378 gpio-controller; 379 #gpio-cells = <2>; 380 gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn", 381 "UB926_LOCK", "UB926_PWR_SW_CNTRL", 382 "UB926_TUNER_RESET", "UB926_GPIO_SPARE", ""; 383 }; 384}; 385 386&main_sdhci0 { 387 /* eMMC */ 388 status = "okay"; 389 non-removable; 390 bootph-all; 391 ti,driver-strength-ohm = <50>; 392 disable-wp; 393}; 394 395&main_sdhci1 { 396 /* SD card */ 397 status = "okay"; 398 pinctrl-0 = <&main_mmc1_pins_default>; 399 pinctrl-names = "default"; 400 vmmc-supply = <&vdd_mmc1>; 401 vqmmc-supply = <&vdd_sd_dv>; 402 bootph-all; 403 ti,driver-strength-ohm = <50>; 404 disable-wp; 405}; 406 407&serdes_ln_ctrl { 408 idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>, 409 <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>; 410}; 411 412&usb_serdes_mux { 413 idle-states = <1>; /* USB0 to SERDES lane 3 */ 414 bootph-all; 415}; 416 417&usbss0 { 418 pinctrl-names = "default"; 419 pinctrl-0 = <&main_usbss0_pins_default>; 420 bootph-all; 421 ti,vbus-divider; 422 ti,usb2-only; 423}; 424 425&usb0 { 426 dr_mode = "otg"; 427 maximum-speed = "high-speed"; 428 bootph-all; 429}; 430 431&tscadc0 { 432 adc { 433 ti,adc-channels = <0 1 2 3 4 5 6 7>; 434 }; 435}; 436 437&serdes_refclk { 438 clock-frequency = <100000000>; 439}; 440 441&serdes0 { 442 serdes0_pcie_link: phy@0 { 443 reg = <0>; 444 cdns,num-lanes = <2>; 445 #phy-cells = <0>; 446 cdns,phy-type = <PHY_TYPE_PCIE>; 447 resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; 448 }; 449 450 serdes0_qsgmii_link: phy@1 { 451 reg = <2>; 452 cdns,num-lanes = <1>; 453 #phy-cells = <0>; 454 cdns,phy-type = <PHY_TYPE_QSGMII>; 455 resets = <&serdes_wiz0 3>; 456 }; 457}; 458 459&pcie1_rc { 460 status = "okay"; 461 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; 462 phys = <&serdes0_pcie_link>; 463 phy-names = "pcie-phy"; 464 num-lanes = <2>; 465}; 466 467&mcu_mcan0 { 468 status = "okay"; 469 pinctrl-names = "default"; 470 pinctrl-0 = <&mcu_mcan0_pins_default>; 471 phys = <&transceiver1>; 472}; 473 474&mcu_mcan1 { 475 status = "okay"; 476 pinctrl-names = "default"; 477 pinctrl-0 = <&mcu_mcan1_pins_default>; 478 phys = <&transceiver2>; 479}; 480 481&main_mcan3 { 482 status = "okay"; 483 pinctrl-names = "default"; 484 pinctrl-0 = <&main_mcan3_pins_default>; 485 phys = <&transceiver3>; 486}; 487