1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * Design Files: https://www.ti.com/lit/zip/SPRR466 6 * TRM: https://www.ti.com/lit/zip/spruj52 7 */ 8 9/dts-v1/; 10 11#include <dt-bindings/net/ti-dp83867.h> 12#include <dt-bindings/gpio/gpio.h> 13#include "k3-j784s4.dtsi" 14 15/ { 16 compatible = "ti,am69-sk", "ti,j784s4"; 17 model = "Texas Instruments AM69 SK"; 18 19 chosen { 20 stdout-path = "serial2:115200n8"; 21 }; 22 23 aliases { 24 serial0 = &wkup_uart0; 25 serial1 = &mcu_uart0; 26 serial2 = &main_uart8; 27 mmc0 = &main_sdhci0; 28 mmc1 = &main_sdhci1; 29 i2c0 = &wkup_i2c0; 30 i2c3 = &main_i2c0; 31 ethernet0 = &mcu_cpsw_port1; 32 }; 33 34 memory@80000000 { 35 device_type = "memory"; 36 bootph-all; 37 /* 32G RAM */ 38 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 39 <0x00000008 0x80000000 0x00000007 0x80000000>; 40 }; 41 42 reserved_memory: reserved-memory { 43 #address-cells = <2>; 44 #size-cells = <2>; 45 ranges; 46 47 secure_ddr: optee@9e800000 { 48 reg = <0x00 0x9e800000 0x00 0x01800000>; 49 no-map; 50 }; 51 52 mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { 53 compatible = "shared-dma-pool"; 54 reg = <0x00 0xa0000000 0x00 0x100000>; 55 no-map; 56 }; 57 58 mcu_r5fss0_core0_memory_region: memory@a0100000 { 59 compatible = "shared-dma-pool"; 60 reg = <0x00 0xa0100000 0x00 0xf00000>; 61 no-map; 62 }; 63 }; 64 65 vusb_main: regulator-vusb-main5v0 { 66 /* USB MAIN INPUT 5V DC */ 67 compatible = "regulator-fixed"; 68 regulator-name = "vusb-main5v0"; 69 regulator-min-microvolt = <5000000>; 70 regulator-max-microvolt = <5000000>; 71 regulator-always-on; 72 regulator-boot-on; 73 }; 74 75 vsys_5v0: regulator-vsys5v0 { 76 /* Output of LM61460 */ 77 compatible = "regulator-fixed"; 78 regulator-name = "vsys_5v0"; 79 regulator-min-microvolt = <5000000>; 80 regulator-max-microvolt = <5000000>; 81 vin-supply = <&vusb_main>; 82 regulator-always-on; 83 regulator-boot-on; 84 }; 85 86 vsys_3v3: regulator-vsys3v3 { 87 /* Output of LM5143 */ 88 compatible = "regulator-fixed"; 89 regulator-name = "vsys_3v3"; 90 regulator-min-microvolt = <3300000>; 91 regulator-max-microvolt = <3300000>; 92 vin-supply = <&vusb_main>; 93 regulator-always-on; 94 regulator-boot-on; 95 }; 96 97 vdd_mmc1: regulator-sd { 98 /* Output of TPS22918 */ 99 compatible = "regulator-fixed"; 100 regulator-name = "vdd_mmc1"; 101 regulator-min-microvolt = <3300000>; 102 regulator-max-microvolt = <3300000>; 103 regulator-boot-on; 104 enable-active-high; 105 vin-supply = <&vsys_3v3>; 106 gpio = <&exp1 2 GPIO_ACTIVE_HIGH>; 107 }; 108 109 vdd_sd_dv: regulator-tlv71033 { 110 /* Output of TLV71033 */ 111 compatible = "regulator-gpio"; 112 regulator-name = "tlv71033"; 113 pinctrl-names = "default"; 114 pinctrl-0 = <&vdd_sd_dv_pins_default>; 115 regulator-min-microvolt = <1800000>; 116 regulator-max-microvolt = <3300000>; 117 regulator-boot-on; 118 vin-supply = <&vsys_5v0>; 119 gpios = <&main_gpio0 49 GPIO_ACTIVE_HIGH>; 120 states = <1800000 0x0>, 121 <3300000 0x1>; 122 }; 123 124 dp0_pwr_3v3: regulator-dp0-pwr { 125 compatible = "regulator-fixed"; 126 regulator-name = "dp0-pwr"; 127 regulator-min-microvolt = <3300000>; 128 regulator-max-microvolt = <3300000>; 129 pinctrl-names = "default"; 130 pinctrl-0 = <&dp_pwr_en_pins_default>; 131 gpio = <&main_gpio0 4 0>; /* DP0_3V3 _EN */ 132 enable-active-high; 133 }; 134 135 dp0: connector-dp0 { 136 compatible = "dp-connector"; 137 label = "DP0"; 138 type = "full-size"; 139 dp-pwr-supply = <&dp0_pwr_3v3>; 140 141 port { 142 dp0_connector_in: endpoint { 143 remote-endpoint = <&dp0_out>; 144 }; 145 }; 146 }; 147 148 connector-hdmi { 149 compatible = "hdmi-connector"; 150 label = "hdmi"; 151 type = "a"; 152 pinctrl-names = "default"; 153 pinctrl-0 = <&hdmi_hpd_pins_default>; 154 ddc-i2c-bus = <&mcu_i2c1>; 155 hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>; /* HDMI_HPD */ 156 157 port { 158 hdmi_connector_in: endpoint { 159 remote-endpoint = <&tfp410_out>; 160 }; 161 }; 162 }; 163 164 bridge-dvi { 165 compatible = "ti,tfp410"; 166 pinctrl-names = "default"; 167 pinctrl-0 = <&hdmi_pdn_pins_default>; 168 powerdown-gpios = <&wkup_gpio0 14 GPIO_ACTIVE_LOW>; /* HDMI_PDn */ 169 ti,deskew = <0>; 170 171 ports { 172 #address-cells = <1>; 173 #size-cells = <0>; 174 175 port@0 { 176 reg = <0>; 177 178 tfp410_in: endpoint { 179 remote-endpoint = <&dpi1_out0>; 180 pclk-sample = <1>; 181 }; 182 }; 183 184 port@1 { 185 reg = <1>; 186 187 tfp410_out: endpoint { 188 remote-endpoint = <&hdmi_connector_in>; 189 }; 190 }; 191 }; 192 }; 193 194 csi_mux: mux-controller { 195 compatible = "gpio-mux"; 196 #mux-state-cells = <1>; 197 mux-gpios = <&exp2 1 GPIO_ACTIVE_HIGH>; 198 idle-state = <0>; 199 }; 200 201 transceiver1: can-phy0 { 202 compatible = "ti,tcan1042"; 203 #phy-cells = <0>; 204 max-bitrate = <5000000>; 205 }; 206 207 transceiver2: can-phy1 { 208 compatible = "ti,tcan1042"; 209 #phy-cells = <0>; 210 max-bitrate = <5000000>; 211 }; 212 213 transceiver3: can-phy2 { 214 compatible = "ti,tcan1042"; 215 #phy-cells = <0>; 216 max-bitrate = <5000000>; 217 }; 218 219 transceiver4: can-phy3 { 220 compatible = "ti,tcan1042"; 221 #phy-cells = <0>; 222 max-bitrate = <5000000>; 223 }; 224 225}; 226 227&main_pmx0 { 228 bootph-all; 229 main_uart8_pins_default: main-uart8-default-pins { 230 bootph-all; 231 pinctrl-single,pins = < 232 J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ 233 J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ 234 >; 235 }; 236 237 main_i2c0_pins_default: main-i2c0-default-pins { 238 pinctrl-single,pins = < 239 J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */ 240 J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ 241 >; 242 }; 243 244 main_i2c1_pins_default: main-i2c1-default-pins { 245 pinctrl-single,pins = < 246 J784S4_IOPAD(0x0ac, PIN_INPUT_PULLUP, 13) /* (AE34) MCASP0_AXR15.I2C1_SCL */ 247 J784S4_IOPAD(0x0b0, PIN_INPUT_PULLUP, 13) /* (AL33) MCASP1_AXR3.I2C1_SDA */ 248 >; 249 }; 250 251 main_mmc1_pins_default: main-mmc1-default-pins { 252 bootph-all; 253 pinctrl-single,pins = < 254 J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ 255 J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ 256 J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */ 257 J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */ 258 J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */ 259 J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */ 260 J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */ 261 J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */ 262 >; 263 }; 264 265 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { 266 pinctrl-single,pins = < 267 J784S4_IOPAD(0x0C4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */ 268 >; 269 }; 270 271 rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { 272 pinctrl-single,pins = < 273 J784S4_IOPAD(0x0BC, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */ 274 J784S4_IOPAD(0x06C, PIN_INPUT, 7) /* (AJ37) MCASP4_AFSX.GPIO0_27 */ 275 J784S4_IOPAD(0x0B4, PIN_INPUT, 7) /* (AL34) MCASP1_AXR4.GPIO0_45 */ 276 J784S4_IOPAD(0x0C0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */ 277 J784S4_IOPAD(0x00C, PIN_INPUT, 7) /* (AF33) MCAN13_TX.GPIO0_3 */ 278 J784S4_IOPAD(0x0B8, PIN_INPUT, 7) /* (AC34) MCASP1_ACLKX.GPIO0_46 */ 279 J784S4_IOPAD(0x090, PIN_INPUT, 7) /* (AC35) MCASP0_AXR8.GPIO0_36 */ 280 J784S4_IOPAD(0x0A8, PIN_INPUT, 7) /* (AF34) MCASP0_AXR14.GPIO0_42 */ 281 J784S4_IOPAD(0x0A4, PIN_INPUT, 7) /* (AJ36) MCASP0_AXR13.GPIO0_41 */ 282 J784S4_IOPAD(0x034, PIN_INPUT, 7) /* (AJ34) PMIC_WAKE0n.GPIO0_13 */ 283 J784S4_IOPAD(0x0CC, PIN_INPUT, 7) /* (AM37) SPI0_CS0.GPIO0_51 */ 284 J784S4_IOPAD(0x08C, PIN_INPUT, 7) /* (AE35) MCASP0_AXR7.GPIO0_35 */ 285 J784S4_IOPAD(0x008, PIN_INPUT, 7) /* (AJ33) MCAN12_RX.GPIO0_2 */ 286 J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */ 287 >; 288 }; 289 290 dp0_pins_default: dp0-default-pins { 291 pinctrl-single,pins = < 292 J784S4_IOPAD(0x014, PIN_INPUT, 13) /* (AG33) MCAN14_TX.DP0_HPD */ 293 >; 294 }; 295 296 dp_pwr_en_pins_default: dp-pwr-en-default-pins { 297 pinctrl-single,pins = < 298 J784S4_IOPAD(0x010, PIN_INPUT, 7) /* (AH33) MCAN13_RX.GPIO0_4 */ 299 >; 300 }; 301 302 dss_vout0_pins_default: dss-vout0-default-pins { 303 pinctrl-single,pins = < 304 J784S4_IOPAD(0x074, PIN_OUTPUT, 2) /* (AC33) MCAN2_TX.VOUT0_DATA0 */ 305 J784S4_IOPAD(0x070, PIN_OUTPUT, 2) /* (AH38) MCAN1_RX.VOUT0_DATA1 */ 306 J784S4_IOPAD(0x07c, PIN_OUTPUT, 2) /* (AJ38) MCASP0_AXR3.VOUT0_DATA2 */ 307 J784S4_IOPAD(0x068, PIN_OUTPUT, 2) /* (AE38) MCAN0_RX.VOUT0_DATA3 */ 308 J784S4_IOPAD(0x064, PIN_OUTPUT, 2) /* (AF38) MCAN0_TX.VOUT0_DATA4 */ 309 J784S4_IOPAD(0x060, PIN_OUTPUT, 2) /* (AE36) MCASP2_AXR1.VOUT0_DATA5 */ 310 J784S4_IOPAD(0x05c, PIN_OUTPUT, 2) /* (AC36) MCASP2_AXR0.VOUT0_DATA6 */ 311 J784S4_IOPAD(0x058, PIN_OUTPUT, 2) /* (AE37) MCASP2_AFSX.VOUT0_DATA7 */ 312 J784S4_IOPAD(0x054, PIN_OUTPUT, 2) /* (AD37) MCASP2_ACLKX.VOUT0_DATA8 */ 313 J784S4_IOPAD(0x050, PIN_OUTPUT, 2) /* (AC37) MCASP1_AXR2.VOUT0_DATA9 */ 314 J784S4_IOPAD(0x04c, PIN_OUTPUT, 2) /* (AC32) MCASP1_AXR1.VOUT0_DATA10 */ 315 J784S4_IOPAD(0x048, PIN_OUTPUT, 2) /* (AK33) MCASP0_AXR2.VOUT0_DATA11 */ 316 J784S4_IOPAD(0x044, PIN_OUTPUT, 2) /* (AG37) MCASP0_AXR1.VOUT0_DATA12 */ 317 J784S4_IOPAD(0x040, PIN_OUTPUT, 2) /* (AF37) MCASP0_AXR0.VOUT0_DATA13 */ 318 J784S4_IOPAD(0x03c, PIN_OUTPUT, 2) /* (AK38) MCASP0_AFSX.VOUT0_DATA14 */ 319 J784S4_IOPAD(0x038, PIN_OUTPUT, 2) /* (AK35) MCASP0_ACLKX.VOUT0_DATA15 */ 320 J784S4_IOPAD(0x0c8, PIN_OUTPUT, 2) /* (AJ32) EXT_REFCLK1.VOUT0_DATA16 */ 321 J784S4_IOPAD(0x030, PIN_OUTPUT, 2) /* (AK37) GPIO0_12.VOUT0_DATA17 */ 322 J784S4_IOPAD(0x02c, PIN_OUTPUT, 2) /* (AL32) GPIO0_11.VOUT0_DATA18 */ 323 J784S4_IOPAD(0x028, PIN_OUTPUT, 2) /* (AE33) MCAN16_RX.VOUT0_DATA19 */ 324 J784S4_IOPAD(0x024, PIN_OUTPUT, 2) /* (AH34) MCAN16_TX.VOUT0_DATA20 */ 325 J784S4_IOPAD(0x020, PIN_OUTPUT, 2) /* (AJ35) MCAN15_RX.VOUT0_DATA21 */ 326 J784S4_IOPAD(0x01c, PIN_OUTPUT, 2) /* (AG34) MCAN15_TX.VOUT0_DATA22 */ 327 J784S4_IOPAD(0x018, PIN_OUTPUT, 2) /* (AK36) MCAN14_RX.VOUT0_DATA23 */ 328 J784S4_IOPAD(0x084, PIN_OUTPUT, 2) /* (AG38) MCASP0_AXR5.VOUT0_DE */ 329 J784S4_IOPAD(0x080, PIN_OUTPUT, 2) /* (AK34) MCASP0_AXR4.VOUT0_HSYNC */ 330 J784S4_IOPAD(0x078, PIN_OUTPUT, 2) /* (AH37) MCAN2_RX.VOUT0_PCLK */ 331 J784S4_IOPAD(0x088, PIN_OUTPUT, 2) /* (AF36) MCASP0_AXR6.VOUT0_VSYNC */ 332 >; 333 }; 334 335 hdmi_hpd_pins_default: hdmi-hpd-default-pins { 336 pinctrl-single,pins = < 337 J784S4_IOPAD(0x000, PIN_INPUT, 7) /* (AN35) EXTINTN.GPIO0_0 */ 338 >; 339 }; 340 341 main_mcan6_pins_default: main-mcan6-default-pins { 342 pinctrl-single,pins = < 343 J784S4_IOPAD(0x098, PIN_INPUT, 0) /* (AH36) MCAN6_RX */ 344 J784S4_IOPAD(0x094, PIN_OUTPUT, 0) /* (AG35) MCAN6_TX */ 345 >; 346 }; 347 348 main_mcan7_pins_default: main-mcan7-default-pins { 349 pinctrl-single,pins = < 350 J784S4_IOPAD(0x0A0, PIN_INPUT, 0) /* (AD34) MCAN7_RX */ 351 J784S4_IOPAD(0x09C, PIN_OUTPUT, 0) /* (AF35) MCAN7_TX */ 352 >; 353 }; 354 355 main_usbss0_pins_default: main-usbss0-default-pins { 356 pinctrl-single,pins = < 357 J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */ 358 >; 359 }; 360 361}; 362 363&wkup_pmx0 { 364 bootph-all; 365 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { 366 pinctrl-single,pins = < 367 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ 368 J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ 369 J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ 370 J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ 371 J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ 372 J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ 373 J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ 374 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ 375 J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ 376 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ 377 J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ 378 >; 379 }; 380}; 381 382&wkup_pmx2 { 383 bootph-all; 384 pmic_irq_pins_default: pmic-irq-default-pins { 385 pinctrl-single,pins = < 386 /* (AA37) MCU_ADC1_AIN4.WKUP_GPIO0_83 */ 387 J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 7) 388 >; 389 }; 390 391 wkup_uart0_pins_default: wkup-uart0-default-pins { 392 bootph-all; 393 pinctrl-single,pins = < 394 J784S4_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_UART0_CTSn */ 395 J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (L36) WKUP_UART0_RTSn */ 396 J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ 397 J784S4_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (K34) WKUP_UART0_TXD */ 398 >; 399 }; 400 401 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 402 bootph-all; 403 pinctrl-single,pins = < 404 J784S4_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ 405 J784S4_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ 406 >; 407 }; 408 409 mcu_uart0_pins_default: mcu-uart0-default-pins { 410 bootph-all; 411 pinctrl-single,pins = < 412 J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ 413 J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ 414 >; 415 }; 416 417 mcu_i2c0_pins_default: mcu-i2c0-default-pins { 418 pinctrl-single,pins = < 419 J784S4_WKUP_IOPAD(0x0a0, PIN_INPUT_PULLUP, 0) /* (M35) MCU_I2C0_SCL */ 420 J784S4_WKUP_IOPAD(0x0a4, PIN_INPUT_PULLUP, 0) /* (G34) MCU_I2C0_SDA */ 421 >; 422 }; 423 424 mcu_cpsw_pins_default: mcu-cpsw-default-pins { 425 pinctrl-single,pins = < 426 J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ 427 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ 428 J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ 429 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ 430 J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ 431 J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ 432 J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ 433 J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ 434 J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ 435 J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ 436 J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ 437 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ 438 >; 439 bootph-all; 440 }; 441 442 mcu_mdio_pins_default: mcu-mdio-default-pins { 443 pinctrl-single,pins = < 444 J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ 445 J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ 446 >; 447 bootph-all; 448 }; 449 450 mcu_rpi_hdr1_gpio0_pins_default: mcu-rpi-hdr1-gpio0-default-pins { 451 pinctrl-single,pins = < 452 J784S4_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (N34) WKUP_GPIO0_66 */ 453 J784S4_WKUP_IOPAD(0x05c, PIN_INPUT, 7) /* (J34) WKUP_GPIO0_1 */ 454 J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */ 455 J784S4_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (H38) WKUP_GPIO0_0 */ 456 J784S4_WKUP_IOPAD(0x0b8, PIN_INPUT, 7) /* (M37) WKUP_GPIO0_56 */ 457 J784S4_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (M36) WKUP_GPIO0_57 */ 458 J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (K37) WKUP_GPIO0_15 */ 459 J784S4_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (J36) WKUP_GPIO0_3 */ 460 J784S4_WKUP_IOPAD(0x11c, PIN_INPUT, 7) /* (M34) WKUP_GPIO0_67 */ 461 >; 462 }; 463 464 mcu_i2c1_pins_default: mcu-i2c1-default-pins { 465 pinctrl-single,pins = < 466 /* (L35) WKUP_GPIO0_8.MCU_I2C1_SCL */ 467 J784S4_WKUP_IOPAD(0x078, PIN_INPUT_PULLUP, 0) 468 /* (L34) WKUP_GPIO0_9.MCU_I2C1_SDA */ 469 J784S4_WKUP_IOPAD(0x07c, PIN_INPUT_PULLUP, 0) 470 >; 471 }; 472 473 hdmi_pdn_pins_default: hdmi-pdn-default-pins { 474 pinctrl-single,pins = < 475 J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 7) /* (H37) WKUP_GPIO0_14 */ 476 >; 477 }; 478 479 mcu_mcan0_pins_default: mcu-mcan0-default-pins { 480 pinctrl-single,pins = < 481 J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */ 482 J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */ 483 >; 484 }; 485 486 mcu_mcan1_pins_default: mcu-mcan1-default-pins { 487 pinctrl-single,pins = < 488 J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_RX */ 489 J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0)/* (H35) WKUP_GPIO0_4.MCU_MCAN1_TX */ 490 >; 491 }; 492 493}; 494 495&wkup_pmx3 { 496 mcu_rpi_hdr2_gpio0_pins_default: mcu-rpi-hdr2-gpio0-default-pins { 497 pinctrl-single,pins = < 498 J784S4_WKUP_IOPAD(0x0, PIN_INPUT, 7) /* (M33) WKUP_GPIO0_49 */ 499 >; 500 }; 501}; 502 503&cpsw_mac_syscon { 504 bootph-all; 505}; 506 507&phy_gmii_sel { 508 bootph-all; 509}; 510 511&wkup_uart0 { 512 /* Firmware usage */ 513 status = "reserved"; 514 pinctrl-names = "default"; 515 pinctrl-0 = <&wkup_uart0_pins_default>; 516}; 517 518&wkup_i2c0 { 519 bootph-all; 520 status = "okay"; 521 pinctrl-names = "default"; 522 pinctrl-0 = <&wkup_i2c0_pins_default>; 523 clock-frequency = <400000>; 524 525 eeprom@51 { 526 /* AT24C512C-MAHM-T */ 527 compatible = "atmel,24c512"; 528 reg = <0x51>; 529 }; 530 531 tps659413: pmic@48 { 532 compatible = "ti,tps6594-q1"; 533 reg = <0x48>; 534 system-power-controller; 535 pinctrl-names = "default"; 536 pinctrl-0 = <&pmic_irq_pins_default>; 537 interrupt-parent = <&wkup_gpio0>; 538 interrupts = <83 IRQ_TYPE_EDGE_FALLING>; 539 gpio-controller; 540 #gpio-cells = <2>; 541 ti,primary-pmic; 542 buck12-supply = <&vsys_3v3>; 543 buck3-supply = <&vsys_3v3>; 544 buck4-supply = <&vsys_3v3>; 545 buck5-supply = <&vsys_3v3>; 546 ldo1-supply = <&vsys_3v3>; 547 ldo2-supply = <&vsys_3v3>; 548 ldo3-supply = <&vsys_3v3>; 549 ldo4-supply = <&vsys_3v3>; 550 551 regulators { 552 bucka12: buck12 { 553 regulator-name = "vdd_ddr_1v1"; 554 regulator-min-microvolt = <1100000>; 555 regulator-max-microvolt = <1100000>; 556 regulator-boot-on; 557 regulator-always-on; 558 bootph-all; 559 }; 560 561 bucka3: buck3 { 562 regulator-name = "vdd_ram_0v85"; 563 regulator-min-microvolt = <850000>; 564 regulator-max-microvolt = <850000>; 565 regulator-boot-on; 566 regulator-always-on; 567 bootph-all; 568 }; 569 570 bucka4: buck4 { 571 regulator-name = "vdd_io_1v8"; 572 regulator-min-microvolt = <1800000>; 573 regulator-max-microvolt = <1800000>; 574 regulator-boot-on; 575 regulator-always-on; 576 bootph-all; 577 }; 578 579 bucka5: buck5 { 580 regulator-name = "vdd_mcu_0v85"; 581 regulator-min-microvolt = <850000>; 582 regulator-max-microvolt = <850000>; 583 regulator-boot-on; 584 regulator-always-on; 585 bootph-all; 586 }; 587 588 ldoa1: ldo1 { 589 regulator-name = "vdd_mcuio_1v8"; 590 regulator-min-microvolt = <1800000>; 591 regulator-max-microvolt = <1800000>; 592 regulator-boot-on; 593 regulator-always-on; 594 bootph-all; 595 }; 596 597 ldoa2: ldo2 { 598 regulator-name = "vdd_mcuio_3v3"; 599 regulator-min-microvolt = <3300000>; 600 regulator-max-microvolt = <3300000>; 601 regulator-boot-on; 602 regulator-always-on; 603 bootph-all; 604 }; 605 606 ldoa3: ldo3 { 607 regulator-name = "vds_dll_0v8"; 608 regulator-min-microvolt = <800000>; 609 regulator-max-microvolt = <800000>; 610 regulator-boot-on; 611 regulator-always-on; 612 bootph-all; 613 }; 614 615 ldoa4: ldo4 { 616 regulator-name = "vda_mcu_1v8"; 617 regulator-min-microvolt = <1800000>; 618 regulator-max-microvolt = <1800000>; 619 regulator-boot-on; 620 regulator-always-on; 621 bootph-all; 622 }; 623 }; 624 }; 625 626 tps62873a: regulator@40 { 627 compatible = "ti,tps62873"; 628 reg = <0x40>; 629 bootph-pre-ram; 630 regulator-name = "VDD_CPU_AVS"; 631 regulator-min-microvolt = <600000>; 632 regulator-max-microvolt = <900000>; 633 regulator-boot-on; 634 regulator-always-on; 635 }; 636 637 tps62873b: regulator@43 { 638 compatible = "ti,tps62873"; 639 reg = <0x43>; 640 regulator-name = "VDD_CORE_0V8"; 641 regulator-min-microvolt = <760000>; 642 regulator-max-microvolt = <840000>; 643 regulator-boot-on; 644 regulator-always-on; 645 }; 646}; 647 648&wkup_gpio0 { 649 status = "okay"; 650 pinctrl-names = "default"; 651 pinctrl-0 = <&mcu_rpi_hdr1_gpio0_pins_default>, <&mcu_rpi_hdr2_gpio0_pins_default>; 652}; 653 654&mcu_uart0 { 655 bootph-all; 656 status = "okay"; 657 pinctrl-names = "default"; 658 pinctrl-0 = <&mcu_uart0_pins_default>; 659}; 660 661&mcu_i2c0 { 662 status = "okay"; 663 pinctrl-names = "default"; 664 pinctrl-0 = <&mcu_i2c0_pins_default>; 665 clock-frequency = <400000>; 666}; 667 668&main_uart8 { 669 bootph-all; 670 status = "okay"; 671 pinctrl-names = "default"; 672 pinctrl-0 = <&main_uart8_pins_default>; 673}; 674 675&main_i2c0 { 676 status = "okay"; 677 pinctrl-names = "default"; 678 pinctrl-0 = <&main_i2c0_pins_default>; 679 clock-frequency = <400000>; 680 681 exp1: gpio@21 { 682 compatible = "ti,tca6416"; 683 reg = <0x21>; 684 gpio-controller; 685 #gpio-cells = <2>; 686 gpio-line-names = "BOARDID_EEPROM_WP", "CAN_STB", "GPIO_uSD_PWR_EN", 687 "IO_EXP_MCU_RGMII_RST#", "IO_EXP_PCIe0_4L_PERST#", 688 "IO_EXP_PCIe1_M.2_RTSz", "IO_EXP_PCIe3_M.2_RTSz", 689 "PM_INA_BUS_EN", "ENET1_EXP_PWRDN", "EXP1_ENET_RSTz", 690 "ENET1_I2CMUX_SEL", "PCIe0_CLKREQ#", "PCIe1_M.2_CLKREQ#", 691 "PCIe3_M2_CLKREQ#", "PCIe0_PRSNT2#_1", "PCIe0_PRSNT2#_2"; 692 }; 693}; 694 695&main_i2c1 { 696 pinctrl-names = "default"; 697 pinctrl-0 = <&main_i2c1_pins_default>; 698 clock-frequency = <400000>; 699 status = "okay"; 700 701 exp2: gpio@21 { 702 compatible = "ti,tca6408"; 703 reg = <0x21>; 704 gpio-controller; 705 #gpio-cells = <2>; 706 gpio-line-names = "CSI_VIO_SEL", "CSI_MUX_SEL_2", "CSI2_RSTz", 707 "IO_EXP_CAM0_GPIO1", "IO_EXP_CAM1_GPIO1"; 708 }; 709 710 i2c-mux@70 { 711 compatible = "nxp,pca9543"; 712 #address-cells = <1>; 713 #size-cells = <0>; 714 reg = <0x70>; 715 716 cam0_i2c: i2c@0 { 717 #address-cells = <1>; 718 #size-cells = <0>; 719 reg = <0>; 720 }; 721 722 cam1_i2c: i2c@1 { 723 #address-cells = <1>; 724 #size-cells = <0>; 725 reg = <1>; 726 }; 727 728 }; 729}; 730 731&main_sdhci0 { 732 bootph-all; 733 /* eMMC */ 734 status = "okay"; 735 non-removable; 736 ti,driver-strength-ohm = <50>; 737}; 738 739&main_sdhci1 { 740 bootph-all; 741 /* SD card */ 742 status = "okay"; 743 pinctrl-0 = <&main_mmc1_pins_default>; 744 pinctrl-names = "default"; 745 disable-wp; 746 vmmc-supply = <&vdd_mmc1>; 747 vqmmc-supply = <&vdd_sd_dv>; 748}; 749 750&main_gpio0 { 751 status = "okay"; 752 pinctrl-names = "default"; 753 pinctrl-0 = <&rpi_header_gpio0_pins_default>; 754}; 755 756&mcu_cpsw { 757 status = "okay"; 758 pinctrl-names = "default"; 759 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; 760}; 761 762&davinci_mdio { 763 mcu_phy0: ethernet-phy@0 { 764 reg = <0>; 765 bootph-all; 766 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 767 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 768 ti,min-output-impedance; 769 }; 770}; 771 772&mcu_cpsw_port1 { 773 status = "okay"; 774 phy-mode = "rgmii-rxid"; 775 phy-handle = <&mcu_phy0>; 776 bootph-all; 777}; 778 779&wkup_gpio_intr { 780 status = "okay"; 781}; 782 783&mcu_i2c1 { 784 status = "okay"; 785 pinctrl-names = "default"; 786 pinctrl-0 = <&mcu_i2c1_pins_default>; 787 clock-frequency = <100000>; 788}; 789 790&serdes_refclk { 791 status = "okay"; 792 clock-frequency = <100000000>; 793}; 794 795&dss { 796 status = "okay"; 797 pinctrl-names = "default"; 798 pinctrl-0 = <&dss_vout0_pins_default>; 799 assigned-clocks = <&k3_clks 218 2>, 800 <&k3_clks 218 5>; 801 assigned-clock-parents = <&k3_clks 218 3>, 802 <&k3_clks 218 7>; 803}; 804 805&serdes_wiz4 { 806 status = "okay"; 807}; 808 809&serdes4 { 810 status = "okay"; 811 serdes4_dp_link: phy@0 { 812 reg = <0>; 813 cdns,num-lanes = <4>; 814 #phy-cells = <0>; 815 cdns,phy-type = <PHY_TYPE_DP>; 816 resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>, 817 <&serdes_wiz4 3>, <&serdes_wiz4 4>; 818 }; 819}; 820 821&mhdp { 822 status = "okay"; 823 pinctrl-names = "default"; 824 pinctrl-0 = <&dp0_pins_default>; 825 phys = <&serdes4_dp_link>; 826 phy-names = "dpphy"; 827}; 828 829&dss_ports { 830 #address-cells = <1>; 831 #size-cells = <0>; 832 833 /* DP */ 834 port@0 { 835 reg = <0>; 836 837 dpi0_out: endpoint { 838 remote-endpoint = <&dp0_in>; 839 }; 840 }; 841 842 /* HDMI */ 843 port@1 { 844 reg = <1>; 845 846 dpi1_out0: endpoint { 847 remote-endpoint = <&tfp410_in>; 848 }; 849 }; 850}; 851 852&dp0_ports { 853 854 port@0 { 855 reg = <0>; 856 857 dp0_in: endpoint { 858 remote-endpoint = <&dpi0_out>; 859 }; 860 }; 861 862 port@4 { 863 reg = <4>; 864 865 dp0_out: endpoint { 866 remote-endpoint = <&dp0_connector_in>; 867 }; 868 }; 869}; 870 871&mcu_mcan0 { 872 status = "okay"; 873 pinctrl-names = "default"; 874 pinctrl-0 = <&mcu_mcan0_pins_default>; 875 phys = <&transceiver1>; 876}; 877 878&mcu_mcan1 { 879 status = "okay"; 880 pinctrl-names = "default"; 881 pinctrl-0 = <&mcu_mcan1_pins_default>; 882 phys = <&transceiver2>; 883}; 884 885&main_mcan6 { 886 status = "okay"; 887 pinctrl-names = "default"; 888 pinctrl-0 = <&main_mcan6_pins_default>; 889 phys = <&transceiver3>; 890}; 891 892&main_mcan7 { 893 status = "okay"; 894 pinctrl-names = "default"; 895 pinctrl-0 = <&main_mcan7_pins_default>; 896 phys = <&transceiver4>; 897}; 898 899&ospi0 { 900 status = "okay"; 901 pinctrl-names = "default"; 902 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 903 904 flash@0 { 905 compatible = "jedec,spi-nor"; 906 reg = <0x0>; 907 spi-tx-bus-width = <8>; 908 spi-rx-bus-width = <8>; 909 spi-max-frequency = <25000000>; 910 cdns,tshsl-ns = <60>; 911 cdns,tsd2d-ns = <60>; 912 cdns,tchsh-ns = <60>; 913 cdns,tslch-ns = <60>; 914 cdns,read-delay = <4>; 915 916 partitions { 917 bootph-all; 918 compatible = "fixed-partitions"; 919 #address-cells = <1>; 920 #size-cells = <1>; 921 922 partition@0 { 923 label = "ospi.tiboot3"; 924 reg = <0x0 0x100000>; 925 }; 926 927 partition@100000 { 928 label = "ospi.tispl"; 929 reg = <0x100000 0x200000>; 930 }; 931 932 partition@300000 { 933 label = "ospi.u-boot"; 934 reg = <0x300000 0x400000>; 935 }; 936 937 partition@700000 { 938 label = "ospi.env"; 939 reg = <0x700000 0x40000>; 940 }; 941 942 partition@740000 { 943 label = "ospi.env.backup"; 944 reg = <0x740000 0x40000>; 945 }; 946 947 partition@800000 { 948 label = "ospi.rootfs"; 949 reg = <0x800000 0x37c0000>; 950 }; 951 952 partition@3fc0000 { 953 bootph-pre-ram; 954 label = "ospi.phypattern"; 955 reg = <0x3fc0000 0x40000>; 956 }; 957 }; 958 }; 959}; 960 961&serdes_ln_ctrl { 962 idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>, 963 <J784S4_SERDES0_LANE2_PCIE3_LANE0>, <J784S4_SERDES0_LANE3_USB>, 964 <J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>, 965 <J784S4_SERDES1_LANE2_PCIE0_LANE2>, <J784S4_SERDES1_LANE3_PCIE0_LANE3>, 966 <J784S4_SERDES2_LANE0_IP2_UNUSED>, <J784S4_SERDES2_LANE1_IP2_UNUSED>, 967 <J784S4_SERDES2_LANE2_QSGMII_LANE1>, <J784S4_SERDES2_LANE3_QSGMII_LANE2>, 968 <J784S4_SERDES4_LANE0_EDP_LANE0>, <J784S4_SERDES4_LANE1_EDP_LANE1>, 969 <J784S4_SERDES4_LANE2_EDP_LANE2>, <J784S4_SERDES4_LANE3_EDP_LANE3>; 970}; 971 972&serdes_wiz0 { 973 status = "okay"; 974}; 975 976&serdes0 { 977 status = "okay"; 978 979 serdes0_pcie1_link: phy@0 { 980 reg = <0>; 981 cdns,num-lanes = <2>; 982 #phy-cells = <0>; 983 cdns,phy-type = <PHY_TYPE_PCIE>; 984 resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; 985 }; 986 987 serdes0_pcie3_link: phy@2 { 988 reg = <2>; 989 cdns,num-lanes = <1>; 990 #phy-cells = <0>; 991 cdns,phy-type = <PHY_TYPE_PCIE>; 992 resets = <&serdes_wiz0 3>; 993 }; 994 995 serdes0_usb_link: phy@3 { 996 reg = <3>; 997 cdns,num-lanes = <1>; 998 #phy-cells = <0>; 999 cdns,phy-type = <PHY_TYPE_USB3>; 1000 resets = <&serdes_wiz0 4>; 1001 }; 1002}; 1003 1004&serdes_wiz1 { 1005 status = "okay"; 1006}; 1007 1008&serdes1 { 1009 status = "okay"; 1010 1011 serdes1_pcie_link: phy@0 { 1012 reg = <0>; 1013 cdns,num-lanes = <4>; 1014 #phy-cells = <0>; 1015 cdns,phy-type = <PHY_TYPE_PCIE>; 1016 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>, <&serdes_wiz1 3>, <&serdes_wiz1 4>; 1017 }; 1018}; 1019 1020&pcie0_rc { 1021 status = "okay"; 1022 reset-gpios = <&exp1 4 GPIO_ACTIVE_HIGH>; 1023 phys = <&serdes1_pcie_link>; 1024 phy-names = "pcie-phy"; 1025}; 1026 1027&pcie1_rc { 1028 status = "okay"; 1029 reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; 1030 phys = <&serdes0_pcie1_link>; 1031 phy-names = "pcie-phy"; 1032 num-lanes = <2>; 1033}; 1034 1035&pcie3_rc { 1036 status = "okay"; 1037 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; 1038 phys = <&serdes0_pcie3_link>; 1039 phy-names = "pcie-phy"; 1040 num-lanes = <1>; 1041}; 1042 1043&usb_serdes_mux { 1044 idle-states = <0>; /* USB0 to SERDES0 */ 1045}; 1046 1047&usbss0 { 1048 status = "okay"; 1049 pinctrl-0 = <&main_usbss0_pins_default>; 1050 pinctrl-names = "default"; 1051 ti,vbus-divider; 1052}; 1053 1054&usb0 { 1055 status = "okay"; 1056 dr_mode = "otg"; 1057 maximum-speed = "super-speed"; 1058 phys = <&serdes0_usb_link>; 1059 phy-names = "cdns3,usb3-phy"; 1060}; 1061 1062#include "k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi" 1063#include "k3-j784s4-ti-ipc-firmware.dtsi" 1064