1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include "k3-j721s2.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10 11/ { 12 memory@80000000 { 13 device_type = "memory"; 14 bootph-all; 15 /* 16 GB RAM */ 16 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 17 <0x00000008 0x80000000 0x00000003 0x80000000>; 18 }; 19 20 reserved_memory: reserved-memory { 21 #address-cells = <2>; 22 #size-cells = <2>; 23 ranges; 24 25 secure_ddr: optee@9e800000 { 26 reg = <0x00 0x9e800000 0x00 0x01800000>; 27 no-map; 28 }; 29 30 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 31 compatible = "shared-dma-pool"; 32 reg = <0x00 0xa0000000 0x00 0x100000>; 33 no-map; 34 }; 35 36 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 37 compatible = "shared-dma-pool"; 38 reg = <0x00 0xa0100000 0x00 0xf00000>; 39 no-map; 40 }; 41 42 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 43 compatible = "shared-dma-pool"; 44 reg = <0x00 0xa1000000 0x00 0x100000>; 45 no-map; 46 }; 47 48 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 49 compatible = "shared-dma-pool"; 50 reg = <0x00 0xa1100000 0x00 0xf00000>; 51 no-map; 52 }; 53 54 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 55 compatible = "shared-dma-pool"; 56 reg = <0x00 0xa2000000 0x00 0x100000>; 57 no-map; 58 }; 59 60 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 61 compatible = "shared-dma-pool"; 62 reg = <0x00 0xa2100000 0x00 0xf00000>; 63 no-map; 64 }; 65 66 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 67 compatible = "shared-dma-pool"; 68 reg = <0x00 0xa3000000 0x00 0x100000>; 69 no-map; 70 }; 71 72 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 73 compatible = "shared-dma-pool"; 74 reg = <0x00 0xa3100000 0x00 0xf00000>; 75 no-map; 76 }; 77 78 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { 79 compatible = "shared-dma-pool"; 80 reg = <0x00 0xa4000000 0x00 0x100000>; 81 no-map; 82 }; 83 84 main_r5fss1_core0_memory_region: r5f-memory@a4100000 { 85 compatible = "shared-dma-pool"; 86 reg = <0x00 0xa4100000 0x00 0xf00000>; 87 no-map; 88 }; 89 90 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { 91 compatible = "shared-dma-pool"; 92 reg = <0x00 0xa5000000 0x00 0x100000>; 93 no-map; 94 }; 95 96 main_r5fss1_core1_memory_region: r5f-memory@a5100000 { 97 compatible = "shared-dma-pool"; 98 reg = <0x00 0xa5100000 0x00 0xf00000>; 99 no-map; 100 }; 101 102 c71_0_dma_memory_region: c71-dma-memory@a6000000 { 103 compatible = "shared-dma-pool"; 104 reg = <0x00 0xa6000000 0x00 0x100000>; 105 no-map; 106 }; 107 108 c71_0_memory_region: c71-memory@a6100000 { 109 compatible = "shared-dma-pool"; 110 reg = <0x00 0xa6100000 0x00 0xf00000>; 111 no-map; 112 }; 113 114 c71_1_dma_memory_region: c71-dma-memory@a7000000 { 115 compatible = "shared-dma-pool"; 116 reg = <0x00 0xa7000000 0x00 0x100000>; 117 no-map; 118 }; 119 120 c71_1_memory_region: c71-memory@a7100000 { 121 compatible = "shared-dma-pool"; 122 reg = <0x00 0xa7100000 0x00 0xf00000>; 123 no-map; 124 }; 125 126 rtos_ipc_memory_region: ipc-memories@a8000000 { 127 reg = <0x00 0xa8000000 0x00 0x01c00000>; 128 alignment = <0x1000>; 129 no-map; 130 }; 131 }; 132}; 133 134&wkup_pmx0 { 135 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins { 136 bootph-all; 137 pinctrl-single,pins = < 138 J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ 139 J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ 140 J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ 141 J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ 142 J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ 143 J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */ 144 J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */ 145 J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */ 146 J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */ 147 J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */ 148 J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ 149 >; 150 }; 151}; 152 153&wkup_pmx2 { 154 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 155 pinctrl-single,pins = < 156 J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ 157 J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ 158 >; 159 bootph-all; 160 }; 161}; 162 163&wkup_i2c0 { 164 status = "okay"; 165 pinctrl-names = "default"; 166 pinctrl-0 = <&wkup_i2c0_pins_default>; 167 clock-frequency = <400000>; 168 169 eeprom@51 { 170 /* AT24C512C-MAHM-T */ 171 compatible = "atmel,24c512"; 172 reg = <0x51>; 173 bootph-all; 174 }; 175}; 176 177&ospi0 { 178 status = "okay"; 179 pinctrl-names = "default"; 180 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 181 182 flash@0 { 183 compatible = "jedec,spi-nor"; 184 reg = <0x0>; 185 spi-tx-bus-width = <8>; 186 spi-rx-bus-width = <8>; 187 spi-max-frequency = <25000000>; 188 cdns,tshsl-ns = <60>; 189 cdns,tsd2d-ns = <60>; 190 cdns,tchsh-ns = <60>; 191 cdns,tslch-ns = <60>; 192 cdns,read-delay = <4>; 193 194 partitions { 195 compatible = "fixed-partitions"; 196 #address-cells = <1>; 197 #size-cells = <1>; 198 199 partition@0 { 200 label = "ospi.tiboot3"; 201 reg = <0x0 0x80000>; 202 }; 203 204 partition@80000 { 205 label = "ospi.tispl"; 206 reg = <0x80000 0x200000>; 207 }; 208 209 partition@280000 { 210 label = "ospi.u-boot"; 211 reg = <0x280000 0x400000>; 212 }; 213 214 partition@680000 { 215 label = "ospi.env"; 216 reg = <0x680000 0x40000>; 217 }; 218 219 partition@6c0000 { 220 label = "ospi.env.backup"; 221 reg = <0x6c0000 0x40000>; 222 }; 223 224 partition@800000 { 225 label = "ospi.rootfs"; 226 reg = <0x800000 0x37c0000>; 227 }; 228 229 partition@3fc0000 { 230 label = "ospi.phypattern"; 231 reg = <0x3fc0000 0x40000>; 232 bootph-all; 233 }; 234 }; 235 }; 236}; 237 238&mailbox0_cluster0 { 239 status = "okay"; 240 interrupts = <436>; 241 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 242 ti,mbox-rx = <0 0 0>; 243 ti,mbox-tx = <1 0 0>; 244 }; 245 246 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 247 ti,mbox-rx = <2 0 0>; 248 ti,mbox-tx = <3 0 0>; 249 }; 250}; 251 252&mailbox0_cluster1 { 253 status = "okay"; 254 interrupts = <432>; 255 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 256 ti,mbox-rx = <0 0 0>; 257 ti,mbox-tx = <1 0 0>; 258 }; 259 260 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 261 ti,mbox-rx = <2 0 0>; 262 ti,mbox-tx = <3 0 0>; 263 }; 264}; 265 266&mailbox0_cluster2 { 267 status = "okay"; 268 interrupts = <428>; 269 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 270 ti,mbox-rx = <0 0 0>; 271 ti,mbox-tx = <1 0 0>; 272 }; 273 274 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 275 ti,mbox-rx = <2 0 0>; 276 ti,mbox-tx = <3 0 0>; 277 }; 278}; 279 280&mailbox0_cluster4 { 281 status = "okay"; 282 interrupts = <420>; 283 mbox_c71_0: mbox-c71-0 { 284 ti,mbox-rx = <0 0 0>; 285 ti,mbox-tx = <1 0 0>; 286 }; 287 288 mbox_c71_1: mbox-c71-1 { 289 ti,mbox-rx = <2 0 0>; 290 ti,mbox-tx = <3 0 0>; 291 }; 292}; 293 294&mcu_r5fss0_core0 { 295 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 296 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 297 <&mcu_r5fss0_core0_memory_region>; 298}; 299 300&mcu_r5fss0_core1 { 301 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 302 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 303 <&mcu_r5fss0_core1_memory_region>; 304}; 305 306&main_r5fss0 { 307 ti,cluster-mode = <0>; 308}; 309 310&main_r5fss1 { 311 ti,cluster-mode = <0>; 312}; 313 314/* Timers are used by Remoteproc firmware */ 315&main_timer0 { 316 status = "reserved"; 317}; 318 319&main_timer1 { 320 status = "reserved"; 321}; 322 323&main_timer2 { 324 status = "reserved"; 325}; 326 327&main_timer3 { 328 status = "reserved"; 329}; 330 331&main_timer4 { 332 status = "reserved"; 333}; 334 335&main_timer5 { 336 status = "reserved"; 337}; 338 339&main_r5fss0_core0 { 340 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 341 memory-region = <&main_r5fss0_core0_dma_memory_region>, 342 <&main_r5fss0_core0_memory_region>; 343}; 344 345&main_r5fss0_core1 { 346 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 347 memory-region = <&main_r5fss0_core1_dma_memory_region>, 348 <&main_r5fss0_core1_memory_region>; 349}; 350 351&main_r5fss1_core0 { 352 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; 353 memory-region = <&main_r5fss1_core0_dma_memory_region>, 354 <&main_r5fss1_core0_memory_region>; 355}; 356 357&main_r5fss1_core1 { 358 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; 359 memory-region = <&main_r5fss1_core1_dma_memory_region>, 360 <&main_r5fss1_core1_memory_region>; 361}; 362 363&c71_0 { 364 status = "okay"; 365 mboxes = <&mailbox0_cluster4 &mbox_c71_0>; 366 memory-region = <&c71_0_dma_memory_region>, 367 <&c71_0_memory_region>; 368}; 369 370&c71_1 { 371 status = "okay"; 372 mboxes = <&mailbox0_cluster4 &mbox_c71_1>; 373 memory-region = <&c71_1_dma_memory_region>, 374 <&c71_1_memory_region>; 375}; 376