1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/** 3 * DT overlay for IDK application board on AM654 EVM 4 * 5 * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8/dts-v1/; 9/plugin/; 10 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/net/ti-dp83867.h> 13#include "k3-pinctrl.h" 14 15&{/} { 16 aliases { 17 ethernet3 = "/icssg0-eth/ethernet-ports/port@0"; 18 ethernet4 = "/icssg0-eth/ethernet-ports/port@1"; 19 ethernet5 = "/icssg1-eth/ethernet-ports/port@0"; 20 ethernet6 = "/icssg1-eth/ethernet-ports/port@1"; 21 }; 22 23 /* Ethernet node on PRU-ICSSG0 */ 24 icssg0_eth: icssg0-eth { 25 compatible = "ti,am654-icssg-prueth"; 26 pinctrl-names = "default"; 27 pinctrl-0 = <&icssg0_rgmii_pins_default>; 28 sram = <&msmc_ram>; 29 ti,prus = <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, <&pru0_1>, <&rtu0_1>, <&tx_pru0_1>; 30 firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", 31 "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", 32 "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", 33 "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", 34 "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", 35 "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; 36 37 ti,pruss-gp-mux-sel = <2>, /* MII mode */ 38 <2>, 39 <2>, 40 <2>, /* MII mode */ 41 <2>, 42 <2>; 43 44 ti,mii-g-rt = <&icssg0_mii_g_rt>; 45 ti,mii-rt = <&icssg0_mii_rt>; 46 ti,pa-stats = <&icssg0_pa_stats>; 47 ti,iep = <&icssg0_iep0>, <&icssg0_iep1>; 48 49 interrupt-parent = <&icssg0_intc>; 50 interrupts = <24 0 2>, <25 1 3>; 51 interrupt-names = "tx_ts0", "tx_ts1"; 52 53 dmas = <&main_udmap 0xc100>, /* egress slice 0 */ 54 <&main_udmap 0xc101>, /* egress slice 0 */ 55 <&main_udmap 0xc102>, /* egress slice 0 */ 56 <&main_udmap 0xc103>, /* egress slice 0 */ 57 <&main_udmap 0xc104>, /* egress slice 1 */ 58 <&main_udmap 0xc105>, /* egress slice 1 */ 59 <&main_udmap 0xc106>, /* egress slice 1 */ 60 <&main_udmap 0xc107>, /* egress slice 1 */ 61 62 <&main_udmap 0x4100>, /* ingress slice 0 */ 63 <&main_udmap 0x4101>; /* ingress slice 1 */ 64 dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", 65 "tx1-0", "tx1-1", "tx1-2", "tx1-3", 66 "rx0", "rx1"; 67 68 ethernet-ports { 69 #address-cells = <1>; 70 #size-cells = <0>; 71 icssg0_emac0: port@0 { 72 reg = <0>; 73 phy-handle = <&icssg0_phy0>; 74 phy-mode = "rgmii-id"; 75 ti,syscon-rgmii-delay = <&scm_conf 0x4100>; 76 /* Filled in by bootloader */ 77 local-mac-address = [00 00 00 00 00 00]; 78 }; 79 icssg0_emac1: port@1 { 80 reg = <1>; 81 phy-handle = <&icssg0_phy1>; 82 phy-mode = "rgmii-id"; 83 ti,syscon-rgmii-delay = <&scm_conf 0x4104>; 84 /* Filled in by bootloader */ 85 local-mac-address = [00 00 00 00 00 00]; 86 }; 87 }; 88 }; 89 90 /* Ethernet node on PRU-ICSSG1 */ 91 icssg1_eth: icssg1-eth { 92 compatible = "ti,am654-icssg-prueth"; 93 pinctrl-names = "default"; 94 pinctrl-0 = <&icssg1_rgmii_pins_default>; 95 sram = <&msmc_ram>; 96 ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>; 97 firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", 98 "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", 99 "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", 100 "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", 101 "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", 102 "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; 103 104 ti,pruss-gp-mux-sel = <2>, /* MII mode */ 105 <2>, 106 <2>, 107 <2>, /* MII mode */ 108 <2>, 109 <2>; 110 111 ti,mii-g-rt = <&icssg1_mii_g_rt>; 112 ti,mii-rt = <&icssg1_mii_rt>; 113 ti,pa-stats = <&icssg1_pa_stats>; 114 ti,iep = <&icssg1_iep0>, <&icssg1_iep1>; 115 116 interrupt-parent = <&icssg1_intc>; 117 interrupts = <24 0 2>, <25 1 3>; 118 interrupt-names = "tx_ts0", "tx_ts1"; 119 120 dmas = <&main_udmap 0xc200>, /* egress slice 0 */ 121 <&main_udmap 0xc201>, /* egress slice 0 */ 122 <&main_udmap 0xc202>, /* egress slice 0 */ 123 <&main_udmap 0xc203>, /* egress slice 0 */ 124 <&main_udmap 0xc204>, /* egress slice 1 */ 125 <&main_udmap 0xc205>, /* egress slice 1 */ 126 <&main_udmap 0xc206>, /* egress slice 1 */ 127 <&main_udmap 0xc207>, /* egress slice 1 */ 128 129 <&main_udmap 0x4200>, /* ingress slice 0 */ 130 <&main_udmap 0x4201>; /* ingress slice 1 */ 131 dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", 132 "tx1-0", "tx1-1", "tx1-2", "tx1-3", 133 "rx0", "rx1"; 134 135 ethernet-ports { 136 #address-cells = <1>; 137 #size-cells = <0>; 138 icssg1_emac0: port@0 { 139 reg = <0>; 140 phy-handle = <&icssg1_phy0>; 141 phy-mode = "rgmii-id"; 142 ti,syscon-rgmii-delay = <&scm_conf 0x4110>; 143 /* Filled in by bootloader */ 144 local-mac-address = [00 00 00 00 00 00]; 145 }; 146 icssg1_emac1: port@1 { 147 reg = <1>; 148 phy-handle = <&icssg1_phy1>; 149 phy-mode = "rgmii-id"; 150 ti,syscon-rgmii-delay = <&scm_conf 0x4114>; 151 /* Filled in by bootloader */ 152 local-mac-address = [00 00 00 00 00 00]; 153 }; 154 }; 155 }; 156 157 transceiver1: can-phy0 { 158 compatible = "ti,tcan1042"; 159 #phy-cells = <0>; 160 max-bitrate = <5000000>; 161 pinctrl-names = "default"; 162 pinctrl-0 = <&mcan0_gpio_pins_default>; 163 standby-gpios = <&main_gpio1 47 GPIO_ACTIVE_LOW>; 164 }; 165 166 transceiver2: can-phy1 { 167 compatible = "ti,tcan1042"; 168 #phy-cells = <0>; 169 max-bitrate = <5000000>; 170 pinctrl-names = "default"; 171 pinctrl-0 = <&mcan1_gpio_pins_default>; 172 standby-gpios = <&main_gpio1 67 GPIO_ACTIVE_LOW>; 173 }; 174}; 175 176&main_pmx0 { 177 178 icssg0_mdio_pins_default: icssg0-mdio-default-pins { 179 pinctrl-single,pins = < 180 AM65X_IOPAD(0x0294, PIN_INPUT, 0) /* (AE26) PRG0_MDIO0_MDIO */ 181 AM65X_IOPAD(0x0298, PIN_OUTPUT, 0) /* (AE28) PRG0_MDIO0_MDC */ 182 >; 183 }; 184 185 icssg0_rgmii_pins_default: icssg0-rgmii-default-pins { 186 pinctrl-single,pins = < 187 AM65X_IOPAD(0x0244, PIN_INPUT, 2) /* (AB28) PRG0_PRU1_GPO0.PRG0_RGMII2_RD0 */ 188 AM65X_IOPAD(0x0248, PIN_INPUT, 2) /* (AC28) PRG0_PRU1_GPO1.PRG0_RGMII2_RD1 */ 189 AM65X_IOPAD(0x024c, PIN_INPUT, 2) /* (AC27) PRG0_PRU1_GPO2.PRG0_RGMII2_RD2 */ 190 AM65X_IOPAD(0x0250, PIN_INPUT, 2) /* (AB26) PRG0_PRU1_GPO3.PRG0_RGMII2_RD3 */ 191 AM65X_IOPAD(0x0274, PIN_OUTPUT, 2) /* (AC25) PRG0_PRU1_GPO12.PRG0_RGMII2_TD0 */ 192 AM65X_IOPAD(0x0278, PIN_OUTPUT, 2) /* (AD25) PRG0_PRU1_GPO13.PRG0_RGMII2_TD1 */ 193 AM65X_IOPAD(0x027c, PIN_OUTPUT, 2) /* (AD24) PRG0_PRU1_GPO14.PRG0_RGMII2_TD2 */ 194 AM65X_IOPAD(0x0280, PIN_OUTPUT, 2) /* (AE27) PRG0_PRU1_GPO15.PRG0_RGMII2_TD3 */ 195 AM65X_IOPAD(0x0284, PIN_INPUT, 2) /* (AC24) PRG0_PRU1_GPO16.PRG0_RGMII2_TXC */ 196 AM65X_IOPAD(0x0270, PIN_OUTPUT, 2) /* (AB24) PRG0_PRU1_GPO11.PRG0_RGMII2_TX_CTL */ 197 AM65X_IOPAD(0x025c, PIN_INPUT, 2) /* (AB27) PRG0_PRU1_GPO6.PRG0_RGMII2_RXC */ 198 AM65X_IOPAD(0x0254, PIN_INPUT, 2) /* (AA25) PRG0_PRU1_GPO4.PRG0_RGMII2_RX_CTL */ 199 200 AM65X_IOPAD(0x01f4, PIN_INPUT, 2) /* (V24) PRG0_PRU0_GPO0.PRG0_RGMII1_RD0 */ 201 AM65X_IOPAD(0x01f8, PIN_INPUT, 2) /* (W25) PRG0_PRU0_GPO1.PRG0_RGMII1_RD1 */ 202 AM65X_IOPAD(0x01fc, PIN_INPUT, 2) /* (W24) PRG0_PRU0_GPO2.PRG0_RGMII1_RD2 */ 203 AM65X_IOPAD(0x0200, PIN_INPUT, 2) /* (AA27) PRG0_PRU0_GPO3.PRG0_RGMII1_RD3 */ 204 AM65X_IOPAD(0x0224, PIN_OUTPUT, 2) /* (AD27) PRG0_PRU0_GPO12.PRG0_RGMII1_TD0 */ 205 AM65X_IOPAD(0x0228, PIN_OUTPUT, 2) /* (AC26) PRG0_PRU0_GPO13.PRG0_RGMII1_TD1 */ 206 AM65X_IOPAD(0x022c, PIN_OUTPUT, 2) /* (AD26) PRG0_PRU0_GPO14.PRG0_RGMII1_TD2 */ 207 AM65X_IOPAD(0x0230, PIN_OUTPUT, 2) /* (AA24) PRG0_PRU0_GPO15.PRG0_RGMII1_TD3 */ 208 AM65X_IOPAD(0x0234, PIN_INPUT, 2) /* (AD28) PRG0_PRU0_GPO16.PRG0_RGMII1_TXC */ 209 AM65X_IOPAD(0x0220, PIN_OUTPUT, 2) /* (AB25) PRG0_PRU0_GPO11.PRG0_RGMII1_TX_CTL */ 210 AM65X_IOPAD(0x020c, PIN_INPUT, 2) /* (Y25) PRG0_PRU0_GPO6.PRG0_RGMII1_RXC */ 211 AM65X_IOPAD(0x0204, PIN_INPUT, 2) /* (Y24) PRG0_PRU0_GPO4.PRG0_RGMII1_RX_CTL */ 212 >; 213 }; 214 215 icssg0_iep0_pins_default: icssg0-iep0-default-pins { 216 pinctrl-single,pins = < 217 AM65X_IOPAD(0x0240, PIN_INPUT, 2) /* (U24) PRG0_PRU0_GPO19.PRG0_IEP0_EDC_SYNC_OUT0 */ 218 >; 219 }; 220 221 icssg1_mdio_pins_default: icssg1-mdio-default-pins { 222 pinctrl-single,pins = < 223 AM65X_IOPAD(0x0180, PIN_INPUT, 0) /* (AD18) PRG1_MDIO0_MDIO */ 224 AM65X_IOPAD(0x0184, PIN_OUTPUT, 0) /* (AH18) PRG1_MDIO0_MDC */ 225 >; 226 }; 227 228 icssg1_rgmii_pins_default: icssg1-rgmii-default-pins { 229 pinctrl-single,pins = < 230 AM65X_IOPAD(0x0130, PIN_INPUT, 2) /* (AH24) PRG1_PRU1_GPO0.PRG1_RGMII2_RD0 */ 231 AM65X_IOPAD(0x0134, PIN_INPUT, 2) /* (AH23) PRG1_PRU1_GPO1.PRG1_RGMII2_RD1 */ 232 AM65X_IOPAD(0x0138, PIN_INPUT, 2) /* (AG21) PRG1_PRU1_GPO2.PRG1_RGMII2_RD2 */ 233 AM65X_IOPAD(0x013c, PIN_INPUT, 2) /* (AH22) PRG1_PRU1_GPO3.PRG1_RGMII2_RD3 */ 234 AM65X_IOPAD(0x0160, PIN_OUTPUT, 2) /* (AE20) PRG1_PRU1_GPO12.PRG1_RGMII2_TD0 */ 235 AM65X_IOPAD(0x0164, PIN_OUTPUT, 2) /* (AF19) PRG1_PRU1_GPO13.PRG1_RGMII2_TD1 */ 236 AM65X_IOPAD(0x0168, PIN_OUTPUT, 2) /* (AH19) PRG1_PRU1_GPO14.PRG1_RGMII2_TD2 */ 237 AM65X_IOPAD(0x016c, PIN_OUTPUT, 2) /* (AG19) PRG1_PRU1_GPO15.PRG1_RGMII2_TD3 */ 238 AM65X_IOPAD(0x0170, PIN_INPUT, 2) /* (AE19) PRG1_PRU1_GPO16.PRG1_RGMII2_TXC */ 239 AM65X_IOPAD(0x015c, PIN_OUTPUT, 2) /* (AC20) PRG1_PRU1_GPO11.PRG1_RGMII2_TX_CTL */ 240 AM65X_IOPAD(0x0148, PIN_INPUT, 2) /* (AG22) PRG1_PRU1_GPO6.PRG1_RGMII2_RXC */ 241 AM65X_IOPAD(0x0140, PIN_INPUT, 2) /* (AE21) PRG1_PRU1_GPO4.PRG1_RGMII2_RX_CTL */ 242 243 AM65X_IOPAD(0x00e0, PIN_INPUT, 2) /* (AE22) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */ 244 AM65X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AG24) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */ 245 AM65X_IOPAD(0x00e8, PIN_INPUT, 2) /* (AF23) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */ 246 AM65X_IOPAD(0x00ec, PIN_INPUT, 2) /* (AD21) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */ 247 AM65X_IOPAD(0x0110, PIN_OUTPUT, 2) /* (AH20) PRG1_PRU0_GPO12.PRG1_RGMII1_TD0 */ 248 AM65X_IOPAD(0x0114, PIN_OUTPUT, 2) /* (AH21) PRG1_PRU0_GPO13.PRG1_RGMII1_TD1 */ 249 AM65X_IOPAD(0x0118, PIN_OUTPUT, 2) /* (AG20) PRG1_PRU0_GPO14.PRG1_RGMII1_TD2 */ 250 AM65X_IOPAD(0x011c, PIN_OUTPUT, 2) /* (AD19) PRG1_PRU0_GPO15.PRG1_RGMII1_TD3 */ 251 AM65X_IOPAD(0x0120, PIN_INPUT, 2) /* (AD20) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */ 252 AM65X_IOPAD(0x010c, PIN_OUTPUT, 2) /* (AF21) PRG1_PRU0_GPO11.PRG1_RGMII1_TX_CTL */ 253 AM65X_IOPAD(0x00f8, PIN_INPUT, 2) /* (AF22) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */ 254 AM65X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AG23) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */ 255 >; 256 }; 257 258 icssg1_iep0_pins_default: icssg1-iep0-default-pins { 259 pinctrl-single,pins = < 260 AM65X_IOPAD(0x012c, PIN_INPUT, 2) /* (AG26) PRG1_PRU0_GPO19.PRG1_IEP0_EDC_SYNC_OUT0 */ 261 >; 262 }; 263 264 mcan0_gpio_pins_default: mcan0-gpio-default-pins { 265 pinctrl-single,pins = < 266 AM65X_IOPAD(0x023c, PIN_INPUT, 7) /* (V25) PRG0_PRU0_GPIO18:GPIO1_47 */ 267 >; 268 }; 269 270 mcan1_gpio_pins_default: mcan1-gpio-default-pins { 271 pinctrl-single,pins = < 272 AM65X_IOPAD(0x028c, PIN_INPUT, 7) /* (Y26) PRG0_PRU1_GPIO18.GPIO1_67 */ 273 >; 274 }; 275}; 276 277&wkup_pmx0 { 278 mcu_mcan0_pins_default: mcu-mcan0-default-pins { 279 pinctrl-single,pins = < 280 AM65X_WKUP_IOPAD(0x00ac, PIN_INPUT_PULLUP, 0) /* (W2) MCU_MCAN0_RX */ 281 AM65X_WKUP_IOPAD(0x00a8, PIN_OUTPUT_PULLUP, 0) /* (W1) MCU_MCAN0_TX */ 282 >; 283 }; 284 285 mcu_mcan1_pins_default: mcu-mcan1-default-pins { 286 pinctrl-single,pins = < 287 AM65X_WKUP_IOPAD(0x00c4, PIN_INPUT_PULLUP, 1) /* (AD3) WKUP_GPIO0_5.MCU_MCAN1_RX */ 288 AM65X_WKUP_IOPAD(0x00c0, PIN_OUTPUT_PULLUP, 1) /* (AC3) WKUP_GPIO0_4.MCU_MCAN1_TX */ 289 >; 290 }; 291}; 292 293&icssg0_mdio { 294 status = "okay"; 295 pinctrl-names = "default"; 296 pinctrl-0 = <&icssg0_mdio_pins_default>; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 300 icssg0_phy0: ethernet-phy@0 { 301 reg = <0>; 302 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 303 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 304 }; 305 306 icssg0_phy1: ethernet-phy@3 { 307 reg = <3>; 308 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 309 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 310 }; 311}; 312 313&icssg0_iep0 { 314 pinctrl-names = "default"; 315 pinctrl-0 = <&icssg0_iep0_pins_default>; 316}; 317 318&icssg1_mdio { 319 status = "okay"; 320 pinctrl-names = "default"; 321 pinctrl-0 = <&icssg1_mdio_pins_default>; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 325 icssg1_phy0: ethernet-phy@0 { 326 reg = <0>; 327 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 328 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 329 }; 330 331 icssg1_phy1: ethernet-phy@3 { 332 reg = <3>; 333 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 334 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 335 }; 336}; 337 338&icssg1_iep0 { 339 pinctrl-names = "default"; 340 pinctrl-0 = <&icssg1_iep0_pins_default>; 341}; 342 343&m_can0 { 344 pinctrl-names = "default"; 345 pinctrl-0 = <&mcu_mcan0_pins_default>; 346 phys = <&transceiver1>; 347 status = "okay"; 348}; 349 350&m_can1 { 351 pinctrl-names = "default"; 352 pinctrl-0 = <&mcu_mcan1_pins_default>; 353 phys = <&transceiver2>; 354 status = "okay"; 355}; 356