xref: /linux/arch/arm64/boot/dts/ti/k3-am654-idk.dtso (revision 6d9b262afe0ec1d6e0ef99321ca9d6b921310471)
1// SPDX-License-Identifier: GPL-2.0-only OR MIT
2/**
3 * DT overlay for IDK application board on AM654 EVM
4 *
5 * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8/dts-v1/;
9/plugin/;
10
11#include <dt-bindings/net/ti-dp83867.h>
12#include "k3-pinctrl.h"
13
14&{/} {
15	aliases {
16		ethernet3 = "/icssg0-eth/ethernet-ports/port@0";
17		ethernet4 = "/icssg0-eth/ethernet-ports/port@1";
18		ethernet5 = "/icssg1-eth/ethernet-ports/port@0";
19		ethernet6 = "/icssg1-eth/ethernet-ports/port@1";
20	};
21
22	/* Ethernet node on PRU-ICSSG0 */
23	icssg0_eth: icssg0-eth {
24		compatible = "ti,am654-icssg-prueth";
25		pinctrl-names = "default";
26		pinctrl-0 = <&icssg0_rgmii_pins_default>;
27		sram = <&msmc_ram>;
28		ti,prus = <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, <&pru0_1>, <&rtu0_1>, <&tx_pru0_1>;
29		firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
30				"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
31				"ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
32				"ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
33				"ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
34				"ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
35
36		ti,pruss-gp-mux-sel = <2>,	/* MII mode */
37				      <2>,
38				      <2>,
39				      <2>,	/* MII mode */
40				      <2>,
41				      <2>;
42
43		ti,mii-g-rt = <&icssg0_mii_g_rt>;
44		ti,mii-rt = <&icssg0_mii_rt>;
45		ti,iep = <&icssg0_iep0>,  <&icssg0_iep1>;
46
47		interrupt-parent = <&icssg0_intc>;
48		interrupts = <24 0 2>, <25 1 3>;
49		interrupt-names = "tx_ts0", "tx_ts1";
50
51		dmas = <&main_udmap 0xc100>, /* egress slice 0 */
52		       <&main_udmap 0xc101>, /* egress slice 0 */
53		       <&main_udmap 0xc102>, /* egress slice 0 */
54		       <&main_udmap 0xc103>, /* egress slice 0 */
55		       <&main_udmap 0xc104>, /* egress slice 1 */
56		       <&main_udmap 0xc105>, /* egress slice 1 */
57		       <&main_udmap 0xc106>, /* egress slice 1 */
58		       <&main_udmap 0xc107>, /* egress slice 1 */
59
60		       <&main_udmap 0x4100>, /* ingress slice 0 */
61		       <&main_udmap 0x4101>, /* ingress slice 1 */
62		       <&main_udmap 0x4102>, /* mgmnt rsp slice 0 */
63		       <&main_udmap 0x4103>; /* mgmnt rsp slice 1 */
64		dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
65			    "tx1-0", "tx1-1", "tx1-2", "tx1-3",
66			    "rx0", "rx1";
67
68		ethernet-ports {
69			#address-cells = <1>;
70			#size-cells = <0>;
71			icssg0_emac0: port@0 {
72				reg = <0>;
73				phy-handle = <&icssg0_phy0>;
74				phy-mode = "rgmii-id";
75				ti,syscon-rgmii-delay = <&scm_conf 0x4100>;
76				/* Filled in by bootloader */
77				local-mac-address = [00 00 00 00 00 00];
78			};
79			icssg0_emac1: port@1 {
80				reg = <1>;
81				phy-handle = <&icssg0_phy1>;
82				phy-mode = "rgmii-id";
83				ti,syscon-rgmii-delay = <&scm_conf 0x4104>;
84				/* Filled in by bootloader */
85				local-mac-address = [00 00 00 00 00 00];
86			};
87		};
88	};
89
90	/* Ethernet node on PRU-ICSSG1 */
91	icssg1_eth: icssg1-eth {
92		compatible = "ti,am654-icssg-prueth";
93		pinctrl-names = "default";
94		pinctrl-0 = <&icssg1_rgmii_pins_default>;
95		sram = <&msmc_ram>;
96		ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>;
97		firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
98				"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
99				"ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
100				"ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
101				"ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
102				"ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
103
104		ti,pruss-gp-mux-sel = <2>,	/* MII mode */
105				      <2>,
106				      <2>,
107				      <2>,	/* MII mode */
108				      <2>,
109				      <2>;
110
111		ti,mii-g-rt = <&icssg1_mii_g_rt>;
112		ti,mii-rt = <&icssg1_mii_rt>;
113		ti,iep = <&icssg1_iep0>,  <&icssg1_iep1>;
114
115		interrupt-parent = <&icssg1_intc>;
116		interrupts = <24 0 2>, <25 1 3>;
117		interrupt-names = "tx_ts0", "tx_ts1";
118
119		dmas = <&main_udmap 0xc200>, /* egress slice 0 */
120		       <&main_udmap 0xc201>, /* egress slice 0 */
121		       <&main_udmap 0xc202>, /* egress slice 0 */
122		       <&main_udmap 0xc203>, /* egress slice 0 */
123		       <&main_udmap 0xc204>, /* egress slice 1 */
124		       <&main_udmap 0xc205>, /* egress slice 1 */
125		       <&main_udmap 0xc206>, /* egress slice 1 */
126		       <&main_udmap 0xc207>, /* egress slice 1 */
127
128		       <&main_udmap 0x4200>, /* ingress slice 0 */
129		       <&main_udmap 0x4201>, /* ingress slice 1 */
130		       <&main_udmap 0x4202>, /* mgmnt rsp slice 0 */
131		       <&main_udmap 0x4203>; /* mgmnt rsp slice 1 */
132		dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
133			    "tx1-0", "tx1-1", "tx1-2", "tx1-3",
134			    "rx0", "rx1";
135
136		ethernet-ports {
137			#address-cells = <1>;
138			#size-cells = <0>;
139			icssg1_emac0: port@0 {
140				reg = <0>;
141				phy-handle = <&icssg1_phy0>;
142				phy-mode = "rgmii-id";
143				ti,syscon-rgmii-delay = <&scm_conf 0x4110>;
144				/* Filled in by bootloader */
145				local-mac-address = [00 00 00 00 00 00];
146			};
147			icssg1_emac1: port@1 {
148				reg = <1>;
149				phy-handle = <&icssg1_phy1>;
150				phy-mode = "rgmii-id";
151				ti,syscon-rgmii-delay = <&scm_conf 0x4114>;
152				/* Filled in by bootloader */
153				local-mac-address = [00 00 00 00 00 00];
154			};
155		};
156	};
157};
158
159&main_pmx0 {
160
161	icssg0_mdio_pins_default: icssg0-mdio-default-pins {
162		pinctrl-single,pins = <
163			AM65X_IOPAD(0x0294, PIN_INPUT, 0) /* (AE26) PRG0_MDIO0_MDIO */
164			AM65X_IOPAD(0x0298, PIN_OUTPUT, 0) /* (AE28) PRG0_MDIO0_MDC */
165		>;
166	};
167
168	icssg0_rgmii_pins_default: icssg0-rgmii-default-pins {
169		pinctrl-single,pins = <
170			AM65X_IOPAD(0x0244, PIN_INPUT, 2) /* (AB28) PRG0_PRU1_GPO0.PRG0_RGMII2_RD0 */
171			AM65X_IOPAD(0x0248, PIN_INPUT, 2) /* (AC28) PRG0_PRU1_GPO1.PRG0_RGMII2_RD1 */
172			AM65X_IOPAD(0x024c, PIN_INPUT, 2) /* (AC27) PRG0_PRU1_GPO2.PRG0_RGMII2_RD2 */
173			AM65X_IOPAD(0x0250, PIN_INPUT, 2) /* (AB26) PRG0_PRU1_GPO3.PRG0_RGMII2_RD3 */
174			AM65X_IOPAD(0x0274, PIN_OUTPUT, 2) /* (AC25) PRG0_PRU1_GPO12.PRG0_RGMII2_TD0 */
175			AM65X_IOPAD(0x0278, PIN_OUTPUT, 2) /* (AD25) PRG0_PRU1_GPO13.PRG0_RGMII2_TD1 */
176			AM65X_IOPAD(0x027c, PIN_OUTPUT, 2) /* (AD24) PRG0_PRU1_GPO14.PRG0_RGMII2_TD2 */
177			AM65X_IOPAD(0x0280, PIN_OUTPUT, 2) /* (AE27) PRG0_PRU1_GPO15.PRG0_RGMII2_TD3 */
178			AM65X_IOPAD(0x0284, PIN_INPUT, 2) /* (AC24) PRG0_PRU1_GPO16.PRG0_RGMII2_TXC */
179			AM65X_IOPAD(0x0270, PIN_OUTPUT, 2) /* (AB24) PRG0_PRU1_GPO11.PRG0_RGMII2_TX_CTL */
180			AM65X_IOPAD(0x025c, PIN_INPUT, 2) /* (AB27) PRG0_PRU1_GPO6.PRG0_RGMII2_RXC */
181			AM65X_IOPAD(0x0254, PIN_INPUT, 2) /* (AA25) PRG0_PRU1_GPO4.PRG0_RGMII2_RX_CTL */
182
183			AM65X_IOPAD(0x01f4, PIN_INPUT, 2) /* (V24) PRG0_PRU0_GPO0.PRG0_RGMII1_RD0 */
184			AM65X_IOPAD(0x01f8, PIN_INPUT, 2) /* (W25) PRG0_PRU0_GPO1.PRG0_RGMII1_RD1 */
185			AM65X_IOPAD(0x01fc, PIN_INPUT, 2) /* (W24) PRG0_PRU0_GPO2.PRG0_RGMII1_RD2 */
186			AM65X_IOPAD(0x0200, PIN_INPUT, 2) /* (AA27) PRG0_PRU0_GPO3.PRG0_RGMII1_RD3 */
187			AM65X_IOPAD(0x0224, PIN_OUTPUT, 2) /* (AD27) PRG0_PRU0_GPO12.PRG0_RGMII1_TD0 */
188			AM65X_IOPAD(0x0228, PIN_OUTPUT, 2) /* (AC26) PRG0_PRU0_GPO13.PRG0_RGMII1_TD1 */
189			AM65X_IOPAD(0x022c, PIN_OUTPUT, 2) /* (AD26) PRG0_PRU0_GPO14.PRG0_RGMII1_TD2 */
190			AM65X_IOPAD(0x0230, PIN_OUTPUT, 2) /* (AA24) PRG0_PRU0_GPO15.PRG0_RGMII1_TD3 */
191			AM65X_IOPAD(0x0234, PIN_INPUT, 2) /* (AD28) PRG0_PRU0_GPO16.PRG0_RGMII1_TXC */
192			AM65X_IOPAD(0x0220, PIN_OUTPUT, 2) /* (AB25) PRG0_PRU0_GPO11.PRG0_RGMII1_TX_CTL */
193			AM65X_IOPAD(0x020c, PIN_INPUT, 2) /* (Y25) PRG0_PRU0_GPO6.PRG0_RGMII1_RXC */
194			AM65X_IOPAD(0x0204, PIN_INPUT, 2) /* (Y24) PRG0_PRU0_GPO4.PRG0_RGMII1_RX_CTL */
195		>;
196	};
197
198	icssg0_iep0_pins_default: icssg0-iep0-default-pins {
199		pinctrl-single,pins = <
200			AM65X_IOPAD(0x0240, PIN_INPUT, 2) /* (U24) PRG0_PRU0_GPO19.PRG0_IEP0_EDC_SYNC_OUT0 */
201		>;
202	};
203
204	icssg1_mdio_pins_default: icssg1-mdio-default-pins {
205		pinctrl-single,pins = <
206			AM65X_IOPAD(0x0180, PIN_INPUT, 0) /* (AD18) PRG1_MDIO0_MDIO */
207			AM65X_IOPAD(0x0184, PIN_OUTPUT, 0) /* (AH18) PRG1_MDIO0_MDC */
208		>;
209	};
210
211	icssg1_rgmii_pins_default: icssg1-rgmii-default-pins {
212		pinctrl-single,pins = <
213			AM65X_IOPAD(0x0130, PIN_INPUT, 2) /* (AH24) PRG1_PRU1_GPO0.PRG1_RGMII2_RD0 */
214			AM65X_IOPAD(0x0134, PIN_INPUT, 2) /* (AH23) PRG1_PRU1_GPO1.PRG1_RGMII2_RD1 */
215			AM65X_IOPAD(0x0138, PIN_INPUT, 2) /* (AG21) PRG1_PRU1_GPO2.PRG1_RGMII2_RD2 */
216			AM65X_IOPAD(0x013c, PIN_INPUT, 2) /* (AH22) PRG1_PRU1_GPO3.PRG1_RGMII2_RD3 */
217			AM65X_IOPAD(0x0160, PIN_OUTPUT, 2) /* (AE20) PRG1_PRU1_GPO12.PRG1_RGMII2_TD0 */
218			AM65X_IOPAD(0x0164, PIN_OUTPUT, 2) /* (AF19) PRG1_PRU1_GPO13.PRG1_RGMII2_TD1 */
219			AM65X_IOPAD(0x0168, PIN_OUTPUT, 2) /* (AH19) PRG1_PRU1_GPO14.PRG1_RGMII2_TD2 */
220			AM65X_IOPAD(0x016c, PIN_OUTPUT, 2) /* (AG19) PRG1_PRU1_GPO15.PRG1_RGMII2_TD3 */
221			AM65X_IOPAD(0x0170, PIN_INPUT, 2) /* (AE19) PRG1_PRU1_GPO16.PRG1_RGMII2_TXC */
222			AM65X_IOPAD(0x015c, PIN_OUTPUT, 2) /* (AC20) PRG1_PRU1_GPO11.PRG1_RGMII2_TX_CTL */
223			AM65X_IOPAD(0x0148, PIN_INPUT, 2) /* (AG22) PRG1_PRU1_GPO6.PRG1_RGMII2_RXC */
224			AM65X_IOPAD(0x0140, PIN_INPUT, 2) /* (AE21) PRG1_PRU1_GPO4.PRG1_RGMII2_RX_CTL */
225
226			AM65X_IOPAD(0x00e0, PIN_INPUT, 2) /* (AE22) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */
227			AM65X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AG24) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */
228			AM65X_IOPAD(0x00e8, PIN_INPUT, 2) /* (AF23) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */
229			AM65X_IOPAD(0x00ec, PIN_INPUT, 2) /* (AD21) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */
230			AM65X_IOPAD(0x0110, PIN_OUTPUT, 2) /* (AH20) PRG1_PRU0_GPO12.PRG1_RGMII1_TD0 */
231			AM65X_IOPAD(0x0114, PIN_OUTPUT, 2) /* (AH21) PRG1_PRU0_GPO13.PRG1_RGMII1_TD1 */
232			AM65X_IOPAD(0x0118, PIN_OUTPUT, 2) /* (AG20) PRG1_PRU0_GPO14.PRG1_RGMII1_TD2 */
233			AM65X_IOPAD(0x011c, PIN_OUTPUT, 2) /* (AD19) PRG1_PRU0_GPO15.PRG1_RGMII1_TD3 */
234			AM65X_IOPAD(0x0120, PIN_INPUT, 2) /* (AD20) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */
235			AM65X_IOPAD(0x010c, PIN_OUTPUT, 2) /* (AF21) PRG1_PRU0_GPO11.PRG1_RGMII1_TX_CTL */
236			AM65X_IOPAD(0x00f8, PIN_INPUT, 2) /* (AF22) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */
237			AM65X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AG23) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */
238		>;
239	};
240
241	icssg1_iep0_pins_default: icssg1-iep0-default-pins {
242		pinctrl-single,pins = <
243			AM65X_IOPAD(0x012c, PIN_INPUT, 2) /* (AG26) PRG1_PRU0_GPO19.PRG1_IEP0_EDC_SYNC_OUT0 */
244		>;
245	};
246};
247
248&icssg0_mdio {
249	status = "okay";
250	pinctrl-names = "default";
251	pinctrl-0 = <&icssg0_mdio_pins_default>;
252	#address-cells = <1>;
253	#size-cells = <0>;
254
255	icssg0_phy0: ethernet-phy@0 {
256		reg = <0>;
257		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
258		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
259	};
260
261	icssg0_phy1: ethernet-phy@3 {
262		reg = <3>;
263		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
264		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
265	};
266};
267
268&icssg0_iep0 {
269	pinctrl-names = "default";
270	pinctrl-0 = <&icssg0_iep0_pins_default>;
271};
272
273&icssg1_mdio {
274	status = "okay";
275	pinctrl-names = "default";
276	pinctrl-0 = <&icssg1_mdio_pins_default>;
277	#address-cells = <1>;
278	#size-cells = <0>;
279
280	icssg1_phy0: ethernet-phy@0 {
281		reg = <0>;
282		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
283		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
284	};
285
286	icssg1_phy1: ethernet-phy@3 {
287		reg = <3>;
288		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
289		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
290	};
291};
292
293&icssg1_iep0 {
294	pinctrl-names = "default";
295	pinctrl-0 = <&icssg1_iep0_pins_default>;
296};
297