1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/** 3 * DT overlay for IDK application board on AM654 EVM 4 * 5 * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8/dts-v1/; 9/plugin/; 10 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/net/ti-dp83867.h> 13#include "k3-pinctrl.h" 14 15&{/} { 16 aliases { 17 ethernet3 = "/icssg0-eth/ethernet-ports/port@0"; 18 ethernet4 = "/icssg0-eth/ethernet-ports/port@1"; 19 ethernet5 = "/icssg1-eth/ethernet-ports/port@0"; 20 ethernet6 = "/icssg1-eth/ethernet-ports/port@1"; 21 }; 22 23 /* Ethernet node on PRU-ICSSG0 */ 24 icssg0_eth: icssg0-eth { 25 compatible = "ti,am654-icssg-prueth"; 26 pinctrl-names = "default"; 27 pinctrl-0 = <&icssg0_rgmii_pins_default>; 28 sram = <&msmc_ram>; 29 ti,prus = <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, <&pru0_1>, <&rtu0_1>, <&tx_pru0_1>; 30 firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", 31 "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", 32 "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", 33 "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", 34 "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", 35 "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; 36 37 ti,pruss-gp-mux-sel = <2>, /* MII mode */ 38 <2>, 39 <2>, 40 <2>, /* MII mode */ 41 <2>, 42 <2>; 43 44 ti,mii-g-rt = <&icssg0_mii_g_rt>; 45 ti,mii-rt = <&icssg0_mii_rt>; 46 ti,iep = <&icssg0_iep0>, <&icssg0_iep1>; 47 48 interrupt-parent = <&icssg0_intc>; 49 interrupts = <24 0 2>, <25 1 3>; 50 interrupt-names = "tx_ts0", "tx_ts1"; 51 52 dmas = <&main_udmap 0xc100>, /* egress slice 0 */ 53 <&main_udmap 0xc101>, /* egress slice 0 */ 54 <&main_udmap 0xc102>, /* egress slice 0 */ 55 <&main_udmap 0xc103>, /* egress slice 0 */ 56 <&main_udmap 0xc104>, /* egress slice 1 */ 57 <&main_udmap 0xc105>, /* egress slice 1 */ 58 <&main_udmap 0xc106>, /* egress slice 1 */ 59 <&main_udmap 0xc107>, /* egress slice 1 */ 60 61 <&main_udmap 0x4100>, /* ingress slice 0 */ 62 <&main_udmap 0x4101>; /* ingress slice 1 */ 63 dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", 64 "tx1-0", "tx1-1", "tx1-2", "tx1-3", 65 "rx0", "rx1"; 66 67 ethernet-ports { 68 #address-cells = <1>; 69 #size-cells = <0>; 70 icssg0_emac0: port@0 { 71 reg = <0>; 72 phy-handle = <&icssg0_phy0>; 73 phy-mode = "rgmii-id"; 74 ti,syscon-rgmii-delay = <&scm_conf 0x4100>; 75 /* Filled in by bootloader */ 76 local-mac-address = [00 00 00 00 00 00]; 77 }; 78 icssg0_emac1: port@1 { 79 reg = <1>; 80 phy-handle = <&icssg0_phy1>; 81 phy-mode = "rgmii-id"; 82 ti,syscon-rgmii-delay = <&scm_conf 0x4104>; 83 /* Filled in by bootloader */ 84 local-mac-address = [00 00 00 00 00 00]; 85 }; 86 }; 87 }; 88 89 /* Ethernet node on PRU-ICSSG1 */ 90 icssg1_eth: icssg1-eth { 91 compatible = "ti,am654-icssg-prueth"; 92 pinctrl-names = "default"; 93 pinctrl-0 = <&icssg1_rgmii_pins_default>; 94 sram = <&msmc_ram>; 95 ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>; 96 firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", 97 "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", 98 "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", 99 "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", 100 "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", 101 "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; 102 103 ti,pruss-gp-mux-sel = <2>, /* MII mode */ 104 <2>, 105 <2>, 106 <2>, /* MII mode */ 107 <2>, 108 <2>; 109 110 ti,mii-g-rt = <&icssg1_mii_g_rt>; 111 ti,mii-rt = <&icssg1_mii_rt>; 112 ti,iep = <&icssg1_iep0>, <&icssg1_iep1>; 113 114 interrupt-parent = <&icssg1_intc>; 115 interrupts = <24 0 2>, <25 1 3>; 116 interrupt-names = "tx_ts0", "tx_ts1"; 117 118 dmas = <&main_udmap 0xc200>, /* egress slice 0 */ 119 <&main_udmap 0xc201>, /* egress slice 0 */ 120 <&main_udmap 0xc202>, /* egress slice 0 */ 121 <&main_udmap 0xc203>, /* egress slice 0 */ 122 <&main_udmap 0xc204>, /* egress slice 1 */ 123 <&main_udmap 0xc205>, /* egress slice 1 */ 124 <&main_udmap 0xc206>, /* egress slice 1 */ 125 <&main_udmap 0xc207>, /* egress slice 1 */ 126 127 <&main_udmap 0x4200>, /* ingress slice 0 */ 128 <&main_udmap 0x4201>; /* ingress slice 1 */ 129 dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", 130 "tx1-0", "tx1-1", "tx1-2", "tx1-3", 131 "rx0", "rx1"; 132 133 ethernet-ports { 134 #address-cells = <1>; 135 #size-cells = <0>; 136 icssg1_emac0: port@0 { 137 reg = <0>; 138 phy-handle = <&icssg1_phy0>; 139 phy-mode = "rgmii-id"; 140 ti,syscon-rgmii-delay = <&scm_conf 0x4110>; 141 /* Filled in by bootloader */ 142 local-mac-address = [00 00 00 00 00 00]; 143 }; 144 icssg1_emac1: port@1 { 145 reg = <1>; 146 phy-handle = <&icssg1_phy1>; 147 phy-mode = "rgmii-id"; 148 ti,syscon-rgmii-delay = <&scm_conf 0x4114>; 149 /* Filled in by bootloader */ 150 local-mac-address = [00 00 00 00 00 00]; 151 }; 152 }; 153 }; 154 155 transceiver1: can-phy0 { 156 compatible = "ti,tcan1042"; 157 #phy-cells = <0>; 158 max-bitrate = <5000000>; 159 pinctrl-names = "default"; 160 pinctrl-0 = <&mcan0_gpio_pins_default>; 161 standby-gpios = <&main_gpio1 47 GPIO_ACTIVE_LOW>; 162 }; 163 164 transceiver2: can-phy1 { 165 compatible = "ti,tcan1042"; 166 #phy-cells = <0>; 167 max-bitrate = <5000000>; 168 pinctrl-names = "default"; 169 pinctrl-0 = <&mcan1_gpio_pins_default>; 170 standby-gpios = <&main_gpio1 67 GPIO_ACTIVE_LOW>; 171 }; 172}; 173 174&main_pmx0 { 175 176 icssg0_mdio_pins_default: icssg0-mdio-default-pins { 177 pinctrl-single,pins = < 178 AM65X_IOPAD(0x0294, PIN_INPUT, 0) /* (AE26) PRG0_MDIO0_MDIO */ 179 AM65X_IOPAD(0x0298, PIN_OUTPUT, 0) /* (AE28) PRG0_MDIO0_MDC */ 180 >; 181 }; 182 183 icssg0_rgmii_pins_default: icssg0-rgmii-default-pins { 184 pinctrl-single,pins = < 185 AM65X_IOPAD(0x0244, PIN_INPUT, 2) /* (AB28) PRG0_PRU1_GPO0.PRG0_RGMII2_RD0 */ 186 AM65X_IOPAD(0x0248, PIN_INPUT, 2) /* (AC28) PRG0_PRU1_GPO1.PRG0_RGMII2_RD1 */ 187 AM65X_IOPAD(0x024c, PIN_INPUT, 2) /* (AC27) PRG0_PRU1_GPO2.PRG0_RGMII2_RD2 */ 188 AM65X_IOPAD(0x0250, PIN_INPUT, 2) /* (AB26) PRG0_PRU1_GPO3.PRG0_RGMII2_RD3 */ 189 AM65X_IOPAD(0x0274, PIN_OUTPUT, 2) /* (AC25) PRG0_PRU1_GPO12.PRG0_RGMII2_TD0 */ 190 AM65X_IOPAD(0x0278, PIN_OUTPUT, 2) /* (AD25) PRG0_PRU1_GPO13.PRG0_RGMII2_TD1 */ 191 AM65X_IOPAD(0x027c, PIN_OUTPUT, 2) /* (AD24) PRG0_PRU1_GPO14.PRG0_RGMII2_TD2 */ 192 AM65X_IOPAD(0x0280, PIN_OUTPUT, 2) /* (AE27) PRG0_PRU1_GPO15.PRG0_RGMII2_TD3 */ 193 AM65X_IOPAD(0x0284, PIN_INPUT, 2) /* (AC24) PRG0_PRU1_GPO16.PRG0_RGMII2_TXC */ 194 AM65X_IOPAD(0x0270, PIN_OUTPUT, 2) /* (AB24) PRG0_PRU1_GPO11.PRG0_RGMII2_TX_CTL */ 195 AM65X_IOPAD(0x025c, PIN_INPUT, 2) /* (AB27) PRG0_PRU1_GPO6.PRG0_RGMII2_RXC */ 196 AM65X_IOPAD(0x0254, PIN_INPUT, 2) /* (AA25) PRG0_PRU1_GPO4.PRG0_RGMII2_RX_CTL */ 197 198 AM65X_IOPAD(0x01f4, PIN_INPUT, 2) /* (V24) PRG0_PRU0_GPO0.PRG0_RGMII1_RD0 */ 199 AM65X_IOPAD(0x01f8, PIN_INPUT, 2) /* (W25) PRG0_PRU0_GPO1.PRG0_RGMII1_RD1 */ 200 AM65X_IOPAD(0x01fc, PIN_INPUT, 2) /* (W24) PRG0_PRU0_GPO2.PRG0_RGMII1_RD2 */ 201 AM65X_IOPAD(0x0200, PIN_INPUT, 2) /* (AA27) PRG0_PRU0_GPO3.PRG0_RGMII1_RD3 */ 202 AM65X_IOPAD(0x0224, PIN_OUTPUT, 2) /* (AD27) PRG0_PRU0_GPO12.PRG0_RGMII1_TD0 */ 203 AM65X_IOPAD(0x0228, PIN_OUTPUT, 2) /* (AC26) PRG0_PRU0_GPO13.PRG0_RGMII1_TD1 */ 204 AM65X_IOPAD(0x022c, PIN_OUTPUT, 2) /* (AD26) PRG0_PRU0_GPO14.PRG0_RGMII1_TD2 */ 205 AM65X_IOPAD(0x0230, PIN_OUTPUT, 2) /* (AA24) PRG0_PRU0_GPO15.PRG0_RGMII1_TD3 */ 206 AM65X_IOPAD(0x0234, PIN_INPUT, 2) /* (AD28) PRG0_PRU0_GPO16.PRG0_RGMII1_TXC */ 207 AM65X_IOPAD(0x0220, PIN_OUTPUT, 2) /* (AB25) PRG0_PRU0_GPO11.PRG0_RGMII1_TX_CTL */ 208 AM65X_IOPAD(0x020c, PIN_INPUT, 2) /* (Y25) PRG0_PRU0_GPO6.PRG0_RGMII1_RXC */ 209 AM65X_IOPAD(0x0204, PIN_INPUT, 2) /* (Y24) PRG0_PRU0_GPO4.PRG0_RGMII1_RX_CTL */ 210 >; 211 }; 212 213 icssg0_iep0_pins_default: icssg0-iep0-default-pins { 214 pinctrl-single,pins = < 215 AM65X_IOPAD(0x0240, PIN_INPUT, 2) /* (U24) PRG0_PRU0_GPO19.PRG0_IEP0_EDC_SYNC_OUT0 */ 216 >; 217 }; 218 219 icssg1_mdio_pins_default: icssg1-mdio-default-pins { 220 pinctrl-single,pins = < 221 AM65X_IOPAD(0x0180, PIN_INPUT, 0) /* (AD18) PRG1_MDIO0_MDIO */ 222 AM65X_IOPAD(0x0184, PIN_OUTPUT, 0) /* (AH18) PRG1_MDIO0_MDC */ 223 >; 224 }; 225 226 icssg1_rgmii_pins_default: icssg1-rgmii-default-pins { 227 pinctrl-single,pins = < 228 AM65X_IOPAD(0x0130, PIN_INPUT, 2) /* (AH24) PRG1_PRU1_GPO0.PRG1_RGMII2_RD0 */ 229 AM65X_IOPAD(0x0134, PIN_INPUT, 2) /* (AH23) PRG1_PRU1_GPO1.PRG1_RGMII2_RD1 */ 230 AM65X_IOPAD(0x0138, PIN_INPUT, 2) /* (AG21) PRG1_PRU1_GPO2.PRG1_RGMII2_RD2 */ 231 AM65X_IOPAD(0x013c, PIN_INPUT, 2) /* (AH22) PRG1_PRU1_GPO3.PRG1_RGMII2_RD3 */ 232 AM65X_IOPAD(0x0160, PIN_OUTPUT, 2) /* (AE20) PRG1_PRU1_GPO12.PRG1_RGMII2_TD0 */ 233 AM65X_IOPAD(0x0164, PIN_OUTPUT, 2) /* (AF19) PRG1_PRU1_GPO13.PRG1_RGMII2_TD1 */ 234 AM65X_IOPAD(0x0168, PIN_OUTPUT, 2) /* (AH19) PRG1_PRU1_GPO14.PRG1_RGMII2_TD2 */ 235 AM65X_IOPAD(0x016c, PIN_OUTPUT, 2) /* (AG19) PRG1_PRU1_GPO15.PRG1_RGMII2_TD3 */ 236 AM65X_IOPAD(0x0170, PIN_INPUT, 2) /* (AE19) PRG1_PRU1_GPO16.PRG1_RGMII2_TXC */ 237 AM65X_IOPAD(0x015c, PIN_OUTPUT, 2) /* (AC20) PRG1_PRU1_GPO11.PRG1_RGMII2_TX_CTL */ 238 AM65X_IOPAD(0x0148, PIN_INPUT, 2) /* (AG22) PRG1_PRU1_GPO6.PRG1_RGMII2_RXC */ 239 AM65X_IOPAD(0x0140, PIN_INPUT, 2) /* (AE21) PRG1_PRU1_GPO4.PRG1_RGMII2_RX_CTL */ 240 241 AM65X_IOPAD(0x00e0, PIN_INPUT, 2) /* (AE22) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */ 242 AM65X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AG24) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */ 243 AM65X_IOPAD(0x00e8, PIN_INPUT, 2) /* (AF23) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */ 244 AM65X_IOPAD(0x00ec, PIN_INPUT, 2) /* (AD21) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */ 245 AM65X_IOPAD(0x0110, PIN_OUTPUT, 2) /* (AH20) PRG1_PRU0_GPO12.PRG1_RGMII1_TD0 */ 246 AM65X_IOPAD(0x0114, PIN_OUTPUT, 2) /* (AH21) PRG1_PRU0_GPO13.PRG1_RGMII1_TD1 */ 247 AM65X_IOPAD(0x0118, PIN_OUTPUT, 2) /* (AG20) PRG1_PRU0_GPO14.PRG1_RGMII1_TD2 */ 248 AM65X_IOPAD(0x011c, PIN_OUTPUT, 2) /* (AD19) PRG1_PRU0_GPO15.PRG1_RGMII1_TD3 */ 249 AM65X_IOPAD(0x0120, PIN_INPUT, 2) /* (AD20) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */ 250 AM65X_IOPAD(0x010c, PIN_OUTPUT, 2) /* (AF21) PRG1_PRU0_GPO11.PRG1_RGMII1_TX_CTL */ 251 AM65X_IOPAD(0x00f8, PIN_INPUT, 2) /* (AF22) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */ 252 AM65X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AG23) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */ 253 >; 254 }; 255 256 icssg1_iep0_pins_default: icssg1-iep0-default-pins { 257 pinctrl-single,pins = < 258 AM65X_IOPAD(0x012c, PIN_INPUT, 2) /* (AG26) PRG1_PRU0_GPO19.PRG1_IEP0_EDC_SYNC_OUT0 */ 259 >; 260 }; 261 262 mcan0_gpio_pins_default: mcan0-gpio-default-pins { 263 pinctrl-single,pins = < 264 AM65X_IOPAD(0x023c, PIN_INPUT, 7) /* (V25) PRG0_PRU0_GPIO18:GPIO1_47 */ 265 >; 266 }; 267 268 mcan1_gpio_pins_default: mcan1-gpio-default-pins { 269 pinctrl-single,pins = < 270 AM65X_IOPAD(0x028c, PIN_INPUT, 7) /* (Y26) PRG0_PRU1_GPIO18.GPIO1_67 */ 271 >; 272 }; 273}; 274 275&wkup_pmx0 { 276 mcu_mcan0_pins_default: mcu-mcan0-default-pins { 277 pinctrl-single,pins = < 278 AM65X_WKUP_IOPAD(0x00ac, PIN_INPUT_PULLUP, 0) /* (W2) MCU_MCAN0_RX */ 279 AM65X_WKUP_IOPAD(0x00a8, PIN_OUTPUT_PULLUP, 0) /* (W1) MCU_MCAN0_TX */ 280 >; 281 }; 282 283 mcu_mcan1_pins_default: mcu-mcan1-default-pins { 284 pinctrl-single,pins = < 285 AM65X_WKUP_IOPAD(0x00c4, PIN_INPUT_PULLUP, 1) /* (AD3) WKUP_GPIO0_5.MCU_MCAN1_RX */ 286 AM65X_WKUP_IOPAD(0x00c0, PIN_OUTPUT_PULLUP, 1) /* (AC3) WKUP_GPIO0_4.MCU_MCAN1_TX */ 287 >; 288 }; 289}; 290 291&icssg0_mdio { 292 status = "okay"; 293 pinctrl-names = "default"; 294 pinctrl-0 = <&icssg0_mdio_pins_default>; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 298 icssg0_phy0: ethernet-phy@0 { 299 reg = <0>; 300 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 301 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 302 }; 303 304 icssg0_phy1: ethernet-phy@3 { 305 reg = <3>; 306 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 307 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 308 }; 309}; 310 311&icssg0_iep0 { 312 pinctrl-names = "default"; 313 pinctrl-0 = <&icssg0_iep0_pins_default>; 314}; 315 316&icssg1_mdio { 317 status = "okay"; 318 pinctrl-names = "default"; 319 pinctrl-0 = <&icssg1_mdio_pins_default>; 320 #address-cells = <1>; 321 #size-cells = <0>; 322 323 icssg1_phy0: ethernet-phy@0 { 324 reg = <0>; 325 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 326 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 327 }; 328 329 icssg1_phy1: ethernet-phy@3 { 330 reg = <3>; 331 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 332 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 333 }; 334}; 335 336&icssg1_iep0 { 337 pinctrl-names = "default"; 338 pinctrl-0 = <&icssg1_iep0_pins_default>; 339}; 340 341&m_can0 { 342 pinctrl-names = "default"; 343 pinctrl-0 = <&mcu_mcan0_pins_default>; 344 phys = <&transceiver1>; 345 status = "okay"; 346}; 347 348&m_can1 { 349 pinctrl-names = "default"; 350 pinctrl-0 = <&mcu_mcan1_pins_default>; 351 phys = <&transceiver2>; 352 status = "okay"; 353}; 354