1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for AM65 SoC family in Dual core configuration 4 * 5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include "k3-am65.dtsi" 9 10/ { 11 cpus { 12 #address-cells = <1>; 13 #size-cells = <0>; 14 cpu-map { 15 cluster0: cluster0 { 16 core0 { 17 cpu = <&cpu0>; 18 }; 19 20 core1 { 21 cpu = <&cpu1>; 22 }; 23 }; 24 }; 25 26 cpu0: cpu@0 { 27 compatible = "arm,cortex-a53"; 28 reg = <0x000>; 29 device_type = "cpu"; 30 enable-method = "psci"; 31 i-cache-size = <0x8000>; 32 i-cache-line-size = <64>; 33 i-cache-sets = <256>; 34 d-cache-size = <0x8000>; 35 d-cache-line-size = <64>; 36 d-cache-sets = <128>; 37 next-level-cache = <&L2_0>; 38 }; 39 40 cpu1: cpu@1 { 41 compatible = "arm,cortex-a53"; 42 reg = <0x001>; 43 device_type = "cpu"; 44 enable-method = "psci"; 45 i-cache-size = <0x8000>; 46 i-cache-line-size = <64>; 47 i-cache-sets = <256>; 48 d-cache-size = <0x8000>; 49 d-cache-line-size = <64>; 50 d-cache-sets = <128>; 51 next-level-cache = <&L2_0>; 52 }; 53 }; 54 55 L2_0: l2-cache0 { 56 compatible = "cache"; 57 cache-level = <2>; 58 cache-unified; 59 cache-size = <0x80000>; 60 cache-line-size = <64>; 61 cache-sets = <512>; 62 next-level-cache = <&msmc_l3>; 63 }; 64 65 msmc_l3: l3-cache0 { 66 compatible = "cache"; 67 cache-level = <3>; 68 cache-unified; 69 }; 70 71 thermal_zones: thermal-zones { 72 #include "k3-am654-industrial-thermal.dtsi" 73 }; 74}; 75