1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM6 SoC Family 4 * 5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/pinctrl/k3.h> 12#include <dt-bindings/soc/ti,sci_pm_domain.h> 13 14/ { 15 model = "Texas Instruments K3 AM654 SoC"; 16 compatible = "ti,am654"; 17 interrupt-parent = <&gic500>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 serial0 = &wkup_uart0; 23 serial1 = &mcu_uart0; 24 serial2 = &main_uart0; 25 serial3 = &main_uart1; 26 serial4 = &main_uart2; 27 i2c0 = &wkup_i2c0; 28 i2c1 = &mcu_i2c0; 29 i2c2 = &main_i2c0; 30 i2c3 = &main_i2c1; 31 i2c4 = &main_i2c2; 32 i2c5 = &main_i2c3; 33 }; 34 35 chosen { }; 36 37 firmware { 38 optee { 39 compatible = "linaro,optee-tz"; 40 method = "smc"; 41 }; 42 43 psci: psci { 44 compatible = "arm,psci-1.0"; 45 method = "smc"; 46 }; 47 }; 48 49 a53_timer0: timer-cl0-cpu0 { 50 compatible = "arm,armv8-timer"; 51 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ 52 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ 53 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ 54 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ 55 }; 56 57 pmu: pmu { 58 compatible = "arm,armv8-pmuv3"; 59 /* Recommendation from GIC500 TRM Table A.3 */ 60 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 61 }; 62 63 cbass_main: interconnect@100000 { 64 compatible = "simple-bus"; 65 #address-cells = <2>; 66 #size-cells = <2>; 67 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ 68 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ 69 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ 70 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ 71 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */ 72 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */ 73 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ 74 /* MCUSS Range */ 75 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, 76 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, 77 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, 78 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, 79 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, 80 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, 81 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, 82 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, 83 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>; 84 85 cbass_mcu: interconnect@28380000 { 86 compatible = "simple-bus"; 87 #address-cells = <2>; 88 #size-cells = <2>; 89 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ 90 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */ 91 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ 92 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ 93 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, /* MCU SRAM */ 94 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */ 95 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ 96 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ 97 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>; /* OSPI space 1 */ 98 99 cbass_wakeup: interconnect@42040000 { 100 compatible = "simple-bus"; 101 #address-cells = <1>; 102 #size-cells = <1>; 103 /* WKUP Basic peripherals */ 104 ranges = <0x42040000 0x00 0x42040000 0x03ac2400>; 105 }; 106 }; 107 }; 108}; 109 110/* Now include the peripherals for each bus segments */ 111#include "k3-am65-main.dtsi" 112#include "k3-am65-mcu.dtsi" 113#include "k3-am65-wakeup.dtsi" 114