1*a26bc917SBeleswar Padhi// SPDX-License-Identifier: GPL-2.0-only OR MIT 2*a26bc917SBeleswar Padhi/** 3*a26bc917SBeleswar Padhi * Device Tree Source for enabling IPC using TI SDK firmware on AM65 SoCs 4*a26bc917SBeleswar Padhi * 5*a26bc917SBeleswar Padhi * Copyright (C) 2016-2025 Texas Instruments Incorporated - https://www.ti.com/ 6*a26bc917SBeleswar Padhi */ 7*a26bc917SBeleswar Padhi 8*a26bc917SBeleswar Padhi&reserved_memory { 9*a26bc917SBeleswar Padhi mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { 10*a26bc917SBeleswar Padhi compatible = "shared-dma-pool"; 11*a26bc917SBeleswar Padhi reg = <0 0xa1000000 0 0x100000>; 12*a26bc917SBeleswar Padhi no-map; 13*a26bc917SBeleswar Padhi }; 14*a26bc917SBeleswar Padhi 15*a26bc917SBeleswar Padhi mcu_r5fss0_core1_memory_region: memory@a1100000 { 16*a26bc917SBeleswar Padhi compatible = "shared-dma-pool"; 17*a26bc917SBeleswar Padhi reg = <0 0xa1100000 0 0xf00000>; 18*a26bc917SBeleswar Padhi no-map; 19*a26bc917SBeleswar Padhi }; 20*a26bc917SBeleswar Padhi 21*a26bc917SBeleswar Padhi rtos_ipc_memory_region: memory@a2000000 { 22*a26bc917SBeleswar Padhi reg = <0x00 0xa2000000 0x00 0x00100000>; 23*a26bc917SBeleswar Padhi alignment = <0x1000>; 24*a26bc917SBeleswar Padhi no-map; 25*a26bc917SBeleswar Padhi }; 26*a26bc917SBeleswar Padhi}; 27*a26bc917SBeleswar Padhi 28*a26bc917SBeleswar Padhi&mailbox0_cluster0 { 29*a26bc917SBeleswar Padhi status = "okay"; 30*a26bc917SBeleswar Padhi interrupts = <436>; 31*a26bc917SBeleswar Padhi 32*a26bc917SBeleswar Padhi mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 33*a26bc917SBeleswar Padhi ti,mbox-tx = <1 0 0>; 34*a26bc917SBeleswar Padhi ti,mbox-rx = <0 0 0>; 35*a26bc917SBeleswar Padhi }; 36*a26bc917SBeleswar Padhi}; 37*a26bc917SBeleswar Padhi 38*a26bc917SBeleswar Padhi&mailbox0_cluster1 { 39*a26bc917SBeleswar Padhi status = "okay"; 40*a26bc917SBeleswar Padhi interrupts = <432>; 41*a26bc917SBeleswar Padhi 42*a26bc917SBeleswar Padhi mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 43*a26bc917SBeleswar Padhi ti,mbox-tx = <1 0 0>; 44*a26bc917SBeleswar Padhi ti,mbox-rx = <0 0 0>; 45*a26bc917SBeleswar Padhi }; 46*a26bc917SBeleswar Padhi}; 47*a26bc917SBeleswar Padhi 48*a26bc917SBeleswar Padhi&mcu_r5fss0 { 49*a26bc917SBeleswar Padhi status = "okay"; 50*a26bc917SBeleswar Padhi}; 51*a26bc917SBeleswar Padhi 52*a26bc917SBeleswar Padhi&mcu_r5fss0_core0 { 53*a26bc917SBeleswar Padhi memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 54*a26bc917SBeleswar Padhi <&mcu_r5fss0_core0_memory_region>; 55*a26bc917SBeleswar Padhi mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 56*a26bc917SBeleswar Padhi status = "okay"; 57*a26bc917SBeleswar Padhi}; 58*a26bc917SBeleswar Padhi 59*a26bc917SBeleswar Padhi&mcu_r5fss0_core1 { 60*a26bc917SBeleswar Padhi memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 61*a26bc917SBeleswar Padhi <&mcu_r5fss0_core1_memory_region>; 62*a26bc917SBeleswar Padhi mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; 63*a26bc917SBeleswar Padhi status = "okay"; 64*a26bc917SBeleswar Padhi}; 65