1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for AM6 SoC Family MCU Domain peripherals 4 * 5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu { 9 mcu_conf: bus@40f00000 { 10 compatible = "simple-bus"; 11 #address-cells = <1>; 12 #size-cells = <1>; 13 ranges = <0x0 0x0 0x40f00000 0x20000>; 14 15 cpsw_mac_syscon: ethernet-mac-syscon@200 { 16 compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; 17 reg = <0x200 0x8>; 18 }; 19 20 phy_gmii_sel: phy@4040 { 21 compatible = "ti,am654-phy-gmii-sel"; 22 reg = <0x4040 0x4>; 23 #phy-cells = <1>; 24 }; 25 }; 26 27 /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ 28 mcu_timerio_input: pinctrl@40f04200 { 29 compatible = "pinctrl-single"; 30 reg = <0x0 0x40f04200 0x0 0x10>; 31 #pinctrl-cells = <1>; 32 pinctrl-single,register-width = <32>; 33 pinctrl-single,function-mask = <0x00000101>; 34 }; 35 36 /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ 37 mcu_timerio_output: pinctrl@40f04280 { 38 compatible = "pinctrl-single"; 39 reg = <0x0 0x40f04280 0x0 0x8>; 40 #pinctrl-cells = <1>; 41 pinctrl-single,register-width = <32>; 42 pinctrl-single,function-mask = <0x00000003>; 43 }; 44 45 mcu_uart0: serial@40a00000 { 46 compatible = "ti,am654-uart"; 47 reg = <0x00 0x40a00000 0x00 0x100>; 48 interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; 49 clock-frequency = <96000000>; 50 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 51 status = "disabled"; 52 }; 53 54 mcu_ram: sram@41c00000 { 55 compatible = "mmio-sram"; 56 reg = <0x00 0x41c00000 0x00 0x80000>; 57 ranges = <0x0 0x00 0x41c00000 0x80000>; 58 #address-cells = <1>; 59 #size-cells = <1>; 60 }; 61 62 mcu_i2c0: i2c@40b00000 { 63 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 64 reg = <0x0 0x40b00000 0x0 0x100>; 65 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>; 66 #address-cells = <1>; 67 #size-cells = <0>; 68 clock-names = "fck"; 69 clocks = <&k3_clks 114 1>; 70 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 71 status = "disabled"; 72 }; 73 74 mcu_spi0: spi@40300000 { 75 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 76 reg = <0x0 0x40300000 0x0 0x400>; 77 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>; 78 clocks = <&k3_clks 142 1>; 79 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 80 #address-cells = <1>; 81 #size-cells = <0>; 82 status = "disabled"; 83 }; 84 85 mcu_spi1: spi@40310000 { 86 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 87 reg = <0x0 0x40310000 0x0 0x400>; 88 interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 89 clocks = <&k3_clks 143 1>; 90 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 91 #address-cells = <1>; 92 #size-cells = <0>; 93 status = "disabled"; 94 }; 95 96 mcu_spi2: spi@40320000 { 97 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 98 reg = <0x0 0x40320000 0x0 0x400>; 99 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>; 100 clocks = <&k3_clks 144 1>; 101 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; 102 #address-cells = <1>; 103 #size-cells = <0>; 104 status = "disabled"; 105 }; 106 107 tscadc0: tscadc@40200000 { 108 compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; 109 reg = <0x0 0x40200000 0x0 0x1000>; 110 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 111 clocks = <&k3_clks 0 2>; 112 assigned-clocks = <&k3_clks 0 2>; 113 assigned-clock-rates = <60000000>; 114 clock-names = "fck"; 115 dmas = <&mcu_udmap 0x7100>, 116 <&mcu_udmap 0x7101 >; 117 dma-names = "fifo0", "fifo1"; 118 status = "disabled"; 119 120 adc { 121 #io-channel-cells = <1>; 122 compatible = "ti,am654-adc", "ti,am3359-adc"; 123 }; 124 }; 125 126 tscadc1: tscadc@40210000 { 127 compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; 128 reg = <0x0 0x40210000 0x0 0x1000>; 129 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 130 clocks = <&k3_clks 1 2>; 131 assigned-clocks = <&k3_clks 1 2>; 132 assigned-clock-rates = <60000000>; 133 clock-names = "fck"; 134 dmas = <&mcu_udmap 0x7102>, 135 <&mcu_udmap 0x7103>; 136 dma-names = "fifo0", "fifo1"; 137 status = "disabled"; 138 139 adc { 140 #io-channel-cells = <1>; 141 compatible = "ti,am654-adc", "ti,am3359-adc"; 142 }; 143 }; 144 145 /* 146 * The MCU domain timer interrupts are routed only to the ESM module, 147 * and not currently available for Linux. The MCU domain timers are 148 * of limited use without interrupts, and likely reserved by the ESM. 149 */ 150 mcu_timer0: timer@40400000 { 151 compatible = "ti,am654-timer"; 152 reg = <0x00 0x40400000 0x00 0x400>; 153 clocks = <&k3_clks 35 0>; 154 clock-names = "fck"; 155 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 156 ti,timer-pwm; 157 status = "reserved"; 158 }; 159 160 mcu_timer1: timer@40410000 { 161 compatible = "ti,am654-timer"; 162 reg = <0x00 0x40410000 0x00 0x400>; 163 clocks = <&k3_clks 36 0>; 164 clock-names = "fck"; 165 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 166 ti,timer-pwm; 167 status = "reserved"; 168 }; 169 170 mcu_timer2: timer@40420000 { 171 compatible = "ti,am654-timer"; 172 reg = <0x00 0x40420000 0x00 0x400>; 173 clocks = <&k3_clks 37 0>; 174 clock-names = "fck"; 175 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 176 ti,timer-pwm; 177 status = "reserved"; 178 }; 179 180 mcu_timer3: timer@40430000 { 181 compatible = "ti,am654-timer"; 182 reg = <0x00 0x40430000 0x00 0x400>; 183 clocks = <&k3_clks 38 0>; 184 clock-names = "fck"; 185 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 186 ti,timer-pwm; 187 status = "reserved"; 188 }; 189 190 mcu_navss: bus@28380000 { 191 compatible = "simple-bus"; 192 #address-cells = <2>; 193 #size-cells = <2>; 194 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 195 dma-coherent; 196 dma-ranges; 197 198 ti,sci-dev-id = <119>; 199 200 mcu_ringacc: ringacc@2b800000 { 201 compatible = "ti,am654-navss-ringacc"; 202 reg = <0x0 0x2b800000 0x0 0x400000>, 203 <0x0 0x2b000000 0x0 0x400000>, 204 <0x0 0x28590000 0x0 0x100>, 205 <0x0 0x2a500000 0x0 0x40000>, 206 <0x0 0x28440000 0x0 0x40000>; 207 reg-names = "rt", "fifos", "proxy_gcfg", 208 "proxy_target", "cfg"; 209 ti,num-rings = <286>; 210 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 211 ti,sci = <&dmsc>; 212 ti,sci-dev-id = <195>; 213 msi-parent = <&inta_main_udmass>; 214 }; 215 216 mcu_udmap: dma-controller@285c0000 { 217 compatible = "ti,am654-navss-mcu-udmap"; 218 reg = <0x0 0x285c0000 0x0 0x100>, 219 <0x0 0x2a800000 0x0 0x40000>, 220 <0x0 0x2aa00000 0x0 0x40000>, 221 <0x0 0x284a0000 0x0 0x4000>, 222 <0x0 0x284c0000 0x0 0x4000>, 223 <0x0 0x28400000 0x0 0x2000>; 224 reg-names = "gcfg", "rchanrt", "tchanrt", 225 "tchan", "rchan", "rflow"; 226 msi-parent = <&inta_main_udmass>; 227 #dma-cells = <1>; 228 229 ti,sci = <&dmsc>; 230 ti,sci-dev-id = <194>; 231 ti,ringacc = <&mcu_ringacc>; 232 233 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */ 234 <0xd>; /* TX_CHAN */ 235 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */ 236 <0xa>; /* RX_CHAN */ 237 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */ 238 }; 239 }; 240 241 secure_proxy_mcu: mailbox@2a480000 { 242 compatible = "ti,am654-secure-proxy"; 243 #mbox-cells = <1>; 244 reg-names = "target_data", "rt", "scfg"; 245 reg = <0x0 0x2a480000 0x0 0x80000>, 246 <0x0 0x2a380000 0x0 0x80000>, 247 <0x0 0x2a400000 0x0 0x80000>; 248 /* 249 * Marked Disabled: 250 * Node is incomplete as it is meant for bootloaders and 251 * firmware on non-MPU processors 252 */ 253 status = "disabled"; 254 }; 255 256 m_can0: can@40528000 { 257 compatible = "bosch,m_can"; 258 reg = <0x0 0x40528000 0x0 0x400>, 259 <0x0 0x40500000 0x0 0x4400>; 260 reg-names = "m_can", "message_ram"; 261 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 262 clocks = <&k3_clks 102 5>, <&k3_clks 102 0>; 263 clock-names = "hclk", "cclk"; 264 interrupt-parent = <&gic500>; 265 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 267 interrupt-names = "int0", "int1"; 268 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 269 status = "disabled"; 270 }; 271 272 m_can1: can@40568000 { 273 compatible = "bosch,m_can"; 274 reg = <0x0 0x40568000 0x0 0x400>, 275 <0x0 0x40540000 0x0 0x4400>; 276 reg-names = "m_can", "message_ram"; 277 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 278 clocks = <&k3_clks 103 5>, <&k3_clks 103 0>; 279 clock-names = "hclk", "cclk"; 280 interrupt-parent = <&gic500>; 281 interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>; 283 interrupt-names = "int0", "int1"; 284 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 285 status = "disabled"; 286 }; 287 288 fss: bus@47000000 { 289 compatible = "simple-bus"; 290 #address-cells = <2>; 291 #size-cells = <2>; 292 ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x100>, /* FSS Control */ 293 <0x0 0x47040000 0x0 0x47040000 0x0 0x100>, /* OSPI0 Control */ 294 <0x0 0x47050000 0x0 0x47050000 0x0 0x100>, /* OSPI1 Control */ 295 <0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>, /* FSS data region 1 */ 296 <0x4 0x00000000 0x4 0x00000000 0x4 0x00000000>; /* FSS data region 0/3 */ 297 298 ospi0: spi@47040000 { 299 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 300 reg = <0x0 0x47040000 0x0 0x100>, 301 <0x5 0x00000000 0x1 0x00000000>; 302 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>; 303 cdns,fifo-depth = <256>; 304 cdns,fifo-width = <4>; 305 cdns,trigger-address = <0x0>; 306 clocks = <&k3_clks 248 0>; 307 assigned-clocks = <&k3_clks 248 0>; 308 assigned-clock-parents = <&k3_clks 248 2>; 309 assigned-clock-rates = <166666666>; 310 power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 status = "disabled"; 314 }; 315 316 ospi1: spi@47050000 { 317 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 318 reg = <0x0 0x47050000 0x0 0x100>, 319 <0x7 0x00000000 0x1 0x00000000>; 320 interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 321 cdns,fifo-depth = <256>; 322 cdns,fifo-width = <4>; 323 cdns,trigger-address = <0x0>; 324 clocks = <&k3_clks 249 6>; 325 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 status = "disabled"; 329 }; 330 }; 331 332 mcu_cpsw: ethernet@46000000 { 333 compatible = "ti,am654-cpsw-nuss"; 334 #address-cells = <2>; 335 #size-cells = <2>; 336 reg = <0x0 0x46000000 0x0 0x200000>; 337 reg-names = "cpsw_nuss"; 338 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; 339 dma-coherent; 340 clocks = <&k3_clks 5 10>; 341 clock-names = "fck"; 342 power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>; 343 344 dmas = <&mcu_udmap 0xf000>, 345 <&mcu_udmap 0xf001>, 346 <&mcu_udmap 0xf002>, 347 <&mcu_udmap 0xf003>, 348 <&mcu_udmap 0xf004>, 349 <&mcu_udmap 0xf005>, 350 <&mcu_udmap 0xf006>, 351 <&mcu_udmap 0xf007>, 352 <&mcu_udmap 0x7000>; 353 dma-names = "tx0", "tx1", "tx2", "tx3", 354 "tx4", "tx5", "tx6", "tx7", 355 "rx"; 356 357 ethernet-ports { 358 #address-cells = <1>; 359 #size-cells = <0>; 360 361 cpsw_port1: port@1 { 362 reg = <1>; 363 ti,mac-only; 364 label = "port1"; 365 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; 366 phys = <&phy_gmii_sel 1>; 367 }; 368 }; 369 370 davinci_mdio: mdio@f00 { 371 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 372 reg = <0x0 0xf00 0x0 0x100>; 373 #address-cells = <1>; 374 #size-cells = <0>; 375 clocks = <&k3_clks 5 10>; 376 clock-names = "fck"; 377 bus_freq = <1000000>; 378 status = "disabled"; 379 }; 380 381 cpts@3d000 { 382 compatible = "ti,am65-cpts"; 383 reg = <0x0 0x3d000 0x0 0x400>; 384 clocks = <&mcu_cpsw_cpts_mux>; 385 clock-names = "cpts"; 386 interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>; 387 interrupt-names = "cpts"; 388 ti,cpts-ext-ts-inputs = <4>; 389 ti,cpts-periodic-outputs = <2>; 390 391 mcu_cpsw_cpts_mux: refclk-mux { 392 #clock-cells = <0>; 393 clocks = <&k3_clks 118 5>, <&k3_clks 118 11>, 394 <&k3_clks 118 6>, <&k3_clks 118 3>, 395 <&k3_clks 118 8>, <&k3_clks 118 14>, 396 <&k3_clks 120 3>, <&k3_clks 121 3>; 397 assigned-clocks = <&mcu_cpsw_cpts_mux>; 398 assigned-clock-parents = <&k3_clks 118 5>; 399 }; 400 }; 401 }; 402 403 mcu_r5fss0: r5fss@41000000 { 404 compatible = "ti,am654-r5fss"; 405 ti,cluster-mode = <1>; 406 #address-cells = <1>; 407 #size-cells = <1>; 408 ranges = <0x41000000 0x00 0x41000000 0x20000>, 409 <0x41400000 0x00 0x41400000 0x20000>; 410 power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>; 411 412 mcu_r5fss0_core0: r5f@41000000 { 413 compatible = "ti,am654-r5f"; 414 reg = <0x41000000 0x00008000>, 415 <0x41010000 0x00008000>; 416 reg-names = "atcm", "btcm"; 417 ti,sci = <&dmsc>; 418 ti,sci-dev-id = <159>; 419 ti,sci-proc-ids = <0x01 0xff>; 420 resets = <&k3_reset 159 1>; 421 firmware-name = "am65x-mcu-r5f0_0-fw"; 422 ti,atcm-enable = <1>; 423 ti,btcm-enable = <1>; 424 ti,loczrama = <1>; 425 }; 426 427 mcu_r5fss0_core1: r5f@41400000 { 428 compatible = "ti,am654-r5f"; 429 reg = <0x41400000 0x00008000>, 430 <0x41410000 0x00008000>; 431 reg-names = "atcm", "btcm"; 432 ti,sci = <&dmsc>; 433 ti,sci-dev-id = <245>; 434 ti,sci-proc-ids = <0x02 0xff>; 435 resets = <&k3_reset 245 1>; 436 firmware-name = "am65x-mcu-r5f0_1-fw"; 437 ti,atcm-enable = <1>; 438 ti,btcm-enable = <1>; 439 ti,loczrama = <1>; 440 }; 441 }; 442 443 mcu_esm: esm@40800000 { 444 compatible = "ti,j721e-esm"; 445 reg = <0x00 0x40800000 0x00 0x1000>; 446 bootph-pre-ram; 447 /* Interrupt sources: mrti0, mrti1 */ 448 ti,esm-pins = <104>, <105>; 449 }; 450 451 mcu_rti1: watchdog@40610000 { 452 compatible = "ti,j7-rti-wdt"; 453 reg = <0x0 0x40610000 0x0 0x100>; 454 clocks = <&k3_clks 135 0>; 455 power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>; 456 assigned-clocks = <&k3_clks 135 0>; 457 assigned-clock-parents = <&k3_clks 135 4>; 458 }; 459}; 460