1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2023 Josua Mayer <josua@solid-run.com> 4 * 5 */ 6 7#include <dt-bindings/net/ti-dp83869.h> 8 9/ { 10 model = "SolidRun AM642 SoM"; 11 compatible = "solidrun,am642-sr-som", "ti,am642"; 12 13 aliases { 14 ethernet0 = &cpsw_port1; 15 ethernet1 = &icssg1_emac0; 16 ethernet2 = &icssg1_emac1; 17 mmc0 = &sdhci0; 18 mmc1 = &sdhci1; 19 serial2 = &main_uart0; 20 }; 21 22 chosen { 23 /* SoC default UART console */ 24 stdout-path = "serial2:115200n8"; 25 }; 26 27 /* PRU Ethernet Controller */ 28 ethernet { 29 compatible = "ti,am642-icssg-prueth"; 30 pinctrl-names = "default"; 31 pinctrl-0 = <&pru_rgmii1_default_pins>, <&pru_rgmii2_default_pins>; 32 33 sram = <&oc_sram>; 34 ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>; 35 firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", 36 "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", 37 "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", 38 "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", 39 "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", 40 "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; 41 42 /* configure internal pinmux for mii mode */ 43 ti,pruss-gp-mux-sel = <2>, <2>, <2>, <2>, <2>, <2>; 44 45 ti,mii-g-rt = <&icssg1_mii_g_rt>; 46 ti,mii-rt = <&icssg1_mii_rt>; 47 ti,iep = <&icssg1_iep0>, <&icssg1_iep1>; 48 49 /* 50 * Configure icssg interrupt controller to map pru-internal 51 * interrupts 8/9 via channels 0/1 to host interrupts 0/1. 52 * 53 * For details see interrupt controller documentation: 54 * Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml 55 */ 56 interrupt-parent = <&icssg1_intc>; 57 interrupts = <24 0 2>, <25 1 3>; 58 interrupt-names = "tx_ts0", "tx_ts1"; 59 60 dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */ 61 <&main_pktdma 0xc201 15>, /* egress slice 0 */ 62 <&main_pktdma 0xc202 15>, /* egress slice 0 */ 63 <&main_pktdma 0xc203 15>, /* egress slice 0 */ 64 <&main_pktdma 0xc204 15>, /* egress slice 1 */ 65 <&main_pktdma 0xc205 15>, /* egress slice 1 */ 66 <&main_pktdma 0xc206 15>, /* egress slice 1 */ 67 <&main_pktdma 0xc207 15>, /* egress slice 1 */ 68 <&main_pktdma 0x4200 15>, /* ingress slice 0 */ 69 <&main_pktdma 0x4201 15>; /* ingress slice 1 */ 70 dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", 71 "tx1-0", "tx1-1", "tx1-2", "tx1-3", 72 "rx0", "rx1"; 73 74 ethernet-ports { 75 #address-cells = <1>; 76 #size-cells = <0>; 77 78 icssg1_emac0: port@0 { 79 reg = <0>; 80 ti,syscon-rgmii-delay = <&main_conf 0x4110>; 81 /* Filled in by bootloader */ 82 local-mac-address = [00 00 00 00 00 00]; 83 phy-handle = <ðernet_phy2>; 84 phy-mode = "rgmii-id"; 85 }; 86 87 icssg1_emac1: port@1 { 88 reg = <1>; 89 ti,syscon-rgmii-delay = <&main_conf 0x4114>; 90 /* Filled in by bootloader */ 91 local-mac-address = [00 00 00 00 00 00]; 92 phy-handle = <ðernet_phy1>; 93 phy-mode = "rgmii-id"; 94 }; 95 }; 96 }; 97 98 /* DDR16SS0: 99 * - Bank 1 @ 0x080000000-0x0FFFFFFFF: max. 2GB in 32-bit address space 100 * - Bank 2 @ 0x880000000-0x9FFFFFFFF: max. 6GB in 64-bit address space 101 */ 102 memory@80000000 { 103 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 104 <0x00000008 0x80000000 0x00000001 0x80000000>; 105 device_type = "memory"; 106 }; 107 108 reserved-memory { 109 #address-cells = <2>; 110 #size-cells = <2>; 111 ranges; 112 113 secure_ddr: optee@9e800000 { 114 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ 115 no-map; 116 }; 117 118 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 119 compatible = "shared-dma-pool"; 120 reg = <0x00 0xa0000000 0x00 0x100000>; 121 no-map; 122 }; 123 124 main_r5fss0_core0_memory_region: r5f-memory@a0100000 { 125 compatible = "shared-dma-pool"; 126 reg = <0x00 0xa0100000 0x00 0xf00000>; 127 no-map; 128 }; 129 130 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 131 compatible = "shared-dma-pool"; 132 reg = <0x00 0xa1000000 0x00 0x100000>; 133 no-map; 134 }; 135 136 main_r5fss0_core1_memory_region: r5f-memory@a1100000 { 137 compatible = "shared-dma-pool"; 138 reg = <0x00 0xa1100000 0x00 0xf00000>; 139 no-map; 140 }; 141 142 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { 143 compatible = "shared-dma-pool"; 144 reg = <0x00 0xa2000000 0x00 0x100000>; 145 no-map; 146 }; 147 148 main_r5fss1_core0_memory_region: r5f-memory@a2100000 { 149 compatible = "shared-dma-pool"; 150 reg = <0x00 0xa2100000 0x00 0xf00000>; 151 no-map; 152 }; 153 154 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { 155 compatible = "shared-dma-pool"; 156 reg = <0x00 0xa3000000 0x00 0x100000>; 157 no-map; 158 }; 159 160 main_r5fss1_core1_memory_region: r5f-memory@a3100000 { 161 compatible = "shared-dma-pool"; 162 reg = <0x00 0xa3100000 0x00 0xf00000>; 163 no-map; 164 }; 165 }; 166 167 vdd_mmc0: regulator-vdd-mmc0 { 168 compatible = "regulator-fixed"; 169 regulator-name = "vdd-mmc0"; 170 regulator-min-microvolt = <1800000>; 171 regulator-max-microvolt = <1800000>; 172 regulator-always-on; 173 regulator-boot-on; 174 }; 175}; 176 177&cpsw3g { 178 pinctrl-names = "default"; 179 pinctrl-0 = <&rgmii1_default_pins>; 180}; 181 182&cpsw3g_mdio { 183 pinctrl-names = "default"; 184 pinctrl-0 = <&mdio0_default_pins>; 185 status = "okay"; 186 187 ethernet_phy0: ethernet-phy@0 { 188 compatible = "ethernet-phy-id2000.a0f1"; 189 reg = <0>; 190 pinctrl-names = "default"; 191 pinctrl-0 = <ðernet_phy0_default_pins>; 192 ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>; 193 ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>; 194 /* 195 * Disable interrupts because ISR never clears 0x0040 196 * 197 * interrupt-parent = <&main_gpio1>; 198 * interrupts = <70 IRQ_TYPE_LEVEL_LOW>; 199 */ 200 /* 201 * Disable HW Reset because clock signal is daisy-chained 202 * 203 * reset-gpios = <&main_gpio0 84 GPIO_ACTIVE_LOW>; 204 * reset-assert-us = <1>; 205 * reset-deassert-us = <30>; 206 */ 207 }; 208}; 209 210&cpsw_port1 { 211 phy-mode = "rgmii-id"; 212 phy-handle = <ðernet_phy0>; 213}; 214 215&cpsw_port2 { 216 status = "disabled"; 217}; 218 219&icssg1_mdio { 220 pinctrl-names = "default"; 221 pinctrl-0 = <&pru1_mdio0_default_pins>; 222 status = "okay"; 223 224 ethernet_phy1: ethernet-phy@3 { 225 compatible = "ethernet-phy-id2000.a0f1"; 226 reg = <3>; 227 pinctrl-names = "default"; 228 pinctrl-0 = <ðernet_phy1_default_pins>; 229 ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>; 230 ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>; 231 /* 232 * Disable interrupts because ISR never clears 0x0040 233 * 234 * interrupt-parent = <&main_gpio1>; 235 * interrupts = <70 IRQ_TYPE_LEVEL_LOW>; 236 */ 237 /* 238 * Disable HW Reset because clock signal is daisy-chained 239 * 240 * reset-gpios = <&main_gpio0 20 GPIO_ACTIVE_LOW>; 241 * reset-assert-us = <1>; 242 * reset-deassert-us = <30>; 243 */ 244 }; 245 246 ethernet_phy2: ethernet-phy@f { 247 compatible = "ethernet-phy-id2000.a0f1"; 248 reg = <0xf>; 249 pinctrl-names = "default"; 250 pinctrl-0 = <ðernet_phy2_default_pins>; 251 ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>; 252 /* 253 * Disable interrupts because ISR never clears 0x0040 254 * 255 * interrupt-parent = <&main_gpio1>; 256 * interrupts = <70 IRQ_TYPE_LEVEL_LOW>; 257 */ 258 /* 259 * Disable HW Reset because clock signal is daisy-chained 260 * 261 * reset-gpios = <&main_gpio0 52 GPIO_ACTIVE_LOW>; 262 * reset-assert-us = <1>; 263 * reset-deassert-us = <30>; 264 */ 265 }; 266}; 267 268&mailbox0_cluster2 { 269 status = "okay"; 270 271 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 272 ti,mbox-rx = <0 0 2>; 273 ti,mbox-tx = <1 0 2>; 274 }; 275 276 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 277 ti,mbox-rx = <2 0 2>; 278 ti,mbox-tx = <3 0 2>; 279 }; 280}; 281 282&mailbox0_cluster4 { 283 status = "okay"; 284 285 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 286 ti,mbox-rx = <0 0 2>; 287 ti,mbox-tx = <1 0 2>; 288 }; 289 290 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 291 ti,mbox-rx = <2 0 2>; 292 ti,mbox-tx = <3 0 2>; 293 }; 294}; 295 296&main_i2c0 { 297 pinctrl-names = "default"; 298 pinctrl-0 = <&main_i2c0_default_pins>; 299 status = "okay"; 300 301 som_eeprom: eeprom@50 { 302 compatible = "atmel,24c01"; 303 reg = <0x50>; 304 pagesize = <8>; 305 }; 306}; 307 308&main_pmx0 { 309 /* hog global functions */ 310 pinctrl-names = "default"; 311 pinctrl-0 = <ðernet_phy_default_pins>; 312 313 ethernet_phy_default_pins: ethernet-phy-default-pins { 314 pinctrl-single,pins = < 315 /* interrupt / power-down, external pull-up on SoM */ 316 AM64X_IOPAD(0x0278, PIN_INPUT, 7) /* EXTINTn.GPIO1_70 */ 317 >; 318 }; 319 320 ethernet_phy0_default_pins: ethernet-phy0-default-pins { 321 pinctrl-single,pins = < 322 /* reset */ 323 AM64X_IOPAD(0x0154, PIN_OUTPUT, 7) /* PRG1_PRU1_GPO19.GPIO0_84 */ 324 /* reference clock */ 325 AM64X_IOPAD(0x0274, PIN_OUTPUT, 5) /* EXT_REFCLK1.CLKOUT0 */ 326 >; 327 }; 328 329 ethernet_phy1_default_pins: ethernet-phy1-default-pins { 330 pinctrl-single,pins = < 331 /* reset */ 332 AM64X_IOPAD(0x0150, PIN_OUTPUT, 7) /* PRG1_PRU1_GPO18.GPIO0_20 */ 333 /* led0, external pull-down on SoM */ 334 AM64X_IOPAD(0x0128, PIN_INPUT, 7) /* PRG1_PRU1_GPO8.GPIO0_73 */ 335 /* led1/rxer */ 336 AM64X_IOPAD(0x011c, PIN_INPUT, 7) /* PRG1_PRU1_GPO5.GPIO0_70 */ 337 >; 338 }; 339 340 ethernet_phy2_default_pins: ethernet-phy2-default-pins { 341 pinctrl-single,pins = < 342 /* reset */ 343 AM64X_IOPAD(0x00d4, PIN_OUTPUT, 7) /* PRG1_PRU0_GPO7.GPIO0_52 */ 344 /* led0, external pull-down on SoM */ 345 AM64X_IOPAD(0x00d8, PIN_INPUT, 7) /* PRG1_PRU0_GPO8.GPIO0_53 */ 346 /* led1/rxer */ 347 AM64X_IOPAD(0x00cc, PIN_INPUT, 7) /* PRG1_PRU0_GPO5.GPIO0_50 */ 348 >; 349 }; 350 351 main_i2c0_default_pins: main-i2c0-default-pins { 352 pinctrl-single,pins = < 353 /* external pull-up on SoM */ 354 AM64X_IOPAD(0x0260, PIN_INPUT, 0) /* I2C0_SCL.I2C0_SCL */ 355 AM64X_IOPAD(0x0264, PIN_INPUT, 0) /* I2C0_SDA.I2C0_SDA */ 356 >; 357 }; 358 359 /* 360 * main_mmc0_default_pins: main-mmc0-default-pins 361 * 362 * MMC0_CMD: no padconfig 363 * MMC0_CLK: no padconfig, external pull-up on SoM 364 * MMC0_DAT0: no padconfig 365 * MMC0_DAT1: no padconfig 366 * MMC0_DAT2: no padconfig 367 * MMC0_DAT3: no padconfig 368 * MMC0_DAT4: no padconfig 369 * MMC0_DAT5: no padconfig 370 * MMC0_DAT6: no padconfig 371 * MMC0_DAT7: no padconfig 372 * MMC0_DS: no padconfig, external pull-down on SoM 373 */ 374 375 main_mmc1_default_pins: main-mmc1-default-pins { 376 pinctrl-single,pins = < 377 AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ 378 AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* MMC1_CLK.MMC1_CLK */ 379 AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* MMC1_DAT0.MMC1_DAT0 */ 380 AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* MMC1_DAT1.MMC1_DAT1 */ 381 AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* MMC1_DAT2.MMC1_DAT2 */ 382 AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* MMC1_DAT3.MMC1_DAT3 */ 383 /* external pull-down on SoM & Carrier */ 384 AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* MMC1_SDCD.MMC1_SDCD */ 385 AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB: clock loopback */ 386 >; 387 }; 388 389 main_uart0_default_pins: main-uart0-default-pins { 390 pinctrl-single,pins = < 391 AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* UART0_RXD.UART0_RXD */ 392 AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* UART0_TXD.UART0_TXD */ 393 >; 394 }; 395 396 mdio0_default_pins: mdio0-default-pins { 397 pinctrl-single,pins = < 398 AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* PRG0_PRU1_GPO19.MDIO0_MDC */ 399 AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* PRG0_PRU1_GPO18.MDIO0_MDIO */ 400 >; 401 }; 402 403 ospi0_default_pins: ospi0-default-pins { 404 pinctrl-single,pins = < 405 /* external pull-down on SoM */ 406 AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* OSPI0_CLK.OSPI0_CLK */ 407 AM64X_IOPAD(0x0008, PIN_OUTPUT, 0) /* OSPI0_DQS.OSPI0_DQS */ 408 /* external pull-up on SoM */ 409 AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* OSPI0_CSn0.OSPI0_CSn0 */ 410 AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* OSPI0_D0.OSPI0_D0 */ 411 AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* OSPI0_D1.OSPI0_D1 */ 412 AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* OSPI0_D2.OSPI0_D2 */ 413 AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* OSPI0_D3.OSPI0_D3 */ 414 AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* OSPI0_D4.OSPI0_D4 */ 415 AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* OSPI0_D5.OSPI0_D5 */ 416 AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* OSPI0_D6.OSPI0_D6 */ 417 AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* OSPI0_D7.OSPI0_D7 */ 418 >; 419 }; 420 421 ospi0_flash0_default_pins: ospi0-flash0-default-pins { 422 pinctrl-single,pins = < 423 AM64X_IOPAD(0x0034, PIN_OUTPUT, 7) /* OSPI0_CSn2.GPIO0_13 */ 424 AM64X_IOPAD(0x0038, PIN_INPUT, 7) /* OSPI0_CSn3.GPIO0_14 */ 425 >; 426 }; 427 428 pru1_mdio0_default_pins: pru1-mdio0-default-pins { 429 pinctrl-single,pins = < 430 AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* PRG1_MDIO0_MDC.PRG1_MDIO0_MDC */ 431 AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* PRG1_MDIO0_MDIO.PRG1_MDIO0_MDIO */ 432 >; 433 }; 434 435 pru_rgmii1_default_pins: pru-rgmii1-default-pins { 436 pinctrl-single,pins = < 437 AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */ 438 AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */ 439 AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */ 440 AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */ 441 AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */ 442 AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */ 443 AM64X_IOPAD(0x00e4, PIN_OUTPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */ 444 AM64X_IOPAD(0x00e8, PIN_OUTPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */ 445 AM64X_IOPAD(0x00ec, PIN_OUTPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */ 446 AM64X_IOPAD(0x00f0, PIN_OUTPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */ 447 AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */ 448 AM64X_IOPAD(0x00f4, PIN_OUTPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */ 449 >; 450 }; 451 452 pru_rgmii2_default_pins: pru-rgmii2-default-pins { 453 pinctrl-single,pins = < 454 AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* PRG1_PRU1_GPO0.RGMII2_RD0 */ 455 AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* PRG1_PRU1_GPO1.RGMII2_RD1 */ 456 AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* PRG1_PRU1_GPO2.RGMII2_RD2 */ 457 AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* PRG1_PRU1_GPO3.RGMII2_RD3 */ 458 AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* PRG1_PRU1_GPO6.RGMII2_RXC */ 459 AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* PRG1_PRU1_GPO4.RGMII2_RX_CTL */ 460 AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO11.RGMII2_TD0 */ 461 AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO12.RGMII2_TD1 */ 462 AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO13.RGMII2_TD2 */ 463 AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO14.RGMII2_TD3 */ 464 AM64X_IOPAD(0x0148, PIN_INPUT, 2) /* PRG1_PRU1_GPO16.RGMII2_TXC */ 465 AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO15.RGMII2_TX_CTL */ 466 >; 467 }; 468 469 rgmii1_default_pins: rgmii1-default-pins { 470 pinctrl-single,pins = < 471 AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* PRG0_PRU1_GPO7.RGMII1_RD0 */ 472 AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* PRG0_PRU1_GPO9.RGMII1_RD1 */ 473 AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* PRG0_PRU1_GPO10.RGMII1_RD2 */ 474 AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* PRG0_PRU1_GPO17.RGMII1_RD3 */ 475 AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* PRG0_PRU0_GPO10.RGMII1_RXC */ 476 AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* PRG0_PRU0_GPO9.RGMII1_RX_CTL */ 477 AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO7.RGMII1_TD0 */ 478 AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO9.RGMII1_TD1 */ 479 AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO10.RGMII1_TD2 */ 480 AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO17.RGMII1_TD3 */ 481 AM64X_IOPAD(0x00e0, PIN_INPUT, 4) /* PRG1_PRU0_GPO10.RGMII1_TXC */ 482 AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* PRG1_PRU0_GPO9.RGMII1_TX_CTL */ 483 >; 484 }; 485 486 usb0_default_pins: usb0-default-pins { 487 pinctrl-single,pins = < 488 AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* USB0_DRVVBUS.USB0_DRVVBUS */ 489 >; 490 }; 491}; 492 493&main_r5fss0_core0 { 494 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; 495 memory-region = <&main_r5fss0_core0_dma_memory_region>, 496 <&main_r5fss0_core0_memory_region>; 497}; 498 499&main_r5fss0_core1 { 500 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; 501 memory-region = <&main_r5fss0_core1_dma_memory_region>, 502 <&main_r5fss0_core1_memory_region>; 503}; 504 505&main_r5fss1_core0 { 506 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; 507 memory-region = <&main_r5fss1_core0_dma_memory_region>, 508 <&main_r5fss1_core0_memory_region>; 509}; 510 511&main_r5fss1_core1 { 512 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; 513 memory-region = <&main_r5fss1_core1_dma_memory_region>, 514 <&main_r5fss1_core1_memory_region>; 515}; 516 517/* SoC default UART console */ 518&main_uart0 { 519 pinctrl-names = "default"; 520 pinctrl-0 = <&main_uart0_default_pins>; 521 status = "okay"; 522}; 523 524&ospi0 { 525 pinctrl-names = "default"; 526 pinctrl-0 = <&ospi0_default_pins>; 527 num-cs = <1>; 528 status = "okay"; 529 530 flash@0 { 531 compatible = "jedec,spi-nor"; 532 reg = <0>; 533 pinctrl-names = "default"; 534 pinctrl-0 = <&ospi0_flash0_default_pins>; 535 spi-tx-bus-width = <8>; 536 spi-rx-bus-width = <8>; 537 spi-max-frequency = <200000000>; 538 cdns,tshsl-ns = <50>; 539 cdns,tsd2d-ns = <50>; 540 cdns,tchsh-ns = <4>; 541 cdns,tslch-ns = <4>; 542 cdns,read-delay = <0>; 543 interrupt-parent = <&main_gpio0>; 544 interrupts = <14 IRQ_TYPE_LEVEL_LOW>; 545 reset-gpios = <&main_gpio0 13 GPIO_ACTIVE_LOW>; 546 }; 547}; 548 549&sdhci0 { 550 /* mmc0 pins have no padconfig */ 551 bus-width = <8>; 552 ti,driver-strength-ohm = <50>; 553 disable-wp; 554 non-removable; 555 cap-mmc-hw-reset; 556 no-sd; 557 /* 558 * MMC controller supports switching between 1.8V and 3.3V signalling. 559 * However MMC0 (unlike MMC1) does not integrate an LDO. 560 * Explicitly link a regulator node for indicating to the driver which 561 * voltages are actually usable. 562 */ 563 vqmmc-supply = <&vdd_mmc0>; 564 status = "okay"; 565}; 566 567/* 568 * microSD is on carrier - however since SoC can boot from it, 569 * configure it just in case. 570 */ 571&sdhci1 { 572 pinctrl-names = "default"; 573 pinctrl-0 = <&main_mmc1_default_pins>; 574 bus-width = <4>; 575 ti,driver-strength-ohm = <50>; 576 disable-wp; 577 status = "okay"; 578}; 579 580/* 581 * USB settings are a carrier choice - however since SoC can boot from it, 582 * configure as USB-2.0 OTG here, keeping USB-3 serdes disabled. 583 */ 584&usb0 { 585 pinctrl-names = "default"; 586 pinctrl-0 = <&usb0_default_pins>; 587 dr_mode = "otg"; 588 maximum-speed = "high-speed"; 589}; 590 591&usbss0 { 592 ti,vbus-divider; 593 ti,usb2-only; 594}; 595