1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/phy/phy.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/net/ti-dp83867.h> 11#include <dt-bindings/leds/common.h> 12#include "k3-am642.dtsi" 13 14#include "k3-serdes.h" 15 16/ { 17 compatible = "ti,am642-sk", "ti,am642"; 18 model = "Texas Instruments AM642 SK"; 19 20 chosen { 21 stdout-path = &main_uart0; 22 }; 23 24 aliases { 25 serial0 = &mcu_uart0; 26 serial1 = &main_uart1; 27 serial2 = &main_uart0; 28 i2c0 = &main_i2c0; 29 i2c1 = &main_i2c1; 30 mmc0 = &sdhci0; 31 mmc1 = &sdhci1; 32 ethernet0 = &cpsw_port1; 33 ethernet1 = &cpsw_port2; 34 }; 35 36 memory@80000000 { 37 bootph-pre-ram; 38 device_type = "memory"; 39 /* 2G RAM */ 40 reg = <0x00000000 0x80000000 0x00000000 0x80000000>; 41 }; 42 43 reserved-memory { 44 #address-cells = <2>; 45 #size-cells = <2>; 46 ranges; 47 48 secure_ddr: optee@9e800000 { 49 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ 50 alignment = <0x1000>; 51 no-map; 52 }; 53 54 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 55 compatible = "shared-dma-pool"; 56 reg = <0x00 0xa0000000 0x00 0x100000>; 57 no-map; 58 }; 59 60 main_r5fss0_core0_memory_region: r5f-memory@a0100000 { 61 compatible = "shared-dma-pool"; 62 reg = <0x00 0xa0100000 0x00 0xf00000>; 63 no-map; 64 }; 65 66 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 67 compatible = "shared-dma-pool"; 68 reg = <0x00 0xa1000000 0x00 0x100000>; 69 no-map; 70 }; 71 72 main_r5fss0_core1_memory_region: r5f-memory@a1100000 { 73 compatible = "shared-dma-pool"; 74 reg = <0x00 0xa1100000 0x00 0xf00000>; 75 no-map; 76 }; 77 78 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { 79 compatible = "shared-dma-pool"; 80 reg = <0x00 0xa2000000 0x00 0x100000>; 81 no-map; 82 }; 83 84 main_r5fss1_core0_memory_region: r5f-memory@a2100000 { 85 compatible = "shared-dma-pool"; 86 reg = <0x00 0xa2100000 0x00 0xf00000>; 87 no-map; 88 }; 89 90 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { 91 compatible = "shared-dma-pool"; 92 reg = <0x00 0xa3000000 0x00 0x100000>; 93 no-map; 94 }; 95 96 main_r5fss1_core1_memory_region: r5f-memory@a3100000 { 97 compatible = "shared-dma-pool"; 98 reg = <0x00 0xa3100000 0x00 0xf00000>; 99 no-map; 100 }; 101 102 mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 { 103 compatible = "shared-dma-pool"; 104 reg = <0x00 0xa4000000 0x00 0x100000>; 105 no-map; 106 }; 107 108 mcu_m4fss_memory_region: m4f-memory@a4100000 { 109 compatible = "shared-dma-pool"; 110 reg = <0x00 0xa4100000 0x00 0xf00000>; 111 no-map; 112 }; 113 114 rtos_ipc_memory_region: ipc-memories@a5000000 { 115 reg = <0x00 0xa5000000 0x00 0x00800000>; 116 alignment = <0x1000>; 117 no-map; 118 }; 119 }; 120 121 vusb_main: regulator-0 { 122 /* USB MAIN INPUT 5V DC */ 123 bootph-all; 124 compatible = "regulator-fixed"; 125 regulator-name = "vusb_main5v0"; 126 regulator-min-microvolt = <5000000>; 127 regulator-max-microvolt = <5000000>; 128 regulator-always-on; 129 regulator-boot-on; 130 }; 131 132 vcc_3v3_sys: regulator-1 { 133 /* output of LP8733xx */ 134 bootph-all; 135 compatible = "regulator-fixed"; 136 regulator-name = "vcc_3v3_sys"; 137 regulator-min-microvolt = <3300000>; 138 regulator-max-microvolt = <3300000>; 139 vin-supply = <&vusb_main>; 140 regulator-always-on; 141 regulator-boot-on; 142 }; 143 144 vdd_mmc1: regulator-2 { 145 /* TPS2051BD */ 146 bootph-all; 147 compatible = "regulator-fixed"; 148 regulator-name = "vdd_mmc1"; 149 regulator-min-microvolt = <3300000>; 150 regulator-max-microvolt = <3300000>; 151 regulator-boot-on; 152 enable-active-high; 153 vin-supply = <&vcc_3v3_sys>; 154 gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; 155 }; 156 157 com8_ls_en: regulator-3 { 158 compatible = "regulator-fixed"; 159 regulator-name = "com8_ls_en"; 160 regulator-min-microvolt = <3300000>; 161 regulator-max-microvolt = <3300000>; 162 regulator-always-on; 163 regulator-boot-on; 164 pinctrl-0 = <&main_com8_ls_en_pins_default>; 165 pinctrl-names = "default"; 166 gpio = <&main_gpio0 62 GPIO_ACTIVE_LOW>; 167 }; 168 169 wlan_en: regulator-4 { 170 /* output of SN74AVC4T245RSVR */ 171 compatible = "regulator-fixed"; 172 regulator-name = "wlan_en"; 173 regulator-min-microvolt = <1800000>; 174 regulator-max-microvolt = <1800000>; 175 enable-active-high; 176 pinctrl-0 = <&main_wlan_en_pins_default>; 177 pinctrl-names = "default"; 178 vin-supply = <&com8_ls_en>; 179 gpio = <&main_gpio0 48 GPIO_ACTIVE_HIGH>; 180 }; 181 182 led-controller { 183 compatible = "gpio-leds"; 184 185 led-0 { 186 color = <LED_COLOR_ID_GREEN>; 187 function = LED_FUNCTION_INDICATOR; 188 function-enumerator = <1>; 189 gpios = <&exp2 0 GPIO_ACTIVE_HIGH>; 190 default-state = "off"; 191 }; 192 193 led-1 { 194 color = <LED_COLOR_ID_RED>; 195 function = LED_FUNCTION_INDICATOR; 196 function-enumerator = <2>; 197 gpios = <&exp2 1 GPIO_ACTIVE_HIGH>; 198 default-state = "off"; 199 }; 200 201 led-2 { 202 color = <LED_COLOR_ID_GREEN>; 203 function = LED_FUNCTION_INDICATOR; 204 function-enumerator = <3>; 205 gpios = <&exp2 2 GPIO_ACTIVE_HIGH>; 206 default-state = "off"; 207 }; 208 209 led-3 { 210 color = <LED_COLOR_ID_AMBER>; 211 function = LED_FUNCTION_INDICATOR; 212 function-enumerator = <4>; 213 gpios = <&exp2 3 GPIO_ACTIVE_HIGH>; 214 default-state = "off"; 215 }; 216 217 led-4 { 218 color = <LED_COLOR_ID_GREEN>; 219 function = LED_FUNCTION_INDICATOR; 220 function-enumerator = <5>; 221 gpios = <&exp2 4 GPIO_ACTIVE_HIGH>; 222 default-state = "off"; 223 }; 224 225 led-5 { 226 color = <LED_COLOR_ID_RED>; 227 function = LED_FUNCTION_INDICATOR; 228 function-enumerator = <6>; 229 gpios = <&exp2 5 GPIO_ACTIVE_HIGH>; 230 default-state = "off"; 231 }; 232 233 led-6 { 234 color = <LED_COLOR_ID_GREEN>; 235 function = LED_FUNCTION_INDICATOR; 236 function-enumerator = <7>; 237 gpios = <&exp2 6 GPIO_ACTIVE_HIGH>; 238 default-state = "off"; 239 }; 240 241 led-7 { 242 color = <LED_COLOR_ID_AMBER>; 243 function = LED_FUNCTION_HEARTBEAT; 244 function-enumerator = <8>; 245 linux,default-trigger = "heartbeat"; 246 gpios = <&exp2 7 GPIO_ACTIVE_HIGH>; 247 }; 248 }; 249}; 250 251&main_pmx0 { 252 main_mmc1_pins_default: main-mmc1-default-pins { 253 bootph-all; 254 pinctrl-single,pins = < 255 AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */ 256 AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ 257 AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ 258 AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */ 259 AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */ 260 AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */ 261 AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */ 262 AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */ 263 AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */ 264 >; 265 }; 266 267 main_uart0_pins_default: main-uart0-default-pins { 268 bootph-all; 269 pinctrl-single,pins = < 270 AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ 271 AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ 272 AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ 273 AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ 274 >; 275 }; 276 277 main_uart1_pins_default: main-uart1-default-pins { 278 bootph-pre-ram; 279 pinctrl-single,pins = < 280 AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */ 281 AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ 282 AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */ 283 AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */ 284 >; 285 }; 286 287 main_usb0_pins_default: main-usb0-default-pins { 288 bootph-all; 289 pinctrl-single,pins = < 290 AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ 291 >; 292 }; 293 294 main_i2c0_pins_default: main-i2c0-default-pins { 295 bootph-all; 296 pinctrl-single,pins = < 297 AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ 298 AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ 299 >; 300 }; 301 302 main_i2c1_pins_default: main-i2c1-default-pins { 303 bootph-all; 304 pinctrl-single,pins = < 305 AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ 306 AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ 307 >; 308 }; 309 310 mdio1_pins_default: mdio1-default-pins { 311 pinctrl-single,pins = < 312 AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ 313 AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ 314 >; 315 }; 316 317 rgmii1_pins_default: rgmii1-default-pins { 318 pinctrl-single,pins = < 319 AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */ 320 AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */ 321 AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */ 322 AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */ 323 AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */ 324 AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */ 325 AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */ 326 AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */ 327 AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */ 328 AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ 329 AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */ 330 AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ 331 >; 332 }; 333 334 rgmii2_pins_default: rgmii2-default-pins { 335 pinctrl-single,pins = < 336 AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ 337 AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ 338 AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ 339 AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ 340 AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ 341 AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ 342 AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ 343 AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ 344 AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ 345 AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ 346 AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ 347 AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ 348 >; 349 }; 350 351 ospi0_pins_default: ospi0-default-pins { 352 pinctrl-single,pins = < 353 AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ 354 AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ 355 AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */ 356 AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */ 357 AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */ 358 AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */ 359 AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */ 360 AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */ 361 AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */ 362 AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ 363 AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ 364 >; 365 }; 366 367 main_ecap0_pins_default: main-ecap0-default-pins { 368 pinctrl-single,pins = < 369 AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ 370 >; 371 }; 372 373 main_eqep0_pins_default: main-eqep0-default-pins { 374 pinctrl-single,pins = < 375 AM64X_IOPAD(0x00a0, PIN_INPUT, 3) /* (N16) GPMC0_WPn.EQEP0_A */ 376 AM64X_IOPAD(0x00a4, PIN_INPUT, 3) /* (N17) GPMC0_DIR.EQEP0_B */ 377 AM64X_IOPAD(0x00ac, PIN_INPUT, 3) /* (R20) GPMC0_CSn1.EQEP0_I */ 378 AM64X_IOPAD(0x00a8, PIN_INPUT, 3) /* (R19) GPMC0_CSn0.EQEP0_S */ 379 >; 380 }; 381 382 main_wlan_en_pins_default: main-wlan-en-default-pins { 383 pinctrl-single,pins = < 384 AM64X_IOPAD(0x00c4, PIN_OUTPUT_PULLUP, 7) /* (V8) GPIO0_48 */ 385 >; 386 }; 387 388 main_com8_ls_en_pins_default: main-com8-ls-en-default-pins { 389 pinctrl-single,pins = < 390 AM64X_IOPAD(0x00fc, PIN_OUTPUT, 7) /* (U7) PRG1_PRU0_GPO17.GPIO0_62 */ 391 >; 392 }; 393 394 main_wlan_pins_default: main-wlan-default-pins { 395 pinctrl-single,pins = < 396 AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */ 397 >; 398 }; 399}; 400 401&main_uart0 { 402 bootph-all; 403 status = "okay"; 404 pinctrl-names = "default"; 405 pinctrl-0 = <&main_uart0_pins_default>; 406}; 407 408&main_uart1 { 409 /* main_uart1 is reserved for firmware usage */ 410 bootph-pre-ram; 411 status = "reserved"; 412 pinctrl-names = "default"; 413 pinctrl-0 = <&main_uart1_pins_default>; 414}; 415 416&main_i2c0 { 417 bootph-all; 418 status = "okay"; 419 pinctrl-names = "default"; 420 pinctrl-0 = <&main_i2c0_pins_default>; 421 clock-frequency = <400000>; 422 423 eeprom@51 { 424 compatible = "atmel,24c512"; 425 reg = <0x51>; 426 }; 427}; 428 429&main_i2c1 { 430 bootph-all; 431 status = "okay"; 432 pinctrl-names = "default"; 433 pinctrl-0 = <&main_i2c1_pins_default>; 434 clock-frequency = <400000>; 435 436 exp1: gpio@70 { 437 bootph-all; 438 compatible = "nxp,pca9538"; 439 reg = <0x70>; 440 gpio-controller; 441 #gpio-cells = <2>; 442 gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", 443 "PRU_DETECT", "MMC1_SD_EN", 444 "VPP_LDO_EN", "RPI_PS_3V3_En", 445 "RPI_PS_5V0_En", "RPI_HAT_DETECT"; 446 }; 447 448 exp2: gpio@60 { 449 compatible = "ti,tpic2810"; 450 reg = <0x60>; 451 gpio-controller; 452 #gpio-cells = <2>; 453 gpio-line-names = "LED1","LED2","LED3","LED4","LED5","LED6","LED7","LED8"; 454 }; 455 456 /* SoC power supply temperature */ 457 tmp100@48 { 458 compatible = "ti,tmp100"; 459 reg = <0x48>; 460 }; 461 462 /* DDR power supply temperature */ 463 tmp100@49 { 464 compatible = "ti,tmp100"; 465 reg = <0x49>; 466 }; 467}; 468 469/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */ 470&mcu_gpio0 { 471 status = "reserved"; 472}; 473 474&mcu_gpio_intr { 475 status = "reserved"; 476}; 477 478&sdhci0 { 479 status = "okay"; 480 vmmc-supply = <&wlan_en>; 481 bus-width = <4>; 482 non-removable; 483 cap-power-off-card; 484 keep-power-in-suspend; 485 ti,driver-strength-ohm = <50>; 486 487 #address-cells = <1>; 488 #size-cells = <0>; 489 wlcore: wlcore@2 { 490 compatible = "ti,wl1837"; 491 reg = <2>; 492 pinctrl-0 = <&main_wlan_pins_default>; 493 pinctrl-names = "default"; 494 interrupt-parent = <&main_gpio0>; 495 interrupts = <46 IRQ_TYPE_EDGE_FALLING>; 496 }; 497}; 498 499/* SD/MMC */ 500&sdhci1 { 501 bootph-all; 502 status = "okay"; 503 vmmc-supply = <&vdd_mmc1>; 504 pinctrl-names = "default"; 505 pinctrl-0 = <&main_mmc1_pins_default>; 506 disable-wp; 507}; 508 509&serdes_ln_ctrl { 510 bootph-all; 511 idle-states = <AM64_SERDES0_LANE0_USB>; 512}; 513 514&serdes_refclk { 515 bootph-all; 516}; 517 518&serdes_wiz0 { 519 bootph-all; 520}; 521 522&serdes0 { 523 bootph-all; 524 serdes0_usb_link: phy@0 { 525 bootph-all; 526 reg = <0>; 527 cdns,num-lanes = <1>; 528 #phy-cells = <0>; 529 cdns,phy-type = <PHY_TYPE_USB3>; 530 resets = <&serdes_wiz0 1>; 531 }; 532}; 533 534&usbss0 { 535 bootph-all; 536 ti,vbus-divider; 537}; 538 539&usb0 { 540 bootph-all; 541 dr_mode = "host"; 542 maximum-speed = "super-speed"; 543 pinctrl-names = "default"; 544 pinctrl-0 = <&main_usb0_pins_default>; 545 phys = <&serdes0_usb_link>; 546 phy-names = "cdns3,usb3-phy"; 547}; 548 549&cpsw3g { 550 pinctrl-names = "default"; 551 pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>; 552 status = "okay"; 553}; 554 555&cpsw_port1 { 556 phy-mode = "rgmii-rxid"; 557 phy-handle = <&cpsw3g_phy0>; 558 status = "okay"; 559}; 560 561&cpsw_port2 { 562 phy-mode = "rgmii-rxid"; 563 phy-handle = <&cpsw3g_phy1>; 564 status = "okay"; 565}; 566 567&cpsw3g_mdio { 568 status = "okay"; 569 pinctrl-names = "default"; 570 pinctrl-0 = <&mdio1_pins_default>; 571 572 cpsw3g_phy0: ethernet-phy@0 { 573 reg = <0>; 574 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 575 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 576 }; 577 578 cpsw3g_phy1: ethernet-phy@1 { 579 reg = <1>; 580 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 581 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 582 }; 583}; 584 585&ospi0 { 586 status = "okay"; 587 pinctrl-names = "default"; 588 pinctrl-0 = <&ospi0_pins_default>; 589 590 flash@0 { 591 compatible = "jedec,spi-nor"; 592 reg = <0x0>; 593 spi-tx-bus-width = <8>; 594 spi-rx-bus-width = <8>; 595 spi-max-frequency = <25000000>; 596 cdns,tshsl-ns = <60>; 597 cdns,tsd2d-ns = <60>; 598 cdns,tchsh-ns = <60>; 599 cdns,tslch-ns = <60>; 600 cdns,read-delay = <4>; 601 602 partitions { 603 compatible = "fixed-partitions"; 604 #address-cells = <1>; 605 #size-cells = <1>; 606 607 partition@0 { 608 label = "ospi.tiboot3"; 609 reg = <0x0 0x100000>; 610 }; 611 612 partition@100000 { 613 label = "ospi.tispl"; 614 reg = <0x100000 0x200000>; 615 }; 616 617 partition@300000 { 618 label = "ospi.u-boot"; 619 reg = <0x300000 0x400000>; 620 }; 621 622 partition@700000 { 623 label = "ospi.env"; 624 reg = <0x700000 0x40000>; 625 }; 626 627 partition@740000 { 628 label = "ospi.env.backup"; 629 reg = <0x740000 0x40000>; 630 }; 631 632 partition@800000 { 633 label = "ospi.rootfs"; 634 reg = <0x800000 0x37c0000>; 635 }; 636 637 partition@3fc0000 { 638 label = "ospi.phypattern"; 639 reg = <0x3fc0000 0x40000>; 640 }; 641 }; 642 }; 643}; 644 645&mailbox0_cluster2 { 646 status = "okay"; 647 648 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 649 ti,mbox-rx = <0 0 2>; 650 ti,mbox-tx = <1 0 2>; 651 }; 652 653 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 654 ti,mbox-rx = <2 0 2>; 655 ti,mbox-tx = <3 0 2>; 656 }; 657}; 658 659&mailbox0_cluster4 { 660 status = "okay"; 661 662 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 663 ti,mbox-rx = <0 0 2>; 664 ti,mbox-tx = <1 0 2>; 665 }; 666 667 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 668 ti,mbox-rx = <2 0 2>; 669 ti,mbox-tx = <3 0 2>; 670 }; 671}; 672 673&mailbox0_cluster6 { 674 status = "okay"; 675 676 mbox_m4_0: mbox-m4-0 { 677 ti,mbox-rx = <0 0 2>; 678 ti,mbox-tx = <1 0 2>; 679 }; 680}; 681 682&main_r5fss0_core0 { 683 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; 684 memory-region = <&main_r5fss0_core0_dma_memory_region>, 685 <&main_r5fss0_core0_memory_region>; 686}; 687 688&main_r5fss0_core1 { 689 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; 690 memory-region = <&main_r5fss0_core1_dma_memory_region>, 691 <&main_r5fss0_core1_memory_region>; 692}; 693 694&main_r5fss1_core0 { 695 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; 696 memory-region = <&main_r5fss1_core0_dma_memory_region>, 697 <&main_r5fss1_core0_memory_region>; 698}; 699 700&main_r5fss1_core1 { 701 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; 702 memory-region = <&main_r5fss1_core1_dma_memory_region>, 703 <&main_r5fss1_core1_memory_region>; 704}; 705 706&mcu_m4fss { 707 mboxes = <&mailbox0_cluster6 &mbox_m4_0>; 708 memory-region = <&mcu_m4fss_dma_memory_region>, 709 <&mcu_m4fss_memory_region>; 710 status = "okay"; 711}; 712 713&ecap0 { 714 status = "okay"; 715 /* PWM is available on Pin 1 of header J3 */ 716 pinctrl-names = "default"; 717 pinctrl-0 = <&main_ecap0_pins_default>; 718}; 719 720&eqep0 { 721 status = "okay"; 722 /* EQEP0 A & B available on pins 18 & 22 of J4 header */ 723 pinctrl-names = "default"; 724 pinctrl-0 = <&main_eqep0_pins_default>; 725}; 726