1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/phy/phy.h> 9#include <dt-bindings/leds/common.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/net/ti-dp83867.h> 12#include "k3-am642.dtsi" 13 14#include "k3-serdes.h" 15 16/ { 17 compatible = "ti,am642-evm", "ti,am642"; 18 model = "Texas Instruments AM642 EVM"; 19 20 chosen { 21 stdout-path = &main_uart0; 22 }; 23 24 aliases { 25 serial0 = &mcu_uart0; 26 serial1 = &main_uart1; 27 serial2 = &main_uart0; 28 serial3 = &main_uart3; 29 i2c0 = &main_i2c0; 30 i2c1 = &main_i2c1; 31 mmc0 = &sdhci0; 32 mmc1 = &sdhci1; 33 ethernet0 = &cpsw_port1; 34 ethernet1 = &cpsw_port2; 35 ethernet2 = &icssg1_emac0; 36 }; 37 38 memory@80000000 { 39 bootph-all; 40 device_type = "memory"; 41 /* 2G RAM */ 42 reg = <0x00000000 0x80000000 0x00000000 0x80000000>; 43 }; 44 45 reserved-memory { 46 #address-cells = <2>; 47 #size-cells = <2>; 48 ranges; 49 50 secure_ddr: optee@9e800000 { 51 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ 52 alignment = <0x1000>; 53 no-map; 54 }; 55 56 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 57 compatible = "shared-dma-pool"; 58 reg = <0x00 0xa0000000 0x00 0x100000>; 59 no-map; 60 }; 61 62 main_r5fss0_core0_memory_region: r5f-memory@a0100000 { 63 compatible = "shared-dma-pool"; 64 reg = <0x00 0xa0100000 0x00 0xf00000>; 65 no-map; 66 }; 67 68 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 69 compatible = "shared-dma-pool"; 70 reg = <0x00 0xa1000000 0x00 0x100000>; 71 no-map; 72 }; 73 74 main_r5fss0_core1_memory_region: r5f-memory@a1100000 { 75 compatible = "shared-dma-pool"; 76 reg = <0x00 0xa1100000 0x00 0xf00000>; 77 no-map; 78 }; 79 80 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { 81 compatible = "shared-dma-pool"; 82 reg = <0x00 0xa2000000 0x00 0x100000>; 83 no-map; 84 }; 85 86 main_r5fss1_core0_memory_region: r5f-memory@a2100000 { 87 compatible = "shared-dma-pool"; 88 reg = <0x00 0xa2100000 0x00 0xf00000>; 89 no-map; 90 }; 91 92 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { 93 compatible = "shared-dma-pool"; 94 reg = <0x00 0xa3000000 0x00 0x100000>; 95 no-map; 96 }; 97 98 main_r5fss1_core1_memory_region: r5f-memory@a3100000 { 99 compatible = "shared-dma-pool"; 100 reg = <0x00 0xa3100000 0x00 0xf00000>; 101 no-map; 102 }; 103 104 mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 { 105 compatible = "shared-dma-pool"; 106 reg = <0x00 0xa4000000 0x00 0x100000>; 107 no-map; 108 }; 109 110 mcu_m4fss_memory_region: m4f-memory@a4100000 { 111 compatible = "shared-dma-pool"; 112 reg = <0x00 0xa4100000 0x00 0xf00000>; 113 no-map; 114 }; 115 116 rtos_ipc_memory_region: ipc-memories@a5000000 { 117 reg = <0x00 0xa5000000 0x00 0x00800000>; 118 alignment = <0x1000>; 119 no-map; 120 }; 121 }; 122 123 evm_12v0: regulator-0 { 124 /* main DC jack */ 125 bootph-all; 126 compatible = "regulator-fixed"; 127 regulator-name = "evm_12v0"; 128 regulator-min-microvolt = <12000000>; 129 regulator-max-microvolt = <12000000>; 130 regulator-always-on; 131 regulator-boot-on; 132 }; 133 134 vsys_5v0: regulator-1 { 135 /* output of LM5140 */ 136 compatible = "regulator-fixed"; 137 regulator-name = "vsys_5v0"; 138 regulator-min-microvolt = <5000000>; 139 regulator-max-microvolt = <5000000>; 140 vin-supply = <&evm_12v0>; 141 regulator-always-on; 142 regulator-boot-on; 143 }; 144 145 vsys_3v3: regulator-2 { 146 /* output of LM5140 */ 147 bootph-all; 148 compatible = "regulator-fixed"; 149 regulator-name = "vsys_3v3"; 150 regulator-min-microvolt = <3300000>; 151 regulator-max-microvolt = <3300000>; 152 vin-supply = <&evm_12v0>; 153 regulator-always-on; 154 regulator-boot-on; 155 }; 156 157 vdd_mmc1: regulator-3 { 158 /* TPS2051BD */ 159 bootph-all; 160 compatible = "regulator-fixed"; 161 regulator-name = "vdd_mmc1"; 162 regulator-min-microvolt = <3300000>; 163 regulator-max-microvolt = <3300000>; 164 regulator-boot-on; 165 enable-active-high; 166 vin-supply = <&vsys_3v3>; 167 gpio = <&exp1 6 GPIO_ACTIVE_HIGH>; 168 }; 169 170 vddb: regulator-4 { 171 compatible = "regulator-fixed"; 172 regulator-name = "vddb_3v3_display"; 173 regulator-min-microvolt = <3300000>; 174 regulator-max-microvolt = <3300000>; 175 vin-supply = <&vsys_3v3>; 176 regulator-always-on; 177 regulator-boot-on; 178 }; 179 180 vtt_supply: regulator-5 { 181 bootph-all; 182 compatible = "regulator-fixed"; 183 regulator-name = "vtt"; 184 pinctrl-names = "default"; 185 pinctrl-0 = <&ddr_vtt_pins_default>; 186 regulator-min-microvolt = <3300000>; 187 regulator-max-microvolt = <3300000>; 188 gpio = <&main_gpio0 12 GPIO_ACTIVE_HIGH>; 189 vin-supply = <&vsys_3v3>; 190 enable-active-high; 191 regulator-always-on; 192 regulator-boot-on; 193 }; 194 195 leds { 196 compatible = "gpio-leds"; 197 198 led-0 { 199 label = "am64-evm:red:heartbeat"; 200 gpios = <&exp1 16 GPIO_ACTIVE_HIGH>; 201 linux,default-trigger = "heartbeat"; 202 function = LED_FUNCTION_HEARTBEAT; 203 default-state = "off"; 204 }; 205 }; 206 207 mdio_mux: mux-controller { 208 compatible = "gpio-mux"; 209 #mux-control-cells = <0>; 210 211 mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>; 212 }; 213 214 mdio_mux_1: mdio-mux-1 { 215 compatible = "mdio-mux-multiplexer"; 216 mux-controls = <&mdio_mux>; 217 mdio-parent-bus = <&cpsw3g_mdio>; 218 #address-cells = <1>; 219 #size-cells = <0>; 220 221 mdio@1 { 222 reg = <0x1>; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 226 cpsw3g_phy3: ethernet-phy@3 { 227 reg = <3>; 228 }; 229 }; 230 }; 231 232 transceiver1: can-phy0 { 233 compatible = "ti,tcan1042"; 234 #phy-cells = <0>; 235 max-bitrate = <5000000>; 236 standby-gpios = <&exp1 8 GPIO_ACTIVE_HIGH>; 237 }; 238 239 transceiver2: can-phy1 { 240 compatible = "ti,tcan1042"; 241 #phy-cells = <0>; 242 max-bitrate = <5000000>; 243 standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>; 244 }; 245 246 icssg1_eth: icssg1-eth { 247 compatible = "ti,am642-icssg-prueth"; 248 pinctrl-names = "default"; 249 pinctrl-0 = <&icssg1_rgmii1_pins_default>; 250 sram = <&oc_sram>; 251 ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>; 252 firmware-name = "ti-pruss/am64x-sr2-pru0-prueth-fw.elf", 253 "ti-pruss/am64x-sr2-rtu0-prueth-fw.elf", 254 "ti-pruss/am64x-sr2-txpru0-prueth-fw.elf", 255 "ti-pruss/am64x-sr2-pru1-prueth-fw.elf", 256 "ti-pruss/am64x-sr2-rtu1-prueth-fw.elf", 257 "ti-pruss/am64x-sr2-txpru1-prueth-fw.elf"; 258 259 ti,pruss-gp-mux-sel = <2>, /* MII mode */ 260 <2>, 261 <2>, 262 <2>, /* MII mode */ 263 <2>, 264 <2>; 265 ti,mii-g-rt = <&icssg1_mii_g_rt>; 266 ti,mii-rt = <&icssg1_mii_rt>; 267 ti,iep = <&icssg1_iep0>, <&icssg1_iep1>; 268 ti,pa-stats = <&icssg1_pa_stats>; 269 interrupt-parent = <&icssg1_intc>; 270 interrupts = <24 0 2>, <25 1 3>; 271 interrupt-names = "tx_ts0", "tx_ts1"; 272 dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */ 273 <&main_pktdma 0xc201 15>, /* egress slice 0 */ 274 <&main_pktdma 0xc202 15>, /* egress slice 0 */ 275 <&main_pktdma 0xc203 15>, /* egress slice 0 */ 276 <&main_pktdma 0xc204 15>, /* egress slice 1 */ 277 <&main_pktdma 0xc205 15>, /* egress slice 1 */ 278 <&main_pktdma 0xc206 15>, /* egress slice 1 */ 279 <&main_pktdma 0xc207 15>, /* egress slice 1 */ 280 <&main_pktdma 0x4200 15>, /* ingress slice 0 */ 281 <&main_pktdma 0x4201 15>; /* ingress slice 1 */ 282 dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", 283 "tx1-0", "tx1-1", "tx1-2", "tx1-3", 284 "rx0", "rx1"; 285 286 ethernet-ports { 287 #address-cells = <1>; 288 #size-cells = <0>; 289 icssg1_emac0: port@0 { 290 reg = <0>; 291 phy-handle = <&icssg1_phy1>; 292 phy-mode = "rgmii-id"; 293 /* Filled in by bootloader */ 294 local-mac-address = [00 00 00 00 00 00]; 295 }; 296 icssg1_emac1: port@1 { 297 reg = <1>; 298 /* Filled in by bootloader */ 299 local-mac-address = [00 00 00 00 00 00]; 300 status = "disabled"; 301 }; 302 }; 303 }; 304}; 305 306&main_pmx0 { 307 main_mmc1_pins_default: main-mmc1-default-pins { 308 pinctrl-single,pins = < 309 AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ 310 AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */ 311 AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */ 312 AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */ 313 AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */ 314 AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */ 315 AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ 316 AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */ 317 AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */ 318 >; 319 }; 320 321 main_uart1_pins_default: main-uart1-default-pins { 322 pinctrl-single,pins = < 323 AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */ 324 AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ 325 AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */ 326 AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */ 327 >; 328 }; 329 330 main_uart0_pins_default: main-uart0-default-pins { 331 bootph-all; 332 pinctrl-single,pins = < 333 AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ 334 AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ 335 AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ 336 AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ 337 >; 338 }; 339 340 main_spi0_pins_default: main-spi0-default-pins { 341 pinctrl-single,pins = < 342 AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */ 343 AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */ 344 AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */ 345 AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */ 346 >; 347 }; 348 349 main_i2c0_pins_default: main-i2c0-default-pins { 350 bootph-all; 351 pinctrl-single,pins = < 352 AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ 353 AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ 354 >; 355 }; 356 357 main_i2c1_pins_default: main-i2c1-default-pins { 358 bootph-all; 359 pinctrl-single,pins = < 360 AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ 361 AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ 362 >; 363 }; 364 365 mdio1_pins_default: mdio1-default-pins { 366 bootph-all; 367 pinctrl-single,pins = < 368 AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ 369 AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ 370 >; 371 }; 372 373 rgmii1_pins_default: rgmii1-default-pins { 374 bootph-all; 375 pinctrl-single,pins = < 376 AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */ 377 AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */ 378 AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */ 379 AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */ 380 AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */ 381 AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */ 382 AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */ 383 AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */ 384 AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */ 385 AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ 386 AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */ 387 AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ 388 >; 389 }; 390 391 rgmii2_pins_default: rgmii2-default-pins { 392 bootph-all; 393 pinctrl-single,pins = < 394 AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ 395 AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ 396 AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ 397 AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ 398 AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ 399 AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ 400 AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ 401 AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ 402 AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ 403 AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ 404 AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ 405 AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ 406 >; 407 }; 408 409 main_usb0_pins_default: main-usb0-default-pins { 410 bootph-all; 411 pinctrl-single,pins = < 412 AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ 413 >; 414 }; 415 416 ospi0_pins_default: ospi0-default-pins { 417 pinctrl-single,pins = < 418 AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ 419 AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ 420 AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */ 421 AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */ 422 AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */ 423 AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */ 424 AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */ 425 AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */ 426 AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */ 427 AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ 428 AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ 429 >; 430 }; 431 432 main_ecap0_pins_default: main-ecap0-default-pins { 433 pinctrl-single,pins = < 434 AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ 435 >; 436 }; 437 438 main_mcan0_pins_default: main-mcan0-default-pins { 439 pinctrl-single,pins = < 440 AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */ 441 AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */ 442 >; 443 }; 444 445 main_mcan1_pins_default: main-mcan1-default-pins { 446 pinctrl-single,pins = < 447 AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */ 448 AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */ 449 >; 450 }; 451 452 ddr_vtt_pins_default: ddr-vtt-default-pins { 453 bootph-all; 454 pinctrl-single,pins = < 455 AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */ 456 >; 457 }; 458 459 icssg1_mdio1_pins_default: icssg1-mdio1-default-pins { 460 pinctrl-single,pins = < 461 AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* (Y6) PRG1_MDIO0_MDC */ 462 AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA6) PRG1_MDIO0_MDIO */ 463 >; 464 }; 465 466 icssg1_rgmii1_pins_default: icssg1-rgmii1-default-pins { 467 pinctrl-single,pins = < 468 AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */ 469 AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */ 470 AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */ 471 AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */ 472 AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */ 473 AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */ 474 AM64X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */ 475 AM64X_IOPAD(0x00e8, PIN_INPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */ 476 AM64X_IOPAD(0x00ec, PIN_INPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */ 477 AM64X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */ 478 AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */ 479 AM64X_IOPAD(0x00f4, PIN_INPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */ 480 >; 481 }; 482 483 icssg1_iep0_pins_default: icssg1-iep0-default-pins { 484 pinctrl-single,pins = < 485 AM64X_IOPAD(0x0104, PIN_OUTPUT, 2) /* (W7) PRG1_PRU0_GPO19.PRG1_IEP0_EDC_SYNC_OUT0 */ 486 >; 487 }; 488}; 489 490&main_uart0 { 491 bootph-all; 492 status = "okay"; 493 pinctrl-names = "default"; 494 pinctrl-0 = <&main_uart0_pins_default>; 495}; 496 497/* main_uart1 is reserved for firmware usage */ 498&main_uart1 { 499 status = "reserved"; 500 pinctrl-names = "default"; 501 pinctrl-0 = <&main_uart1_pins_default>; 502}; 503 504&main_i2c0 { 505 bootph-all; 506 status = "okay"; 507 pinctrl-names = "default"; 508 pinctrl-0 = <&main_i2c0_pins_default>; 509 clock-frequency = <400000>; 510 511 gpio@38 { 512 /* TCA9554 */ 513 compatible = "nxp,pca9554"; 514 reg = <0x38>; 515 gpio-controller; 516 #gpio-cells = <2>; 517 gpio-line-names = "HSE_DETECT"; 518 }; 519 520 eeprom@50 { 521 /* AT24CM01 */ 522 compatible = "atmel,24c1024"; 523 reg = <0x50>; 524 }; 525}; 526 527&main_i2c1 { 528 bootph-all; 529 status = "okay"; 530 pinctrl-names = "default"; 531 pinctrl-0 = <&main_i2c1_pins_default>; 532 clock-frequency = <400000>; 533 534 exp1: gpio@22 { 535 bootph-all; 536 compatible = "ti,tca6424"; 537 reg = <0x22>; 538 gpio-controller; 539 #gpio-cells = <2>; 540 gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL", 541 "GPIO_CPSW1_RST", "GPIO_RGMII1_RST", 542 "GPIO_RGMII2_RST", "GPIO_PCIe_RST_OUT", 543 "MMC1_SD_EN", "FSI_FET_SEL", 544 "MCAN0_STB_3V3", "MCAN1_STB_3V3", 545 "CPSW_FET_SEL", "CPSW_FET2_SEL", 546 "PRG1_RGMII2_FET_SEL", "TEST_GPIO2", 547 "GPIO_OLED_RESETn", "VPP_LDO_EN", 548 "TEST_LED1", "TP92", "TP90", "TP88", 549 "TP87", "TP86", "TP89", "TP91"; 550 }; 551 552 /* osd9616p0899-10 */ 553 display@3c { 554 compatible = "solomon,ssd1306fb-i2c"; 555 reg = <0x3c>; 556 reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>; 557 vbat-supply = <&vddb>; 558 solomon,height = <16>; 559 solomon,width = <96>; 560 solomon,com-seq; 561 solomon,com-invdir; 562 solomon,page-offset = <0>; 563 solomon,prechargep1 = <2>; 564 solomon,prechargep2 = <13>; 565 }; 566}; 567 568&main_gpio0 { 569 bootph-all; 570}; 571 572/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */ 573&mcu_gpio0 { 574 status = "reserved"; 575}; 576 577&mcu_gpio_intr { 578 status = "reserved"; 579}; 580 581&main_spi0 { 582 status = "okay"; 583 pinctrl-names = "default"; 584 pinctrl-0 = <&main_spi0_pins_default>; 585 ti,pindir-d0-out-d1-in; 586 eeprom@0 { 587 compatible = "microchip,93lc46b"; 588 reg = <0>; 589 spi-max-frequency = <1000000>; 590 spi-cs-high; 591 data-size = <16>; 592 }; 593}; 594 595/* eMMC */ 596&sdhci0 { 597 status = "okay"; 598 non-removable; 599 ti,driver-strength-ohm = <50>; 600 disable-wp; 601 bootph-all; 602}; 603 604/* SD/MMC */ 605&sdhci1 { 606 bootph-all; 607 status = "okay"; 608 vmmc-supply = <&vdd_mmc1>; 609 pinctrl-names = "default"; 610 pinctrl-0 = <&main_mmc1_pins_default>; 611 disable-wp; 612}; 613 614&usbss0 { 615 bootph-all; 616 ti,vbus-divider; 617 ti,usb2-only; 618}; 619 620&usb0 { 621 bootph-all; 622 dr_mode = "otg"; 623 maximum-speed = "high-speed"; 624 pinctrl-names = "default"; 625 pinctrl-0 = <&main_usb0_pins_default>; 626}; 627 628&cpsw3g { 629 bootph-all; 630 pinctrl-names = "default"; 631 pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>; 632 status = "okay"; 633}; 634 635&cpsw_port1 { 636 bootph-all; 637 phy-mode = "rgmii-rxid"; 638 phy-handle = <&cpsw3g_phy0>; 639 status = "okay"; 640}; 641 642&cpsw_port2 { 643 phy-mode = "rgmii-rxid"; 644 phy-handle = <&cpsw3g_phy3>; 645 status = "okay"; 646}; 647 648&cpsw3g_mdio { 649 bootph-all; 650 status = "okay"; 651 pinctrl-names = "default"; 652 pinctrl-0 = <&mdio1_pins_default>; 653 654 cpsw3g_phy0: ethernet-phy@0 { 655 bootph-all; 656 reg = <0>; 657 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 658 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 659 }; 660}; 661 662&tscadc0 { 663 /* ADC is reserved for R5 usage */ 664 status = "reserved"; 665 666 adc { 667 ti,adc-channels = <0 1 2 3 4 5 6 7>; 668 }; 669}; 670 671&ospi0 { 672 status = "okay"; 673 pinctrl-names = "default"; 674 pinctrl-0 = <&ospi0_pins_default>; 675 676 flash@0 { 677 compatible = "jedec,spi-nor"; 678 reg = <0x0>; 679 spi-tx-bus-width = <8>; 680 spi-rx-bus-width = <8>; 681 spi-max-frequency = <25000000>; 682 cdns,tshsl-ns = <60>; 683 cdns,tsd2d-ns = <60>; 684 cdns,tchsh-ns = <60>; 685 cdns,tslch-ns = <60>; 686 cdns,read-delay = <4>; 687 688 partitions { 689 compatible = "fixed-partitions"; 690 #address-cells = <1>; 691 #size-cells = <1>; 692 693 partition@0 { 694 label = "ospi.tiboot3"; 695 reg = <0x0 0x100000>; 696 }; 697 698 partition@100000 { 699 label = "ospi.tispl"; 700 reg = <0x100000 0x200000>; 701 }; 702 703 partition@300000 { 704 label = "ospi.u-boot"; 705 reg = <0x300000 0x400000>; 706 }; 707 708 partition@700000 { 709 label = "ospi.env"; 710 reg = <0x700000 0x40000>; 711 }; 712 713 partition@740000 { 714 label = "ospi.env.backup"; 715 reg = <0x740000 0x40000>; 716 }; 717 718 partition@800000 { 719 label = "ospi.rootfs"; 720 reg = <0x800000 0x37c0000>; 721 }; 722 723 partition@3fc0000 { 724 label = "ospi.phypattern"; 725 reg = <0x3fc0000 0x40000>; 726 }; 727 }; 728 }; 729}; 730 731&mailbox0_cluster2 { 732 status = "okay"; 733 734 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 735 ti,mbox-rx = <0 0 2>; 736 ti,mbox-tx = <1 0 2>; 737 }; 738 739 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 740 ti,mbox-rx = <2 0 2>; 741 ti,mbox-tx = <3 0 2>; 742 }; 743}; 744 745&mailbox0_cluster4 { 746 status = "okay"; 747 748 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 749 ti,mbox-rx = <0 0 2>; 750 ti,mbox-tx = <1 0 2>; 751 }; 752 753 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 754 ti,mbox-rx = <2 0 2>; 755 ti,mbox-tx = <3 0 2>; 756 }; 757}; 758 759&mailbox0_cluster6 { 760 status = "okay"; 761 762 mbox_m4_0: mbox-m4-0 { 763 ti,mbox-rx = <0 0 2>; 764 ti,mbox-tx = <1 0 2>; 765 }; 766}; 767 768&main_r5fss0_core0 { 769 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; 770 memory-region = <&main_r5fss0_core0_dma_memory_region>, 771 <&main_r5fss0_core0_memory_region>; 772}; 773 774&main_r5fss0_core1 { 775 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; 776 memory-region = <&main_r5fss0_core1_dma_memory_region>, 777 <&main_r5fss0_core1_memory_region>; 778}; 779 780&main_r5fss1_core0 { 781 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; 782 memory-region = <&main_r5fss1_core0_dma_memory_region>, 783 <&main_r5fss1_core0_memory_region>; 784}; 785 786&main_r5fss1_core1 { 787 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; 788 memory-region = <&main_r5fss1_core1_dma_memory_region>, 789 <&main_r5fss1_core1_memory_region>; 790}; 791 792&mcu_m4fss { 793 mboxes = <&mailbox0_cluster6 &mbox_m4_0>; 794 memory-region = <&mcu_m4fss_dma_memory_region>, 795 <&mcu_m4fss_memory_region>; 796 status = "okay"; 797}; 798 799&serdes_ln_ctrl { 800 idle-states = <AM64_SERDES0_LANE0_PCIE0>; 801}; 802 803&serdes0 { 804 serdes0_pcie_link: phy@0 { 805 reg = <0>; 806 cdns,num-lanes = <1>; 807 #phy-cells = <0>; 808 cdns,phy-type = <PHY_TYPE_PCIE>; 809 resets = <&serdes_wiz0 1>; 810 }; 811}; 812 813&pcie0_rc { 814 status = "okay"; 815 reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; 816 phys = <&serdes0_pcie_link>; 817 phy-names = "pcie-phy"; 818 num-lanes = <1>; 819}; 820 821&ecap0 { 822 status = "okay"; 823 /* PWM is available on Pin 1 of header J12 */ 824 pinctrl-names = "default"; 825 pinctrl-0 = <&main_ecap0_pins_default>; 826}; 827 828&main_mcan0 { 829 status = "okay"; 830 pinctrl-names = "default"; 831 pinctrl-0 = <&main_mcan0_pins_default>; 832 phys = <&transceiver1>; 833}; 834 835&main_mcan1 { 836 status = "okay"; 837 pinctrl-names = "default"; 838 pinctrl-0 = <&main_mcan1_pins_default>; 839 phys = <&transceiver2>; 840}; 841 842&icssg1_mdio { 843 status = "okay"; 844 pinctrl-names = "default"; 845 pinctrl-0 = <&icssg1_mdio1_pins_default>; 846 847 icssg1_phy1: ethernet-phy@f { 848 reg = <0xf>; 849 tx-internal-delay-ps = <250>; 850 rx-internal-delay-ps = <2000>; 851 }; 852}; 853 854&gpmc0 { 855 ranges = <0 0 0x00 0x51000000 0x01000000>; /* CS0 space. Min partition = 16MB */ 856}; 857 858&icssg1_iep0 { 859 pinctrl-names = "default"; 860 pinctrl-0 = <&icssg1_iep0_pins_default>; 861}; 862