xref: /linux/arch/arm64/boot/dts/ti/k3-am642-evm.dts (revision c5288cda69ee2d8607f5026bd599a5cebf0ee783)
1// SPDX-License-Identifier: GPL-2.0-only OR MIT
2/*
3 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/phy/phy.h>
9#include <dt-bindings/leds/common.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/net/ti-dp83867.h>
12#include "k3-am642.dtsi"
13
14#include "k3-serdes.h"
15
16/ {
17	compatible = "ti,am642-evm", "ti,am642";
18	model = "Texas Instruments AM642 EVM";
19
20	chosen {
21		stdout-path = &main_uart0;
22	};
23
24	aliases {
25		serial0 = &mcu_uart0;
26		serial1 = &main_uart1;
27		serial2 = &main_uart0;
28		serial3 = &main_uart3;
29		i2c0 = &main_i2c0;
30		i2c1 = &main_i2c1;
31		mmc0 = &sdhci0;
32		mmc1 = &sdhci1;
33		ethernet0 = &cpsw_port1;
34		ethernet1 = &cpsw_port2;
35		ethernet2 = &icssg1_emac0;
36	};
37
38	memory@80000000 {
39		bootph-all;
40		device_type = "memory";
41		/* 2G RAM */
42		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
43	};
44
45	reserved-memory {
46		#address-cells = <2>;
47		#size-cells = <2>;
48		ranges;
49
50		secure_ddr: optee@9e800000 {
51			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
52			alignment = <0x1000>;
53			no-map;
54		};
55
56		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
57			compatible = "shared-dma-pool";
58			reg = <0x00 0xa0000000 0x00 0x100000>;
59			no-map;
60		};
61
62		main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
63			compatible = "shared-dma-pool";
64			reg = <0x00 0xa0100000 0x00 0xf00000>;
65			no-map;
66		};
67
68		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
69			compatible = "shared-dma-pool";
70			reg = <0x00 0xa1000000 0x00 0x100000>;
71			no-map;
72		};
73
74		main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
75			compatible = "shared-dma-pool";
76			reg = <0x00 0xa1100000 0x00 0xf00000>;
77			no-map;
78		};
79
80		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
81			compatible = "shared-dma-pool";
82			reg = <0x00 0xa2000000 0x00 0x100000>;
83			no-map;
84		};
85
86		main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
87			compatible = "shared-dma-pool";
88			reg = <0x00 0xa2100000 0x00 0xf00000>;
89			no-map;
90		};
91
92		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
93			compatible = "shared-dma-pool";
94			reg = <0x00 0xa3000000 0x00 0x100000>;
95			no-map;
96		};
97
98		main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
99			compatible = "shared-dma-pool";
100			reg = <0x00 0xa3100000 0x00 0xf00000>;
101			no-map;
102		};
103
104		rtos_ipc_memory_region: ipc-memories@a5000000 {
105			reg = <0x00 0xa5000000 0x00 0x00800000>;
106			alignment = <0x1000>;
107			no-map;
108		};
109	};
110
111	evm_12v0: regulator-0 {
112		/* main DC jack */
113		bootph-all;
114		compatible = "regulator-fixed";
115		regulator-name = "evm_12v0";
116		regulator-min-microvolt = <12000000>;
117		regulator-max-microvolt = <12000000>;
118		regulator-always-on;
119		regulator-boot-on;
120	};
121
122	vsys_5v0: regulator-1 {
123		/* output of LM5140 */
124		compatible = "regulator-fixed";
125		regulator-name = "vsys_5v0";
126		regulator-min-microvolt = <5000000>;
127		regulator-max-microvolt = <5000000>;
128		vin-supply = <&evm_12v0>;
129		regulator-always-on;
130		regulator-boot-on;
131	};
132
133	vsys_3v3: regulator-2 {
134		/* output of LM5140 */
135		bootph-all;
136		compatible = "regulator-fixed";
137		regulator-name = "vsys_3v3";
138		regulator-min-microvolt = <3300000>;
139		regulator-max-microvolt = <3300000>;
140		vin-supply = <&evm_12v0>;
141		regulator-always-on;
142		regulator-boot-on;
143	};
144
145	vdd_mmc1: regulator-3 {
146		/* TPS2051BD */
147		bootph-all;
148		compatible = "regulator-fixed";
149		regulator-name = "vdd_mmc1";
150		regulator-min-microvolt = <3300000>;
151		regulator-max-microvolt = <3300000>;
152		regulator-boot-on;
153		enable-active-high;
154		vin-supply = <&vsys_3v3>;
155		gpio = <&exp1 6 GPIO_ACTIVE_HIGH>;
156	};
157
158	vddb: regulator-4 {
159		compatible = "regulator-fixed";
160		regulator-name = "vddb_3v3_display";
161		regulator-min-microvolt = <3300000>;
162		regulator-max-microvolt = <3300000>;
163		vin-supply = <&vsys_3v3>;
164		regulator-always-on;
165		regulator-boot-on;
166	};
167
168	vtt_supply: regulator-5 {
169		bootph-all;
170		compatible = "regulator-fixed";
171		regulator-name = "vtt";
172		pinctrl-names = "default";
173		pinctrl-0 = <&ddr_vtt_pins_default>;
174		regulator-min-microvolt = <3300000>;
175		regulator-max-microvolt = <3300000>;
176		gpio = <&main_gpio0 12 GPIO_ACTIVE_HIGH>;
177		vin-supply = <&vsys_3v3>;
178		enable-active-high;
179		regulator-always-on;
180		regulator-boot-on;
181	};
182
183	leds {
184		compatible = "gpio-leds";
185
186		led-0 {
187			label = "am64-evm:red:heartbeat";
188			gpios = <&exp1 16 GPIO_ACTIVE_HIGH>;
189			linux,default-trigger = "heartbeat";
190			function = LED_FUNCTION_HEARTBEAT;
191			default-state = "off";
192		};
193	};
194
195	mdio_mux: mux-controller {
196		compatible = "gpio-mux";
197		#mux-control-cells = <0>;
198
199		mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>;
200	};
201
202	mdio_mux_1: mdio-mux-1 {
203		compatible = "mdio-mux-multiplexer";
204		mux-controls = <&mdio_mux>;
205		mdio-parent-bus = <&cpsw3g_mdio>;
206		#address-cells = <1>;
207		#size-cells = <0>;
208
209		mdio@1 {
210			reg = <0x1>;
211			#address-cells = <1>;
212			#size-cells = <0>;
213
214			cpsw3g_phy3: ethernet-phy@3 {
215				reg = <3>;
216			};
217		};
218	};
219
220	transceiver1: can-phy0 {
221		compatible = "ti,tcan1042";
222		#phy-cells = <0>;
223		max-bitrate = <5000000>;
224		standby-gpios = <&exp1 8 GPIO_ACTIVE_HIGH>;
225	};
226
227	transceiver2: can-phy1 {
228		compatible = "ti,tcan1042";
229		#phy-cells = <0>;
230		max-bitrate = <5000000>;
231		standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>;
232	};
233
234	icssg1_eth: icssg1-eth {
235		compatible = "ti,am642-icssg-prueth";
236		pinctrl-names = "default";
237		pinctrl-0 = <&icssg1_rgmii1_pins_default>;
238		sram = <&oc_sram>;
239		ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>;
240		firmware-name = "ti-pruss/am64x-sr2-pru0-prueth-fw.elf",
241				"ti-pruss/am64x-sr2-rtu0-prueth-fw.elf",
242				"ti-pruss/am64x-sr2-txpru0-prueth-fw.elf",
243				"ti-pruss/am64x-sr2-pru1-prueth-fw.elf",
244				"ti-pruss/am64x-sr2-rtu1-prueth-fw.elf",
245				"ti-pruss/am64x-sr2-txpru1-prueth-fw.elf";
246
247		ti,pruss-gp-mux-sel = <2>,	/* MII mode */
248				      <2>,
249				      <2>,
250				      <2>,	/* MII mode */
251				      <2>,
252				      <2>;
253		ti,mii-g-rt = <&icssg1_mii_g_rt>;
254		ti,mii-rt = <&icssg1_mii_rt>;
255		ti,iep = <&icssg1_iep0>,  <&icssg1_iep1>;
256		interrupt-parent = <&icssg1_intc>;
257		interrupts = <24 0 2>, <25 1 3>;
258		interrupt-names = "tx_ts0", "tx_ts1";
259		dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */
260		       <&main_pktdma 0xc201 15>, /* egress slice 0 */
261		       <&main_pktdma 0xc202 15>, /* egress slice 0 */
262		       <&main_pktdma 0xc203 15>, /* egress slice 0 */
263		       <&main_pktdma 0xc204 15>, /* egress slice 1 */
264		       <&main_pktdma 0xc205 15>, /* egress slice 1 */
265		       <&main_pktdma 0xc206 15>, /* egress slice 1 */
266		       <&main_pktdma 0xc207 15>, /* egress slice 1 */
267		       <&main_pktdma 0x4200 15>, /* ingress slice 0 */
268		       <&main_pktdma 0x4201 15>; /* ingress slice 1 */
269		dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
270			    "tx1-0", "tx1-1", "tx1-2", "tx1-3",
271			    "rx0", "rx1";
272
273		ethernet-ports {
274			#address-cells = <1>;
275			#size-cells = <0>;
276			icssg1_emac0: port@0 {
277				reg = <0>;
278				phy-handle = <&icssg1_phy1>;
279				phy-mode = "rgmii-id";
280				/* Filled in by bootloader */
281				local-mac-address = [00 00 00 00 00 00];
282			};
283			icssg1_emac1: port@1 {
284				reg = <1>;
285				/* Filled in by bootloader */
286				local-mac-address = [00 00 00 00 00 00];
287				status = "disabled";
288			};
289		};
290	};
291};
292
293&main_pmx0 {
294	main_mmc1_pins_default: main-mmc1-default-pins {
295		pinctrl-single,pins = <
296			AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
297			AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
298			AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
299			AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
300			AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
301			AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
302			AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
303			AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */
304			AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
305		>;
306	};
307
308	main_uart1_pins_default: main-uart1-default-pins {
309		pinctrl-single,pins = <
310			AM64X_IOPAD(0x0248, PIN_INPUT, 0)		/* (D16) UART1_CTSn */
311			AM64X_IOPAD(0x024c, PIN_OUTPUT, 0)		/* (E16) UART1_RTSn */
312			AM64X_IOPAD(0x0240, PIN_INPUT, 0)		/* (E15) UART1_RXD */
313			AM64X_IOPAD(0x0244, PIN_OUTPUT, 0)		/* (E14) UART1_TXD */
314		>;
315	};
316
317	main_uart0_pins_default: main-uart0-default-pins {
318		bootph-all;
319		pinctrl-single,pins = <
320			AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
321			AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
322			AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
323			AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
324		>;
325	};
326
327	main_spi0_pins_default: main-spi0-default-pins {
328		pinctrl-single,pins = <
329			AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */
330			AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */
331			AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */
332			AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */
333		>;
334	};
335
336	main_i2c0_pins_default: main-i2c0-default-pins {
337		bootph-all;
338		pinctrl-single,pins = <
339			AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
340			AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
341		>;
342	};
343
344	main_i2c1_pins_default: main-i2c1-default-pins {
345		bootph-all;
346		pinctrl-single,pins = <
347			AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
348			AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
349		>;
350	};
351
352	mdio1_pins_default: mdio1-default-pins {
353		bootph-all;
354		pinctrl-single,pins = <
355			AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
356			AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
357		>;
358	};
359
360	rgmii1_pins_default: rgmii1-default-pins {
361		bootph-all;
362		pinctrl-single,pins = <
363			AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
364			AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
365			AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
366			AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
367			AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
368			AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
369			AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
370			AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
371			AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
372			AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
373			AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
374			AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
375		>;
376	};
377
378       rgmii2_pins_default: rgmii2-default-pins {
379		bootph-all;
380		pinctrl-single,pins = <
381			AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
382			AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
383			AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
384			AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
385			AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
386			AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
387			AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
388			AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
389			AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
390			AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
391			AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
392			AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
393		>;
394	};
395
396	main_usb0_pins_default: main-usb0-default-pins {
397		bootph-all;
398		pinctrl-single,pins = <
399			AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
400		>;
401	};
402
403	ospi0_pins_default: ospi0-default-pins {
404		pinctrl-single,pins = <
405			AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
406			AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
407			AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
408			AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
409			AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
410			AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
411			AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
412			AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
413			AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
414			AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
415			AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
416		>;
417	};
418
419	main_ecap0_pins_default: main-ecap0-default-pins {
420		pinctrl-single,pins = <
421			AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
422		>;
423	};
424
425	main_mcan0_pins_default: main-mcan0-default-pins {
426		pinctrl-single,pins = <
427			AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */
428			AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */
429		>;
430	};
431
432	main_mcan1_pins_default: main-mcan1-default-pins {
433		pinctrl-single,pins = <
434			AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */
435			AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */
436		>;
437	};
438
439	ddr_vtt_pins_default: ddr-vtt-default-pins {
440		bootph-all;
441		pinctrl-single,pins = <
442			AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */
443		>;
444	};
445
446	icssg1_mdio1_pins_default: icssg1-mdio1-default-pins {
447		pinctrl-single,pins = <
448			AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* (Y6) PRG1_MDIO0_MDC */
449			AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA6) PRG1_MDIO0_MDIO */
450		>;
451	};
452
453	icssg1_rgmii1_pins_default: icssg1-rgmii1-default-pins{
454		pinctrl-single,pins = <
455			AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */
456			AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */
457			AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */
458			AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */
459			AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */
460			AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */
461			AM64X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */
462			AM64X_IOPAD(0x00e8, PIN_INPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */
463			AM64X_IOPAD(0x00ec, PIN_INPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */
464			AM64X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */
465			AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */
466			AM64X_IOPAD(0x00f4, PIN_INPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */
467		>;
468	};
469};
470
471&main_uart0 {
472	bootph-all;
473	status = "okay";
474	pinctrl-names = "default";
475	pinctrl-0 = <&main_uart0_pins_default>;
476};
477
478/* main_uart1 is reserved for firmware usage */
479&main_uart1 {
480	status = "reserved";
481	pinctrl-names = "default";
482	pinctrl-0 = <&main_uart1_pins_default>;
483};
484
485&main_i2c0 {
486	bootph-all;
487	status = "okay";
488	pinctrl-names = "default";
489	pinctrl-0 = <&main_i2c0_pins_default>;
490	clock-frequency = <400000>;
491
492	gpio@38 {
493		/* TCA9554 */
494		compatible = "nxp,pca9554";
495		reg = <0x38>;
496		gpio-controller;
497		#gpio-cells = <2>;
498		gpio-line-names = "HSE_DETECT";
499	};
500
501	eeprom@50 {
502		/* AT24CM01 */
503		compatible = "atmel,24c1024";
504		reg = <0x50>;
505	};
506};
507
508&main_i2c1 {
509	bootph-all;
510	status = "okay";
511	pinctrl-names = "default";
512	pinctrl-0 = <&main_i2c1_pins_default>;
513	clock-frequency = <400000>;
514
515	exp1: gpio@22 {
516		bootph-all;
517		compatible = "ti,tca6424";
518		reg = <0x22>;
519		gpio-controller;
520		#gpio-cells = <2>;
521		gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL",
522				  "GPIO_CPSW1_RST", "GPIO_RGMII1_RST",
523				  "GPIO_RGMII2_RST", "GPIO_PCIe_RST_OUT",
524				  "MMC1_SD_EN", "FSI_FET_SEL",
525				  "MCAN0_STB_3V3", "MCAN1_STB_3V3",
526				  "CPSW_FET_SEL", "CPSW_FET2_SEL",
527				  "PRG1_RGMII2_FET_SEL", "TEST_GPIO2",
528				  "GPIO_OLED_RESETn", "VPP_LDO_EN",
529				  "TEST_LED1", "TP92", "TP90", "TP88",
530				  "TP87", "TP86", "TP89", "TP91";
531	};
532
533	/* osd9616p0899-10 */
534	display@3c {
535		compatible = "solomon,ssd1306fb-i2c";
536		reg = <0x3c>;
537		reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>;
538		vbat-supply = <&vddb>;
539		solomon,height = <16>;
540		solomon,width = <96>;
541		solomon,com-seq;
542		solomon,com-invdir;
543		solomon,page-offset = <0>;
544		solomon,prechargep1 = <2>;
545		solomon,prechargep2 = <13>;
546	};
547};
548
549&main_gpio0 {
550	bootph-all;
551};
552
553/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */
554&mcu_gpio0 {
555	status = "reserved";
556};
557
558&mcu_gpio_intr {
559	status = "reserved";
560};
561
562&main_spi0 {
563	status = "okay";
564	pinctrl-names = "default";
565	pinctrl-0 = <&main_spi0_pins_default>;
566	ti,pindir-d0-out-d1-in;
567	eeprom@0 {
568		compatible = "microchip,93lc46b";
569		reg = <0>;
570		spi-max-frequency = <1000000>;
571		spi-cs-high;
572		data-size = <16>;
573	};
574};
575
576/* eMMC */
577&sdhci0 {
578	status = "okay";
579	non-removable;
580	ti,driver-strength-ohm = <50>;
581	disable-wp;
582	bootph-all;
583};
584
585/* SD/MMC */
586&sdhci1 {
587	bootph-all;
588	status = "okay";
589	vmmc-supply = <&vdd_mmc1>;
590	pinctrl-names = "default";
591	pinctrl-0 = <&main_mmc1_pins_default>;
592	disable-wp;
593};
594
595&usbss0 {
596	bootph-all;
597	ti,vbus-divider;
598	ti,usb2-only;
599};
600
601&usb0 {
602	bootph-all;
603	dr_mode = "otg";
604	maximum-speed = "high-speed";
605	pinctrl-names = "default";
606	pinctrl-0 = <&main_usb0_pins_default>;
607};
608
609&cpsw3g {
610	bootph-all;
611	pinctrl-names = "default";
612	pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
613};
614
615&cpsw_port1 {
616	bootph-all;
617	phy-mode = "rgmii-rxid";
618	phy-handle = <&cpsw3g_phy0>;
619};
620
621&cpsw_port2 {
622	phy-mode = "rgmii-rxid";
623	phy-handle = <&cpsw3g_phy3>;
624};
625
626&cpsw3g_mdio {
627	bootph-all;
628	status = "okay";
629	pinctrl-names = "default";
630	pinctrl-0 = <&mdio1_pins_default>;
631
632	cpsw3g_phy0: ethernet-phy@0 {
633		bootph-all;
634		reg = <0>;
635		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
636		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
637	};
638};
639
640&tscadc0 {
641	/* ADC is reserved for R5 usage */
642	status = "reserved";
643};
644
645&ospi0 {
646	status = "okay";
647	pinctrl-names = "default";
648	pinctrl-0 = <&ospi0_pins_default>;
649
650	flash@0 {
651		compatible = "jedec,spi-nor";
652		reg = <0x0>;
653		spi-tx-bus-width = <8>;
654		spi-rx-bus-width = <8>;
655		spi-max-frequency = <25000000>;
656		cdns,tshsl-ns = <60>;
657		cdns,tsd2d-ns = <60>;
658		cdns,tchsh-ns = <60>;
659		cdns,tslch-ns = <60>;
660		cdns,read-delay = <4>;
661
662		partitions {
663			compatible = "fixed-partitions";
664			#address-cells = <1>;
665			#size-cells = <1>;
666
667			partition@0 {
668				label = "ospi.tiboot3";
669				reg = <0x0 0x100000>;
670			};
671
672			partition@100000 {
673				label = "ospi.tispl";
674				reg = <0x100000 0x200000>;
675			};
676
677			partition@300000 {
678				label = "ospi.u-boot";
679				reg = <0x300000 0x400000>;
680			};
681
682			partition@700000 {
683				label = "ospi.env";
684				reg = <0x700000 0x40000>;
685			};
686
687			partition@740000 {
688				label = "ospi.env.backup";
689				reg = <0x740000 0x40000>;
690			};
691
692			partition@800000 {
693				label = "ospi.rootfs";
694				reg = <0x800000 0x37c0000>;
695			};
696
697			partition@3fc0000 {
698				label = "ospi.phypattern";
699				reg = <0x3fc0000 0x40000>;
700			};
701		};
702	};
703};
704
705&mailbox0_cluster2 {
706	status = "okay";
707
708	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
709		ti,mbox-rx = <0 0 2>;
710		ti,mbox-tx = <1 0 2>;
711	};
712
713	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
714		ti,mbox-rx = <2 0 2>;
715		ti,mbox-tx = <3 0 2>;
716	};
717};
718
719&mailbox0_cluster4 {
720	status = "okay";
721
722	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
723		ti,mbox-rx = <0 0 2>;
724		ti,mbox-tx = <1 0 2>;
725	};
726
727	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
728		ti,mbox-rx = <2 0 2>;
729		ti,mbox-tx = <3 0 2>;
730	};
731};
732
733&mailbox0_cluster6 {
734	status = "okay";
735
736	mbox_m4_0: mbox-m4-0 {
737		ti,mbox-rx = <0 0 2>;
738		ti,mbox-tx = <1 0 2>;
739	};
740};
741
742&main_r5fss0_core0 {
743	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
744	memory-region = <&main_r5fss0_core0_dma_memory_region>,
745			<&main_r5fss0_core0_memory_region>;
746};
747
748&main_r5fss0_core1 {
749	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
750	memory-region = <&main_r5fss0_core1_dma_memory_region>,
751			<&main_r5fss0_core1_memory_region>;
752};
753
754&main_r5fss1_core0 {
755	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
756	memory-region = <&main_r5fss1_core0_dma_memory_region>,
757			<&main_r5fss1_core0_memory_region>;
758};
759
760&main_r5fss1_core1 {
761	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
762	memory-region = <&main_r5fss1_core1_dma_memory_region>,
763			<&main_r5fss1_core1_memory_region>;
764};
765
766&serdes_ln_ctrl {
767	idle-states = <AM64_SERDES0_LANE0_PCIE0>;
768};
769
770&serdes0 {
771	serdes0_pcie_link: phy@0 {
772		reg = <0>;
773		cdns,num-lanes = <1>;
774		#phy-cells = <0>;
775		cdns,phy-type = <PHY_TYPE_PCIE>;
776		resets = <&serdes_wiz0 1>;
777	};
778};
779
780&pcie0_rc {
781	status = "okay";
782	reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
783	phys = <&serdes0_pcie_link>;
784	phy-names = "pcie-phy";
785	num-lanes = <1>;
786};
787
788&ecap0 {
789	status = "okay";
790	/* PWM is available on Pin 1 of header J12 */
791	pinctrl-names = "default";
792	pinctrl-0 = <&main_ecap0_pins_default>;
793};
794
795&main_mcan0 {
796	status = "okay";
797	pinctrl-names = "default";
798	pinctrl-0 = <&main_mcan0_pins_default>;
799	phys = <&transceiver1>;
800};
801
802&main_mcan1 {
803	status = "okay";
804	pinctrl-names = "default";
805	pinctrl-0 = <&main_mcan1_pins_default>;
806	phys = <&transceiver2>;
807};
808
809&icssg1_mdio {
810	status = "okay";
811	pinctrl-names = "default";
812	pinctrl-0 = <&icssg1_mdio1_pins_default>;
813
814	icssg1_phy1: ethernet-phy@f {
815		reg = <0xf>;
816		tx-internal-delay-ps = <250>;
817		rx-internal-delay-ps = <2000>;
818	};
819};
820