1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/** 3 * DT overlay for enabling both ICSSG1 port on AM642 EVM in MII mode 4 * 5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8/dts-v1/; 9/plugin/; 10#include <dt-bindings/gpio/gpio.h> 11#include "k3-pinctrl.h" 12 13&{/} { 14 aliases { 15 ethernet1 = "/icssg1-eth/ethernet-ports/port@1"; 16 }; 17 18 mdio-mux-2 { 19 compatible = "mdio-mux-multiplexer"; 20 mux-controls = <&mdio_mux>; 21 mdio-parent-bus = <&icssg1_mdio>; 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 mdio@0 { 26 reg = <0x0>; 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 icssg1_phy2: ethernet-phy@3 { 31 reg = <3>; 32 }; 33 }; 34 }; 35}; 36 37&main_pmx0 { 38 icssg1_mii1_pins_default: icssg1-mii1-default-pins { 39 pinctrl-single,pins = < 40 AM64X_IOPAD(0x00f8, PIN_INPUT, 1) /* (V9) PRG1_PRU0_GPO16.PR1_MII_MT0_CLK */ 41 AM64X_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (Y9) PRG1_PRU0_GPO15.PR1_MII0_TXEN */ 42 AM64X_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (AA9) PRG1_PRU0_GPO14.PR1_MII0_TXD3 */ 43 AM64X_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (W9) PRG1_PRU0_GPO13.PR1_MII0_TXD2 */ 44 AM64X_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (U9) PRG1_PRU0_GPO12.PR1_MII0_TXD1 */ 45 AM64X_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AA8) PRG1_PRU0_GPO11.PR1_MII0_TXD0 */ 46 AM64X_IOPAD(0x00c8, PIN_INPUT, 1) /* (Y8) PRG1_PRU0_GPO4.PR1_MII0_RXDV */ 47 AM64X_IOPAD(0x00d0, PIN_INPUT, 1) /* (AA7) PRG1_PRU0_GPO6.PR1_MII_MR0_CLK */ 48 AM64X_IOPAD(0x00c4, PIN_INPUT, 1) /* (V8) PRG1_PRU0_GPO3.PR1_MII0_RXD3 */ 49 AM64X_IOPAD(0x00c0, PIN_INPUT, 1) /* (W8) PRG1_PRU0_GPO2.PR1_MII0_RXD2 */ 50 AM64X_IOPAD(0x00cc, PIN_INPUT, 1) /* (V13) PRG1_PRU0_GPO5.PR1_MII0_RXER */ 51 AM64X_IOPAD(0x00bc, PIN_INPUT, 1) /* (U8) PRG1_PRU0_GPO1.PR1_MII0_RXD1 */ 52 AM64X_IOPAD(0x00b8, PIN_INPUT, 1) /* (Y7) PRG1_PRU0_GPO0.PR1_MII0_RXD0 */ 53 AM64X_IOPAD(0x00d8, PIN_INPUT, 1) /* (W13) PRG1_PRU0_GPO8.PR1_MII0_RXLINK */ 54 >; 55 }; 56 57 icssg1_mii2_pins_default: icssg1-mii2-default-pins { 58 pinctrl-single,pins = < 59 AM64X_IOPAD(0x0148, PIN_INPUT, 1) /* (Y10) PRG1_PRU1_GPO16.PR1_MII_MT1_CLK */ 60 AM64X_IOPAD(0x0144, PIN_OUTPUT, 0) /* (Y11) PRG1_PRU1_GPO15.PR1_MII1_TXEN */ 61 AM64X_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AA11) PRG1_PRU1_GPO14.PR1_MII1_TXD3 */ 62 AM64X_IOPAD(0x013c, PIN_OUTPUT, 0) /* (U10) PRG1_PRU1_GPO13.PR1_MII1_TXD2 */ 63 AM64X_IOPAD(0x0138, PIN_OUTPUT, 0) /* (V10) PRG1_PRU1_GPO12.PR1_MII1_TXD1 */ 64 AM64X_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AA10) PRG1_PRU1_GPO11.PR1_MII1_TXD0 */ 65 AM64X_IOPAD(0x0118, PIN_INPUT, 1) /* (W12) PRG1_PRU1_GPO4.PR1_MII1_RXDV */ 66 AM64X_IOPAD(0x0120, PIN_INPUT, 1) /* (U11) PRG1_PRU1_GPO6.PR1_MII_MR1_CLK */ 67 AM64X_IOPAD(0x0114, PIN_INPUT, 1) /* (Y12) PRG1_PRU1_GPO3.PR1_MII1_RXD3 */ 68 AM64X_IOPAD(0x0110, PIN_INPUT, 1) /* (AA12) PRG1_PRU1_GPO2.PR1_MII1_RXD2 */ 69 AM64X_IOPAD(0x011c, PIN_INPUT, 1) /* (AA13) PRG1_PRU1_GPO5.PR1_MII1_RXER */ 70 AM64X_IOPAD(0x010c, PIN_INPUT, 1) /* (V11) PRG1_PRU1_GPO1.PR1_MII1_RXD1 */ 71 AM64X_IOPAD(0x0108, PIN_INPUT, 1) /* (W11) PRG1_PRU1_GPO0.PR1_MII1_RXD0 */ 72 AM64X_IOPAD(0x0128, PIN_INPUT, 1) /* (U12) PRG1_PRU1_GPO8.PR1_MII1_RXLINK */ 73 >; 74 }; 75}; 76 77&cpsw3g { 78 pinctrl-0 = <&rgmii1_pins_default>; 79}; 80 81&cpsw_port2 { 82 status = "disabled"; 83}; 84 85&mdio_mux_1 { 86 status = "disabled"; 87}; 88 89&icssg1_eth { 90 pinctrl-0 = <&icssg1_mii1_pins_default &icssg1_mii2_pins_default>; 91}; 92 93&icssg1_emac0 { 94 phy-mode = "mii"; 95}; 96 97&icssg1_emac1 { 98 status = "okay"; 99 phy-handle = <&icssg1_phy2>; 100 phy-mode = "mii"; 101}; 102