1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/** 3 * Device Tree Source for enabling IPC using TI SDK firmware on AM64 SoCs 4 * 5 * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&reserved_memory { 9 main_r5fss0_core1_dma_memory_region: memory@a1000000 { 10 compatible = "shared-dma-pool"; 11 reg = <0x00 0xa1000000 0x00 0x100000>; 12 no-map; 13 }; 14 15 main_r5fss0_core1_memory_region: memory@a1100000 { 16 compatible = "shared-dma-pool"; 17 reg = <0x00 0xa1100000 0x00 0xf00000>; 18 no-map; 19 }; 20 21 main_r5fss1_core0_dma_memory_region: memory@a2000000 { 22 compatible = "shared-dma-pool"; 23 reg = <0x00 0xa2000000 0x00 0x100000>; 24 no-map; 25 }; 26 27 main_r5fss1_core0_memory_region: memory@a2100000 { 28 compatible = "shared-dma-pool"; 29 reg = <0x00 0xa2100000 0x00 0xf00000>; 30 no-map; 31 }; 32 33 main_r5fss1_core1_dma_memory_region: memory@a3000000 { 34 compatible = "shared-dma-pool"; 35 reg = <0x00 0xa3000000 0x00 0x100000>; 36 no-map; 37 }; 38 39 main_r5fss1_core1_memory_region: memory@a3100000 { 40 compatible = "shared-dma-pool"; 41 reg = <0x00 0xa3100000 0x00 0xf00000>; 42 no-map; 43 }; 44 45 mcu_m4fss_dma_memory_region: memory@a4000000 { 46 compatible = "shared-dma-pool"; 47 reg = <0x00 0xa4000000 0x00 0x100000>; 48 no-map; 49 }; 50 51 mcu_m4fss_memory_region: memory@a4100000 { 52 compatible = "shared-dma-pool"; 53 reg = <0x00 0xa4100000 0x00 0xf00000>; 54 no-map; 55 }; 56 57 rtos_ipc_memory_region: memory@a5000000 { 58 reg = <0x00 0xa5000000 0x00 0x00800000>; 59 alignment = <0x1000>; 60 no-map; 61 }; 62}; 63 64&mailbox0_cluster2 { 65 status = "okay"; 66 67 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 68 ti,mbox-rx = <0 0 2>; 69 ti,mbox-tx = <1 0 2>; 70 }; 71 72 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 73 ti,mbox-rx = <2 0 2>; 74 ti,mbox-tx = <3 0 2>; 75 }; 76}; 77 78&mailbox0_cluster4 { 79 status = "okay"; 80 81 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 82 ti,mbox-rx = <0 0 2>; 83 ti,mbox-tx = <1 0 2>; 84 }; 85 86 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 87 ti,mbox-rx = <2 0 2>; 88 ti,mbox-tx = <3 0 2>; 89 }; 90}; 91 92&mailbox0_cluster6 { 93 status = "okay"; 94 95 mbox_m4_0: mbox-m4-0 { 96 ti,mbox-rx = <0 0 2>; 97 ti,mbox-tx = <1 0 2>; 98 }; 99}; 100 101/* main_timer8 is used by r5f0-0 */ 102&main_timer8 { 103 status = "reserved"; 104}; 105 106/* main_timer9 is used by r5f0-1 */ 107&main_timer9 { 108 status = "reserved"; 109}; 110 111/* main_timer10 is used by r5f1-0 */ 112&main_timer10 { 113 status = "reserved"; 114}; 115 116/* main_timer11 is used by r5f1-1 */ 117&main_timer11 { 118 status = "reserved"; 119}; 120 121&main_r5fss0 { 122 status = "okay"; 123}; 124 125&main_r5fss0_core0 { 126 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; 127 memory-region = <&main_r5fss0_core0_dma_memory_region>, 128 <&main_r5fss0_core0_memory_region>; 129 status = "okay"; 130}; 131 132&main_r5fss0_core1 { 133 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; 134 memory-region = <&main_r5fss0_core1_dma_memory_region>, 135 <&main_r5fss0_core1_memory_region>; 136 status = "okay"; 137}; 138 139&main_r5fss1 { 140 status = "okay"; 141}; 142 143&main_r5fss1_core0 { 144 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; 145 memory-region = <&main_r5fss1_core0_dma_memory_region>, 146 <&main_r5fss1_core0_memory_region>; 147 status = "okay"; 148}; 149 150&main_r5fss1_core1 { 151 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; 152 memory-region = <&main_r5fss1_core1_dma_memory_region>, 153 <&main_r5fss1_core1_memory_region>; 154 status = "okay"; 155}; 156 157&mcu_m4fss { 158 mboxes = <&mailbox0_cluster6 &mbox_m4_0>; 159 memory-region = <&mcu_m4fss_dma_memory_region>, 160 <&mcu_m4fss_memory_region>; 161 status = "okay"; 162}; 163