1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Copyright (C) 2021-2024 PHYTEC America, LLC - https://www.phytec.com 4 * Author: Matt McKee <mmckee@phytec.com> 5 * 6 * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH 7 * Author: Wadim Egorov <w.egorov@phytec.de> 8 * 9 * Product homepage: 10 * https://www.phytec.com/product/phycore-am64x 11 */ 12 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/leds/common.h> 15#include <dt-bindings/net/ti-dp83867.h> 16 17/ { 18 model = "PHYTEC phyCORE-AM64x"; 19 compatible = "phytec,am64-phycore-som", "ti,am642"; 20 21 aliases { 22 ethernet0 = &cpsw_port1; 23 mmc0 = &sdhci0; 24 rtc0 = &i2c_som_rtc; 25 }; 26 27 memory@80000000 { 28 device_type = "memory"; 29 reg = <0x00000000 0x80000000 0x00000000 0x80000000>; 30 }; 31 32 reserved_memory: reserved-memory { 33 #address-cells = <2>; 34 #size-cells = <2>; 35 ranges; 36 37 secure_ddr: optee@9e800000 { 38 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ 39 alignment = <0x1000>; 40 no-map; 41 }; 42 43 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 44 compatible = "shared-dma-pool"; 45 reg = <0x00 0xa0000000 0x00 0x100000>; 46 no-map; 47 }; 48 49 main_r5fss0_core0_memory_region: r5f-memory@a0100000 { 50 compatible = "shared-dma-pool"; 51 reg = <0x00 0xa0100000 0x00 0xf00000>; 52 no-map; 53 }; 54 55 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 56 compatible = "shared-dma-pool"; 57 reg = <0x00 0xa1000000 0x00 0x100000>; 58 no-map; 59 }; 60 61 main_r5fss0_core1_memory_region: r5f-memory@a1100000 { 62 compatible = "shared-dma-pool"; 63 reg = <0x00 0xa1100000 0x00 0xf00000>; 64 no-map; 65 }; 66 67 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { 68 compatible = "shared-dma-pool"; 69 reg = <0x00 0xa2000000 0x00 0x100000>; 70 no-map; 71 }; 72 73 main_r5fss1_core0_memory_region: r5f-memory@a2100000 { 74 compatible = "shared-dma-pool"; 75 reg = <0x00 0xa2100000 0x00 0xf00000>; 76 no-map; 77 }; 78 79 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { 80 compatible = "shared-dma-pool"; 81 reg = <0x00 0xa3000000 0x00 0x100000>; 82 no-map; 83 }; 84 85 main_r5fss1_core1_memory_region: r5f-memory@a3100000 { 86 compatible = "shared-dma-pool"; 87 reg = <0x00 0xa3100000 0x00 0xf00000>; 88 no-map; 89 }; 90 91 mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 { 92 compatible = "shared-dma-pool"; 93 reg = <0x00 0xa4000000 0x00 0x100000>; 94 no-map; 95 }; 96 97 mcu_m4fss_memory_region: m4f-memory@a4100000 { 98 compatible = "shared-dma-pool"; 99 reg = <0x00 0xa4100000 0x00 0xf00000>; 100 no-map; 101 }; 102 }; 103 104 leds { 105 compatible = "gpio-leds"; 106 pinctrl-names = "default"; 107 pinctrl-0 = <&leds_pins_default>; 108 109 led-0 { 110 color = <LED_COLOR_ID_GREEN>; 111 gpios = <&main_gpio0 12 GPIO_ACTIVE_HIGH>; 112 linux,default-trigger = "heartbeat"; 113 function = LED_FUNCTION_HEARTBEAT; 114 }; 115 }; 116 117 vcc_5v0_som: regulator-vcc-5v0-som { 118 /* VIN / VCC_5V0_SOM */ 119 compatible = "regulator-fixed"; 120 regulator-name = "VCC_5V0_SOM"; 121 regulator-min-microvolt = <5000000>; 122 regulator-max-microvolt = <5000000>; 123 regulator-always-on; 124 regulator-boot-on; 125 }; 126}; 127 128&main_pmx0 { 129 cpsw_mdio_pins_default: cpsw-mdio-default-pins { 130 pinctrl-single,pins = < 131 AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ 132 AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ 133 AM64X_IOPAD(0x0100, PIN_OUTPUT, 7) /* (V7) PRG1_PRU0_GPO18.GPIO0_63 */ 134 >; 135 }; 136 137 cpsw_rgmii1_pins_default: cpsw-rgmii1-default-pins { 138 pinctrl-single,pins = < 139 AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */ 140 AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */ 141 AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ 142 AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */ 143 AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */ 144 AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */ 145 AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */ 146 AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */ 147 AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */ 148 AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */ 149 AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */ 150 AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ 151 AM64X_IOPAD(0x0154, PIN_INPUT, 7) /* (V12) PRG1_PRU1_GPO19.GPIO0_84 */ 152 >; 153 }; 154 155 eeprom_wp_pins_default: eeprom-wp-default-pins { 156 pinctrl-single,pins = < 157 AM64X_IOPAD(0x0208, PIN_OUTPUT, 7) /* (D12) SPI0_CS0.GPIO1_42 */ 158 >; 159 }; 160 161 leds_pins_default: leds-default-pins { 162 pinctrl-single,pins = < 163 AM64X_IOPAD(0x0030, PIN_OUTPUT, 7) /* (L18) OSPI0_CSn1.GPIO0_12 */ 164 >; 165 }; 166 167 main_i2c0_pins_default: main-i2c0-default-pins { 168 pinctrl-single,pins = < 169 AM64X_IOPAD(0x0260, PIN_INPUT, 0) /* (A18) I2C0_SCL */ 170 AM64X_IOPAD(0x0264, PIN_INPUT, 0) /* (B18) I2C0_SDA */ 171 >; 172 }; 173 174 ospi0_pins_default: ospi0-default-pins { 175 pinctrl-single,pins = < 176 AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ 177 AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ 178 AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */ 179 AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */ 180 AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */ 181 AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */ 182 AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */ 183 AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */ 184 AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */ 185 AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ 186 AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ 187 >; 188 }; 189 190 rtc_pins_default: rtc-defaults-pins { 191 pinctrl-single,pins = < 192 AM64X_IOPAD(0x0278, PIN_INPUT, 7) /* (C19) EXTINTn.GPIO1_70 */ 193 >; 194 }; 195}; 196 197&cpsw3g { 198 pinctrl-names = "default"; 199 pinctrl-0 = <&cpsw_rgmii1_pins_default>; 200 status = "okay"; 201}; 202 203&cpsw3g_mdio { 204 status = "okay"; 205 pinctrl-names = "default"; 206 pinctrl-0 = <&cpsw_mdio_pins_default>; 207 208 cpsw3g_phy1: ethernet-phy@1 { 209 compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; 210 reg = <1>; 211 interrupt-parent = <&main_gpio0>; 212 interrupts = <84 IRQ_TYPE_EDGE_FALLING>; 213 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 214 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 215 reset-gpios = <&main_gpio0 63 GPIO_ACTIVE_LOW>; 216 reset-assert-us = <1000>; 217 reset-deassert-us = <1000>; 218 }; 219}; 220 221&cpsw_port1 { 222 phy-mode = "rgmii-rxid"; 223 phy-handle = <&cpsw3g_phy1>; 224 status = "okay"; 225}; 226 227&mailbox0_cluster2 { 228 status = "okay"; 229 230 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 231 ti,mbox-rx = <0 0 2>; 232 ti,mbox-tx = <1 0 2>; 233 }; 234 235 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 236 ti,mbox-rx = <2 0 2>; 237 ti,mbox-tx = <3 0 2>; 238 }; 239}; 240 241&mailbox0_cluster4 { 242 status = "okay"; 243 244 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 245 ti,mbox-rx = <0 0 2>; 246 ti,mbox-tx = <1 0 2>; 247 }; 248 249 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 250 ti,mbox-rx = <2 0 2>; 251 ti,mbox-tx = <3 0 2>; 252 }; 253}; 254 255&mailbox0_cluster6 { 256 status = "okay"; 257 258 mbox_m4_0: mbox-m4-0 { 259 ti,mbox-rx = <0 0 2>; 260 ti,mbox-tx = <1 0 2>; 261 }; 262}; 263 264&main_i2c0 { 265 status = "okay"; 266 pinctrl-names = "default"; 267 pinctrl-0 = <&main_i2c0_pins_default>; 268 clock-frequency = <400000>; 269 270 eeprom@50 { 271 compatible = "atmel,24c32"; 272 pinctrl-names = "default"; 273 pinctrl-0 = <&eeprom_wp_pins_default>; 274 pagesize = <32>; 275 reg = <0x50>; 276 }; 277 278 i2c_som_rtc: rtc@52 { 279 compatible = "microcrystal,rv3028"; 280 reg = <0x52>; 281 pinctrl-names = "default"; 282 pinctrl-0 = <&rtc_pins_default>; 283 interrupt-parent = <&main_gpio1>; 284 interrupts = <70 IRQ_TYPE_EDGE_FALLING>; 285 wakeup-source; 286 }; 287 288 pmic@61 { 289 compatible = "ti,lp8733"; 290 reg = <0x61>; 291 292 buck0-in-supply = <&vcc_5v0_som>; 293 buck1-in-supply = <&vcc_5v0_som>; 294 ldo0-in-supply = <&vdd_3v3>; 295 ldo1-in-supply = <&vdd_3v3>; 296 297 regulators { 298 vdd_core: buck0 { 299 regulator-name = "VDD_CORE"; 300 regulator-min-microvolt = <750000>; 301 regulator-max-microvolt = <750000>; 302 regulator-always-on; 303 regulator-boot-on; 304 }; 305 306 vdd_3v3: buck1 { 307 regulator-name = "VDD_3V3"; 308 regulator-min-microvolt = <3300000>; 309 regulator-max-microvolt = <3300000>; 310 regulator-always-on; 311 regulator-boot-on; 312 }; 313 314 vdd_1v8_ldo0: ldo0 { 315 regulator-name = "VDD_1V8_LDO0"; 316 regulator-min-microvolt = <1800000>; 317 regulator-max-microvolt = <1800000>; 318 regulator-always-on; 319 regulator-boot-on; 320 }; 321 322 vdda_1v8: ldo1 { 323 regulator-name = "VDDA_1V8"; 324 regulator-min-microvolt = <1800000>; 325 regulator-max-microvolt = <1800000>; 326 regulator-always-on; 327 regulator-boot-on; 328 }; 329 }; 330 }; 331}; 332 333&main_r5fss0_core0 { 334 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; 335 memory-region = <&main_r5fss0_core0_dma_memory_region>, 336 <&main_r5fss0_core0_memory_region>; 337}; 338 339&main_r5fss0_core1 { 340 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; 341 memory-region = <&main_r5fss0_core1_dma_memory_region>, 342 <&main_r5fss0_core1_memory_region>; 343}; 344 345&main_r5fss1_core0 { 346 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; 347 memory-region = <&main_r5fss1_core0_dma_memory_region>, 348 <&main_r5fss1_core0_memory_region>; 349}; 350 351&main_r5fss1_core1 { 352 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; 353 memory-region = <&main_r5fss1_core1_dma_memory_region>, 354 <&main_r5fss1_core1_memory_region>; 355}; 356 357&mcu_m4fss { 358 mboxes = <&mailbox0_cluster6 &mbox_m4_0>; 359 memory-region = <&mcu_m4fss_dma_memory_region>, 360 <&mcu_m4fss_memory_region>; 361 status = "okay"; 362}; 363 364&ospi0 { 365 status = "okay"; 366 pinctrl-names = "default"; 367 pinctrl-0 = <&ospi0_pins_default>; 368 369 serial_flash: flash@0 { 370 compatible = "jedec,spi-nor"; 371 reg = <0x0>; 372 spi-tx-bus-width = <8>; 373 spi-rx-bus-width = <8>; 374 spi-max-frequency = <25000000>; 375 cdns,tshsl-ns = <60>; 376 cdns,tsd2d-ns = <60>; 377 cdns,tchsh-ns = <60>; 378 cdns,tslch-ns = <60>; 379 cdns,read-delay = <0>; 380 }; 381}; 382 383&sdhci0 { 384 status = "okay"; 385 non-removable; 386 ti,driver-strength-ohm = <50>; 387 disable-wp; 388 keep-power-in-suspend; 389}; 390 391&tscadc0 { 392 status = "okay"; 393 adc { 394 ti,adc-channels = <0 1 2 3 4 5 6 7>; 395 }; 396}; 397