1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM64 SoC Family MCU Domain peripherals 4 * 5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu { 9 /* 10 * The MCU domain timer interrupts are routed only to the ESM module, 11 * and not currently available for Linux. The MCU domain timers are 12 * of limited use without interrupts, and likely reserved by the ESM. 13 */ 14 mcu_timer0: timer@4800000 { 15 compatible = "ti,am654-timer"; 16 reg = <0x00 0x4800000 0x00 0x400>; 17 clocks = <&k3_clks 35 1>; 18 clock-names = "fck"; 19 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 20 ti,timer-pwm; 21 status = "reserved"; 22 }; 23 24 mcu_timer1: timer@4810000 { 25 compatible = "ti,am654-timer"; 26 reg = <0x00 0x4810000 0x00 0x400>; 27 clocks = <&k3_clks 48 1>; 28 clock-names = "fck"; 29 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; 30 ti,timer-pwm; 31 status = "reserved"; 32 }; 33 34 mcu_timer2: timer@4820000 { 35 compatible = "ti,am654-timer"; 36 reg = <0x00 0x4820000 0x00 0x400>; 37 clocks = <&k3_clks 49 1>; 38 clock-names = "fck"; 39 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; 40 ti,timer-pwm; 41 status = "reserved"; 42 }; 43 44 mcu_timer3: timer@4830000 { 45 compatible = "ti,am654-timer"; 46 reg = <0x00 0x4830000 0x00 0x400>; 47 clocks = <&k3_clks 50 1>; 48 clock-names = "fck"; 49 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; 50 ti,timer-pwm; 51 status = "reserved"; 52 }; 53 54 mcu_uart0: serial@4a00000 { 55 compatible = "ti,am64-uart", "ti,am654-uart"; 56 reg = <0x00 0x04a00000 0x00 0x100>; 57 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 58 current-speed = <115200>; 59 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 60 clocks = <&k3_clks 149 0>; 61 clock-names = "fclk"; 62 status = "disabled"; 63 }; 64 65 mcu_uart1: serial@4a10000 { 66 compatible = "ti,am64-uart", "ti,am654-uart"; 67 reg = <0x00 0x04a10000 0x00 0x100>; 68 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 69 current-speed = <115200>; 70 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; 71 clocks = <&k3_clks 160 0>; 72 clock-names = "fclk"; 73 status = "disabled"; 74 }; 75 76 mcu_i2c0: i2c@4900000 { 77 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 78 reg = <0x00 0x04900000 0x00 0x100>; 79 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 80 #address-cells = <1>; 81 #size-cells = <0>; 82 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 83 clocks = <&k3_clks 106 2>; 84 clock-names = "fck"; 85 status = "disabled"; 86 }; 87 88 mcu_i2c1: i2c@4910000 { 89 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 90 reg = <0x00 0x04910000 0x00 0x100>; 91 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 92 #address-cells = <1>; 93 #size-cells = <0>; 94 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 95 clocks = <&k3_clks 107 2>; 96 clock-names = "fck"; 97 status = "disabled"; 98 }; 99 100 mcu_spi0: spi@4b00000 { 101 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 102 reg = <0x00 0x04b00000 0x00 0x400>; 103 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 104 #address-cells = <1>; 105 #size-cells = <0>; 106 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; 107 clocks = <&k3_clks 147 0>; 108 status = "disabled"; 109 }; 110 111 mcu_spi1: spi@4b10000 { 112 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 113 reg = <0x00 0x04b10000 0x00 0x400>; 114 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 115 #address-cells = <1>; 116 #size-cells = <0>; 117 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; 118 clocks = <&k3_clks 148 0>; 119 status = "disabled"; 120 }; 121 122 mcu_gpio_intr: interrupt-controller@4210000 { 123 compatible = "ti,sci-intr"; 124 reg = <0x00 0x04210000 0x00 0x200>; 125 ti,intr-trigger-type = <1>; 126 interrupt-controller; 127 interrupt-parent = <&gic500>; 128 #interrupt-cells = <1>; 129 ti,sci = <&dmsc>; 130 ti,sci-dev-id = <5>; 131 ti,interrupt-ranges = <0 104 4>; 132 }; 133 134 mcu_gpio0: gpio@4201000 { 135 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 136 reg = <0x0 0x4201000 0x0 0x100>; 137 gpio-controller; 138 #gpio-cells = <2>; 139 interrupt-parent = <&mcu_gpio_intr>; 140 interrupts = <30>, <31>; 141 interrupt-controller; 142 #interrupt-cells = <2>; 143 ti,ngpio = <23>; 144 ti,davinci-gpio-unbanked = <0>; 145 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; 146 clocks = <&k3_clks 79 0>; 147 clock-names = "gpio"; 148 }; 149 150 mcu_pmx0: pinctrl@4084000 { 151 compatible = "pinctrl-single"; 152 reg = <0x00 0x4084000 0x00 0x84>; 153 #pinctrl-cells = <1>; 154 pinctrl-single,register-width = <32>; 155 pinctrl-single,function-mask = <0xffffffff>; 156 }; 157}; 158