18abae938SDave Gerlach// SPDX-License-Identifier: GPL-2.0 28abae938SDave Gerlach/* 38abae938SDave Gerlach * Device Tree Source for AM64 SoC Family MCU Domain peripherals 48abae938SDave Gerlach * 58abae938SDave Gerlach * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 68abae938SDave Gerlach */ 78abae938SDave Gerlach 88abae938SDave Gerlach&cbass_mcu { 9*9972b457SNishanth Menon /* 10*9972b457SNishanth Menon * The MCU domain timer interrupts are routed only to the ESM module, 11*9972b457SNishanth Menon * and not currently available for Linux. The MCU domain timers are 12*9972b457SNishanth Menon * of limited use without interrupts, and likely reserved by the ESM. 13*9972b457SNishanth Menon */ 14*9972b457SNishanth Menon mcu_timer0: timer@4800000 { 15*9972b457SNishanth Menon compatible = "ti,am654-timer"; 16*9972b457SNishanth Menon reg = <0x00 0x4800000 0x00 0x400>; 17*9972b457SNishanth Menon clocks = <&k3_clks 35 1>; 18*9972b457SNishanth Menon clock-names = "fck"; 19*9972b457SNishanth Menon power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 20*9972b457SNishanth Menon ti,timer-pwm; 21*9972b457SNishanth Menon status = "reserved"; 22*9972b457SNishanth Menon }; 23*9972b457SNishanth Menon 24*9972b457SNishanth Menon mcu_timer1: timer@4810000 { 25*9972b457SNishanth Menon compatible = "ti,am654-timer"; 26*9972b457SNishanth Menon reg = <0x00 0x4810000 0x00 0x400>; 27*9972b457SNishanth Menon clocks = <&k3_clks 48 1>; 28*9972b457SNishanth Menon clock-names = "fck"; 29*9972b457SNishanth Menon power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; 30*9972b457SNishanth Menon ti,timer-pwm; 31*9972b457SNishanth Menon status = "reserved"; 32*9972b457SNishanth Menon }; 33*9972b457SNishanth Menon 34*9972b457SNishanth Menon mcu_timer2: timer@4820000 { 35*9972b457SNishanth Menon compatible = "ti,am654-timer"; 36*9972b457SNishanth Menon reg = <0x00 0x4820000 0x00 0x400>; 37*9972b457SNishanth Menon clocks = <&k3_clks 49 1>; 38*9972b457SNishanth Menon clock-names = "fck"; 39*9972b457SNishanth Menon power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; 40*9972b457SNishanth Menon ti,timer-pwm; 41*9972b457SNishanth Menon status = "reserved"; 42*9972b457SNishanth Menon }; 43*9972b457SNishanth Menon 44*9972b457SNishanth Menon mcu_timer3: timer@4830000 { 45*9972b457SNishanth Menon compatible = "ti,am654-timer"; 46*9972b457SNishanth Menon reg = <0x00 0x4830000 0x00 0x400>; 47*9972b457SNishanth Menon clocks = <&k3_clks 50 1>; 48*9972b457SNishanth Menon clock-names = "fck"; 49*9972b457SNishanth Menon power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; 50*9972b457SNishanth Menon ti,timer-pwm; 51*9972b457SNishanth Menon status = "reserved"; 52*9972b457SNishanth Menon }; 53*9972b457SNishanth Menon 548abae938SDave Gerlach mcu_uart0: serial@4a00000 { 558abae938SDave Gerlach compatible = "ti,am64-uart", "ti,am654-uart"; 568abae938SDave Gerlach reg = <0x00 0x04a00000 0x00 0x100>; 578abae938SDave Gerlach interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 588abae938SDave Gerlach current-speed = <115200>; 598abae938SDave Gerlach power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 608abae938SDave Gerlach clocks = <&k3_clks 149 0>; 618abae938SDave Gerlach clock-names = "fclk"; 62dacf4705SAndrew Davis status = "disabled"; 638abae938SDave Gerlach }; 648abae938SDave Gerlach 658abae938SDave Gerlach mcu_uart1: serial@4a10000 { 668abae938SDave Gerlach compatible = "ti,am64-uart", "ti,am654-uart"; 678abae938SDave Gerlach reg = <0x00 0x04a10000 0x00 0x100>; 688abae938SDave Gerlach interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 698abae938SDave Gerlach current-speed = <115200>; 708abae938SDave Gerlach power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; 718abae938SDave Gerlach clocks = <&k3_clks 160 0>; 728abae938SDave Gerlach clock-names = "fclk"; 73dacf4705SAndrew Davis status = "disabled"; 748abae938SDave Gerlach }; 758abae938SDave Gerlach 768abae938SDave Gerlach mcu_i2c0: i2c@4900000 { 778abae938SDave Gerlach compatible = "ti,am64-i2c", "ti,omap4-i2c"; 788abae938SDave Gerlach reg = <0x00 0x04900000 0x00 0x100>; 798abae938SDave Gerlach interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 808abae938SDave Gerlach #address-cells = <1>; 818abae938SDave Gerlach #size-cells = <0>; 828abae938SDave Gerlach power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 838abae938SDave Gerlach clocks = <&k3_clks 106 2>; 848abae938SDave Gerlach clock-names = "fck"; 85b80f75d8SAndrew Davis status = "disabled"; 868abae938SDave Gerlach }; 878abae938SDave Gerlach 888abae938SDave Gerlach mcu_i2c1: i2c@4910000 { 898abae938SDave Gerlach compatible = "ti,am64-i2c", "ti,omap4-i2c"; 908abae938SDave Gerlach reg = <0x00 0x04910000 0x00 0x100>; 918abae938SDave Gerlach interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 928abae938SDave Gerlach #address-cells = <1>; 938abae938SDave Gerlach #size-cells = <0>; 948abae938SDave Gerlach power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 958abae938SDave Gerlach clocks = <&k3_clks 107 2>; 968abae938SDave Gerlach clock-names = "fck"; 97b80f75d8SAndrew Davis status = "disabled"; 988abae938SDave Gerlach }; 998abae938SDave Gerlach 1008abae938SDave Gerlach mcu_spi0: spi@4b00000 { 1018abae938SDave Gerlach compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 1028abae938SDave Gerlach reg = <0x00 0x04b00000 0x00 0x400>; 1038abae938SDave Gerlach interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1048abae938SDave Gerlach #address-cells = <1>; 1058abae938SDave Gerlach #size-cells = <0>; 1068abae938SDave Gerlach power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; 1078abae938SDave Gerlach clocks = <&k3_clks 147 0>; 10879d4aa62SAndrew Davis status = "disabled"; 1098abae938SDave Gerlach }; 1108abae938SDave Gerlach 1118abae938SDave Gerlach mcu_spi1: spi@4b10000 { 1128abae938SDave Gerlach compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1138abae938SDave Gerlach reg = <0x00 0x04b10000 0x00 0x400>; 1148abae938SDave Gerlach interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 1158abae938SDave Gerlach #address-cells = <1>; 1168abae938SDave Gerlach #size-cells = <0>; 1178abae938SDave Gerlach power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; 1188abae938SDave Gerlach clocks = <&k3_clks 148 0>; 11979d4aa62SAndrew Davis status = "disabled"; 1208abae938SDave Gerlach }; 12101a91e01SAswath Govindraju 122cab12badSNishanth Menon mcu_gpio_intr: interrupt-controller@4210000 { 12301a91e01SAswath Govindraju compatible = "ti,sci-intr"; 124cab12badSNishanth Menon reg = <0x00 0x04210000 0x00 0x200>; 12501a91e01SAswath Govindraju ti,intr-trigger-type = <1>; 12601a91e01SAswath Govindraju interrupt-controller; 12701a91e01SAswath Govindraju interrupt-parent = <&gic500>; 12801a91e01SAswath Govindraju #interrupt-cells = <1>; 12901a91e01SAswath Govindraju ti,sci = <&dmsc>; 13001a91e01SAswath Govindraju ti,sci-dev-id = <5>; 13101a91e01SAswath Govindraju ti,interrupt-ranges = <0 104 4>; 13201a91e01SAswath Govindraju }; 13301a91e01SAswath Govindraju 13401a91e01SAswath Govindraju mcu_gpio0: gpio@4201000 { 135ec2fb989SAswath Govindraju compatible = "ti,am64-gpio", "ti,keystone-gpio"; 13601a91e01SAswath Govindraju reg = <0x0 0x4201000 0x0 0x100>; 13701a91e01SAswath Govindraju gpio-controller; 13801a91e01SAswath Govindraju #gpio-cells = <2>; 13901a91e01SAswath Govindraju interrupt-parent = <&mcu_gpio_intr>; 14001a91e01SAswath Govindraju interrupts = <30>, <31>; 14101a91e01SAswath Govindraju interrupt-controller; 14201a91e01SAswath Govindraju #interrupt-cells = <2>; 14301a91e01SAswath Govindraju ti,ngpio = <23>; 14401a91e01SAswath Govindraju ti,davinci-gpio-unbanked = <0>; 14501a91e01SAswath Govindraju power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; 14601a91e01SAswath Govindraju clocks = <&k3_clks 79 0>; 14701a91e01SAswath Govindraju clock-names = "gpio"; 14801a91e01SAswath Govindraju }; 149500e6dfbSChristian Gmeiner 150500e6dfbSChristian Gmeiner mcu_pmx0: pinctrl@4084000 { 151500e6dfbSChristian Gmeiner compatible = "pinctrl-single"; 152500e6dfbSChristian Gmeiner reg = <0x00 0x4084000 0x00 0x84>; 153500e6dfbSChristian Gmeiner #pinctrl-cells = <1>; 154500e6dfbSChristian Gmeiner pinctrl-single,register-width = <32>; 155500e6dfbSChristian Gmeiner pinctrl-single,function-mask = <0xffffffff>; 156500e6dfbSChristian Gmeiner }; 1578abae938SDave Gerlach}; 158