1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for AM642 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/phy/phy-cadence.h> 9#include <dt-bindings/phy/phy-ti.h> 10 11/ { 12 serdes_refclk: clock-cmnrefclk { 13 #clock-cells = <0>; 14 compatible = "fixed-clock"; 15 clock-frequency = <0>; 16 }; 17}; 18 19&cbass_main { 20 oc_sram: sram@70000000 { 21 compatible = "mmio-sram"; 22 reg = <0x00 0x70000000 0x00 0x200000>; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 ranges = <0x0 0x00 0x70000000 0x200000>; 26 27 tfa-sram@1c0000 { 28 reg = <0x1c0000 0x20000>; 29 }; 30 31 dmsc-sram@1e0000 { 32 reg = <0x1e0000 0x1c000>; 33 }; 34 35 sproxy-sram@1fc000 { 36 reg = <0x1fc000 0x4000>; 37 }; 38 }; 39 40 main_conf: syscon@43000000 { 41 bootph-all; 42 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 43 reg = <0x0 0x43000000 0x0 0x20000>; 44 #address-cells = <1>; 45 #size-cells = <1>; 46 ranges = <0x0 0x0 0x43000000 0x20000>; 47 48 chipid@14 { 49 bootph-all; 50 compatible = "ti,am654-chipid"; 51 reg = <0x00000014 0x4>; 52 }; 53 54 pcie0_ctrl: pcie-ctrl@4070 { 55 compatible = "ti,j784s4-pcie-ctrl", "syscon"; 56 reg = <0x4070 0x4>; 57 }; 58 59 serdes_ln_ctrl: mux-controller@4080 { 60 compatible = "reg-mux"; 61 reg = <0x4080 0x4>; 62 #mux-control-cells = <1>; 63 mux-reg-masks = <0x0 0x3>; /* SERDES0 lane0 select */ 64 }; 65 66 phy_gmii_sel: phy@4044 { 67 compatible = "ti,am654-phy-gmii-sel"; 68 reg = <0x4044 0x8>; 69 #phy-cells = <1>; 70 }; 71 72 epwm_tbclk: clock-controller@4130 { 73 compatible = "ti,am64-epwm-tbclk"; 74 reg = <0x4130 0x4>; 75 #clock-cells = <1>; 76 }; 77 }; 78 79 gic500: interrupt-controller@1800000 { 80 compatible = "arm,gic-v3"; 81 #address-cells = <2>; 82 #size-cells = <2>; 83 ranges; 84 #interrupt-cells = <3>; 85 interrupt-controller; 86 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 87 <0x00 0x01840000 0x00 0xC0000>, /* GICR */ 88 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 89 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 90 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 91 /* 92 * vcpumntirq: 93 * virtual CPU interface maintenance interrupt 94 */ 95 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 96 97 gic_its: msi-controller@1820000 { 98 compatible = "arm,gic-v3-its"; 99 reg = <0x00 0x01820000 0x00 0x10000>; 100 socionext,synquacer-pre-its = <0x1000000 0x400000>; 101 msi-controller; 102 #msi-cells = <1>; 103 }; 104 }; 105 106 dmss: bus@48000000 { 107 bootph-all; 108 compatible = "simple-bus"; 109 #address-cells = <2>; 110 #size-cells = <2>; 111 dma-ranges; 112 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; 113 114 ti,sci-dev-id = <25>; 115 116 secure_proxy_main: mailbox@4d000000 { 117 bootph-all; 118 compatible = "ti,am654-secure-proxy"; 119 #mbox-cells = <1>; 120 reg-names = "target_data", "rt", "scfg"; 121 reg = <0x00 0x4d000000 0x00 0x80000>, 122 <0x00 0x4a600000 0x00 0x80000>, 123 <0x00 0x4a400000 0x00 0x80000>; 124 interrupt-names = "rx_012"; 125 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 126 }; 127 128 inta_main_dmss: interrupt-controller@48000000 { 129 compatible = "ti,sci-inta"; 130 reg = <0x00 0x48000000 0x00 0x100000>; 131 #interrupt-cells = <0>; 132 interrupt-controller; 133 interrupt-parent = <&gic500>; 134 msi-controller; 135 ti,sci = <&dmsc>; 136 ti,sci-dev-id = <28>; 137 ti,interrupt-ranges = <4 68 36>; 138 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 139 }; 140 141 main_bcdma: dma-controller@485c0100 { 142 compatible = "ti,am64-dmss-bcdma"; 143 reg = <0x00 0x485c0100 0x00 0x100>, 144 <0x00 0x4c000000 0x00 0x20000>, 145 <0x00 0x4a820000 0x00 0x20000>, 146 <0x00 0x4aa40000 0x00 0x20000>, 147 <0x00 0x4bc00000 0x00 0x100000>, 148 <0x00 0x48600000 0x00 0x8000>, 149 <0x00 0x484a4000 0x00 0x2000>, 150 <0x00 0x484c2000 0x00 0x2000>, 151 <0x00 0x48420000 0x00 0x2000>; 152 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt", 153 "ring", "tchan", "rchan", "bchan"; 154 msi-parent = <&inta_main_dmss>; 155 #dma-cells = <3>; 156 157 ti,sci = <&dmsc>; 158 ti,sci-dev-id = <26>; 159 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 160 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 161 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 162 }; 163 164 main_pktdma: dma-controller@485c0000 { 165 compatible = "ti,am64-dmss-pktdma"; 166 reg = <0x00 0x485c0000 0x00 0x100>, 167 <0x00 0x4a800000 0x00 0x20000>, 168 <0x00 0x4aa00000 0x00 0x40000>, 169 <0x00 0x4b800000 0x00 0x400000>, 170 <0x00 0x485e0000 0x00 0x20000>, 171 <0x00 0x484a0000 0x00 0x4000>, 172 <0x00 0x484c0000 0x00 0x2000>, 173 <0x00 0x48430000 0x00 0x4000>; 174 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", 175 "ring", "tchan", "rchan", "rflow"; 176 msi-parent = <&inta_main_dmss>; 177 #dma-cells = <2>; 178 179 ti,sci = <&dmsc>; 180 ti,sci-dev-id = <30>; 181 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 182 <0x24>, /* CPSW_TX_CHAN */ 183 <0x25>, /* SAUL_TX_0_CHAN */ 184 <0x26>, /* SAUL_TX_1_CHAN */ 185 <0x27>, /* ICSSG_0_TX_CHAN */ 186 <0x28>; /* ICSSG_1_TX_CHAN */ 187 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 188 <0x11>, /* RING_CPSW_TX_CHAN */ 189 <0x12>, /* RING_SAUL_TX_0_CHAN */ 190 <0x13>, /* RING_SAUL_TX_1_CHAN */ 191 <0x14>, /* RING_ICSSG_0_TX_CHAN */ 192 <0x15>; /* RING_ICSSG_1_TX_CHAN */ 193 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 194 <0x2b>, /* CPSW_RX_CHAN */ 195 <0x2d>, /* SAUL_RX_0_CHAN */ 196 <0x2f>, /* SAUL_RX_1_CHAN */ 197 <0x31>, /* SAUL_RX_2_CHAN */ 198 <0x33>, /* SAUL_RX_3_CHAN */ 199 <0x35>, /* ICSSG_0_RX_CHAN */ 200 <0x37>; /* ICSSG_1_RX_CHAN */ 201 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 202 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 203 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 204 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */ 205 <0x36>, /* FLOW_ICSSG_0_RX_CHAN */ 206 <0x38>; /* FLOW_ICSSG_1_RX_CHAN */ 207 }; 208 }; 209 210 dmsc: system-controller@44043000 { 211 bootph-all; 212 compatible = "ti,k2g-sci"; 213 ti,host-id = <12>; 214 mbox-names = "rx", "tx"; 215 mboxes = <&secure_proxy_main 12>, 216 <&secure_proxy_main 13>; 217 reg-names = "debug_messages"; 218 reg = <0x00 0x44043000 0x00 0xfe0>; 219 220 k3_pds: power-controller { 221 bootph-all; 222 compatible = "ti,sci-pm-domain"; 223 #power-domain-cells = <2>; 224 }; 225 226 k3_clks: clock-controller { 227 bootph-all; 228 compatible = "ti,k2g-sci-clk"; 229 #clock-cells = <2>; 230 }; 231 232 k3_reset: reset-controller { 233 bootph-all; 234 compatible = "ti,sci-reset"; 235 #reset-cells = <2>; 236 }; 237 }; 238 239 main_pmx0: pinctrl@f4000 { 240 bootph-all; 241 compatible = "pinctrl-single"; 242 reg = <0x00 0xf4000 0x00 0x2d0>; 243 #pinctrl-cells = <1>; 244 pinctrl-single,register-width = <32>; 245 pinctrl-single,function-mask = <0xffffffff>; 246 }; 247 248 main_timer0: timer@2400000 { 249 bootph-all; 250 compatible = "ti,am654-timer"; 251 reg = <0x00 0x2400000 0x00 0x400>; 252 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&k3_clks 36 1>; 254 clock-names = "fck"; 255 assigned-clocks = <&k3_clks 36 1>; 256 assigned-clock-parents = <&k3_clks 36 2>; 257 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 258 ti,timer-pwm; 259 }; 260 261 main_timer1: timer@2410000 { 262 compatible = "ti,am654-timer"; 263 reg = <0x00 0x2410000 0x00 0x400>; 264 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 265 clocks = <&k3_clks 37 1>; 266 clock-names = "fck"; 267 assigned-clocks = <&k3_clks 37 1>; 268 assigned-clock-parents = <&k3_clks 37 2>; 269 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 270 ti,timer-pwm; 271 }; 272 273 main_timer2: timer@2420000 { 274 compatible = "ti,am654-timer"; 275 reg = <0x00 0x2420000 0x00 0x400>; 276 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 277 clocks = <&k3_clks 38 1>; 278 clock-names = "fck"; 279 assigned-clocks = <&k3_clks 38 1>; 280 assigned-clock-parents = <&k3_clks 38 2>; 281 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 282 ti,timer-pwm; 283 }; 284 285 main_timer3: timer@2430000 { 286 compatible = "ti,am654-timer"; 287 reg = <0x00 0x2430000 0x00 0x400>; 288 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 289 clocks = <&k3_clks 39 1>; 290 clock-names = "fck"; 291 assigned-clocks = <&k3_clks 39 1>; 292 assigned-clock-parents = <&k3_clks 39 2>; 293 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 294 ti,timer-pwm; 295 }; 296 297 main_timer4: timer@2440000 { 298 compatible = "ti,am654-timer"; 299 reg = <0x00 0x2440000 0x00 0x400>; 300 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&k3_clks 40 1>; 302 clock-names = "fck"; 303 assigned-clocks = <&k3_clks 40 1>; 304 assigned-clock-parents = <&k3_clks 40 2>; 305 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 306 ti,timer-pwm; 307 }; 308 309 main_timer5: timer@2450000 { 310 compatible = "ti,am654-timer"; 311 reg = <0x00 0x2450000 0x00 0x400>; 312 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&k3_clks 41 1>; 314 clock-names = "fck"; 315 assigned-clocks = <&k3_clks 41 1>; 316 assigned-clock-parents = <&k3_clks 41 2>; 317 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 318 ti,timer-pwm; 319 }; 320 321 main_timer6: timer@2460000 { 322 compatible = "ti,am654-timer"; 323 reg = <0x00 0x2460000 0x00 0x400>; 324 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 325 clocks = <&k3_clks 42 1>; 326 clock-names = "fck"; 327 assigned-clocks = <&k3_clks 42 1>; 328 assigned-clock-parents = <&k3_clks 42 2>; 329 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 330 ti,timer-pwm; 331 }; 332 333 main_timer7: timer@2470000 { 334 compatible = "ti,am654-timer"; 335 reg = <0x00 0x2470000 0x00 0x400>; 336 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 337 clocks = <&k3_clks 43 1>; 338 clock-names = "fck"; 339 assigned-clocks = <&k3_clks 43 1>; 340 assigned-clock-parents = <&k3_clks 43 2>; 341 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 342 ti,timer-pwm; 343 }; 344 345 main_timer8: timer@2480000 { 346 compatible = "ti,am654-timer"; 347 reg = <0x00 0x2480000 0x00 0x400>; 348 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&k3_clks 44 1>; 350 clock-names = "fck"; 351 assigned-clocks = <&k3_clks 44 1>; 352 assigned-clock-parents = <&k3_clks 44 2>; 353 power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>; 354 ti,timer-pwm; 355 }; 356 357 main_timer9: timer@2490000 { 358 compatible = "ti,am654-timer"; 359 reg = <0x00 0x2490000 0x00 0x400>; 360 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 361 clocks = <&k3_clks 45 1>; 362 clock-names = "fck"; 363 assigned-clocks = <&k3_clks 45 1>; 364 assigned-clock-parents = <&k3_clks 45 2>; 365 power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>; 366 ti,timer-pwm; 367 }; 368 369 main_timer10: timer@24a0000 { 370 compatible = "ti,am654-timer"; 371 reg = <0x00 0x24a0000 0x00 0x400>; 372 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&k3_clks 46 1>; 374 clock-names = "fck"; 375 assigned-clocks = <&k3_clks 46 1>; 376 assigned-clock-parents = <&k3_clks 46 2>; 377 power-domains = <&k3_pds 46 TI_SCI_PD_EXCLUSIVE>; 378 ti,timer-pwm; 379 }; 380 381 main_timer11: timer@24b0000 { 382 compatible = "ti,am654-timer"; 383 reg = <0x00 0x24b0000 0x00 0x400>; 384 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 385 clocks = <&k3_clks 47 1>; 386 clock-names = "fck"; 387 assigned-clocks = <&k3_clks 47 1>; 388 assigned-clock-parents = <&k3_clks 47 2>; 389 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; 390 ti,timer-pwm; 391 }; 392 393 main_esm: esm@420000 { 394 bootph-pre-ram; 395 compatible = "ti,j721e-esm"; 396 reg = <0x00 0x420000 0x00 0x1000>; 397 /* Interrupt sources: rti0, rti1, rti8, rti9, rti10, rti11 */ 398 ti,esm-pins = <160>, <161>, <162>, <163>, <164>, <165>; 399 }; 400 401 main_uart0: serial@2800000 { 402 compatible = "ti,am64-uart", "ti,am654-uart"; 403 reg = <0x00 0x02800000 0x00 0x100>; 404 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 405 clock-frequency = <48000000>; 406 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 407 clocks = <&k3_clks 146 0>; 408 clock-names = "fclk"; 409 status = "disabled"; 410 }; 411 412 main_uart1: serial@2810000 { 413 compatible = "ti,am64-uart", "ti,am654-uart"; 414 reg = <0x00 0x02810000 0x00 0x100>; 415 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 416 clock-frequency = <48000000>; 417 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 418 clocks = <&k3_clks 152 0>; 419 clock-names = "fclk"; 420 status = "disabled"; 421 }; 422 423 main_uart2: serial@2820000 { 424 compatible = "ti,am64-uart", "ti,am654-uart"; 425 reg = <0x00 0x02820000 0x00 0x100>; 426 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 427 clock-frequency = <48000000>; 428 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 429 clocks = <&k3_clks 153 0>; 430 clock-names = "fclk"; 431 status = "disabled"; 432 }; 433 434 main_uart3: serial@2830000 { 435 compatible = "ti,am64-uart", "ti,am654-uart"; 436 reg = <0x00 0x02830000 0x00 0x100>; 437 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 438 clock-frequency = <48000000>; 439 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 440 clocks = <&k3_clks 154 0>; 441 clock-names = "fclk"; 442 status = "disabled"; 443 }; 444 445 main_uart4: serial@2840000 { 446 compatible = "ti,am64-uart", "ti,am654-uart"; 447 reg = <0x00 0x02840000 0x00 0x100>; 448 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 449 clock-frequency = <48000000>; 450 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 451 clocks = <&k3_clks 155 0>; 452 clock-names = "fclk"; 453 status = "disabled"; 454 }; 455 456 main_uart5: serial@2850000 { 457 compatible = "ti,am64-uart", "ti,am654-uart"; 458 reg = <0x00 0x02850000 0x00 0x100>; 459 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 460 clock-frequency = <48000000>; 461 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 462 clocks = <&k3_clks 156 0>; 463 clock-names = "fclk"; 464 status = "disabled"; 465 }; 466 467 main_uart6: serial@2860000 { 468 compatible = "ti,am64-uart", "ti,am654-uart"; 469 reg = <0x00 0x02860000 0x00 0x100>; 470 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 471 clock-frequency = <48000000>; 472 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 473 clocks = <&k3_clks 158 0>; 474 clock-names = "fclk"; 475 status = "disabled"; 476 }; 477 478 main_i2c0: i2c@20000000 { 479 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 480 reg = <0x00 0x20000000 0x00 0x100>; 481 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 482 #address-cells = <1>; 483 #size-cells = <0>; 484 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 485 clocks = <&k3_clks 102 2>; 486 clock-names = "fck"; 487 status = "disabled"; 488 }; 489 490 main_i2c1: i2c@20010000 { 491 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 492 reg = <0x00 0x20010000 0x00 0x100>; 493 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 494 #address-cells = <1>; 495 #size-cells = <0>; 496 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 497 clocks = <&k3_clks 103 2>; 498 clock-names = "fck"; 499 status = "disabled"; 500 }; 501 502 main_i2c2: i2c@20020000 { 503 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 504 reg = <0x00 0x20020000 0x00 0x100>; 505 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 506 #address-cells = <1>; 507 #size-cells = <0>; 508 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 509 clocks = <&k3_clks 104 2>; 510 clock-names = "fck"; 511 status = "disabled"; 512 }; 513 514 main_i2c3: i2c@20030000 { 515 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 516 reg = <0x00 0x20030000 0x00 0x100>; 517 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 521 clocks = <&k3_clks 105 2>; 522 clock-names = "fck"; 523 status = "disabled"; 524 }; 525 526 main_spi0: spi@20100000 { 527 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 528 reg = <0x00 0x20100000 0x00 0x400>; 529 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 533 clocks = <&k3_clks 141 0>; 534 dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>; 535 dma-names = "tx0", "rx0"; 536 status = "disabled"; 537 }; 538 539 main_spi1: spi@20110000 { 540 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 541 reg = <0x00 0x20110000 0x00 0x400>; 542 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 543 #address-cells = <1>; 544 #size-cells = <0>; 545 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 546 clocks = <&k3_clks 142 0>; 547 status = "disabled"; 548 }; 549 550 main_spi2: spi@20120000 { 551 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 552 reg = <0x00 0x20120000 0x00 0x400>; 553 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 554 #address-cells = <1>; 555 #size-cells = <0>; 556 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 557 clocks = <&k3_clks 143 0>; 558 status = "disabled"; 559 }; 560 561 main_spi3: spi@20130000 { 562 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 563 reg = <0x00 0x20130000 0x00 0x400>; 564 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 565 #address-cells = <1>; 566 #size-cells = <0>; 567 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; 568 clocks = <&k3_clks 144 0>; 569 status = "disabled"; 570 }; 571 572 main_spi4: spi@20140000 { 573 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 574 reg = <0x00 0x20140000 0x00 0x400>; 575 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 576 #address-cells = <1>; 577 #size-cells = <0>; 578 power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>; 579 clocks = <&k3_clks 145 0>; 580 status = "disabled"; 581 }; 582 583 main_gpio_intr: interrupt-controller@a00000 { 584 compatible = "ti,sci-intr"; 585 reg = <0x00 0x00a00000 0x00 0x800>; 586 ti,intr-trigger-type = <1>; 587 interrupt-controller; 588 interrupt-parent = <&gic500>; 589 #interrupt-cells = <1>; 590 ti,sci = <&dmsc>; 591 ti,sci-dev-id = <3>; 592 ti,interrupt-ranges = <0 32 16>; 593 }; 594 595 main_gpio0: gpio@600000 { 596 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 597 reg = <0x0 0x00600000 0x0 0x100>; 598 gpio-controller; 599 #gpio-cells = <2>; 600 interrupt-parent = <&main_gpio_intr>; 601 interrupts = <190>, <191>, <192>, 602 <193>, <194>, <195>; 603 interrupt-controller; 604 #interrupt-cells = <2>; 605 ti,ngpio = <87>; 606 ti,davinci-gpio-unbanked = <0>; 607 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 608 clocks = <&k3_clks 77 0>; 609 clock-names = "gpio"; 610 }; 611 612 main_gpio1: gpio@601000 { 613 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 614 reg = <0x0 0x00601000 0x0 0x100>; 615 gpio-controller; 616 #gpio-cells = <2>; 617 interrupt-parent = <&main_gpio_intr>; 618 interrupts = <180>, <181>, <182>, 619 <183>, <184>, <185>; 620 interrupt-controller; 621 #interrupt-cells = <2>; 622 ti,ngpio = <88>; 623 ti,davinci-gpio-unbanked = <0>; 624 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 625 clocks = <&k3_clks 78 0>; 626 clock-names = "gpio"; 627 }; 628 629 sdhci0: mmc@fa10000 { 630 compatible = "ti,am64-sdhci-8bit"; 631 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; 632 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 633 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 634 clocks = <&k3_clks 57 0>, <&k3_clks 57 1>; 635 clock-names = "clk_ahb", "clk_xin"; 636 bus-width = <8>; 637 mmc-ddr-1_8v; 638 mmc-hs200-1_8v; 639 ti,clkbuf-sel = <0x7>; 640 ti,trm-icp = <0x2>; 641 ti,otap-del-sel-legacy = <0x0>; 642 ti,otap-del-sel-mmc-hs = <0x0>; 643 ti,otap-del-sel-ddr52 = <0x6>; 644 ti,otap-del-sel-hs200 = <0x7>; 645 ti,itap-del-sel-legacy = <0x10>; 646 ti,itap-del-sel-mmc-hs = <0xa>; 647 ti,itap-del-sel-ddr52 = <0x3>; 648 status = "disabled"; 649 }; 650 651 sdhci1: mmc@fa00000 { 652 compatible = "ti,am64-sdhci-4bit"; 653 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; 654 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 655 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 656 clocks = <&k3_clks 58 3>, <&k3_clks 58 4>; 657 clock-names = "clk_ahb", "clk_xin"; 658 bus-width = <4>; 659 ti,clkbuf-sel = <0x7>; 660 ti,otap-del-sel-legacy = <0x0>; 661 ti,otap-del-sel-sd-hs = <0x0>; 662 ti,otap-del-sel-sdr12 = <0xf>; 663 ti,otap-del-sel-sdr25 = <0xf>; 664 ti,otap-del-sel-sdr50 = <0xc>; 665 ti,otap-del-sel-sdr104 = <0x6>; 666 ti,otap-del-sel-ddr50 = <0x9>; 667 ti,itap-del-sel-legacy = <0x0>; 668 ti,itap-del-sel-sd-hs = <0x0>; 669 ti,itap-del-sel-sdr12 = <0x0>; 670 ti,itap-del-sel-sdr25 = <0x0>; 671 status = "disabled"; 672 }; 673 674 cpsw3g: ethernet@8000000 { 675 compatible = "ti,am642-cpsw-nuss"; 676 #address-cells = <2>; 677 #size-cells = <2>; 678 reg = <0x0 0x8000000 0x0 0x200000>; 679 reg-names = "cpsw_nuss"; 680 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>; 681 clocks = <&k3_clks 13 0>; 682 assigned-clocks = <&k3_clks 13 1>; 683 assigned-clock-parents = <&k3_clks 13 9>; 684 clock-names = "fck"; 685 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 686 status = "disabled"; 687 688 dmas = <&main_pktdma 0xC500 15>, 689 <&main_pktdma 0xC501 15>, 690 <&main_pktdma 0xC502 15>, 691 <&main_pktdma 0xC503 15>, 692 <&main_pktdma 0xC504 15>, 693 <&main_pktdma 0xC505 15>, 694 <&main_pktdma 0xC506 15>, 695 <&main_pktdma 0xC507 15>, 696 <&main_pktdma 0x4500 15>; 697 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 698 "tx7", "rx"; 699 700 ethernet-ports { 701 #address-cells = <1>; 702 #size-cells = <0>; 703 704 cpsw_port1: port@1 { 705 reg = <1>; 706 ti,mac-only; 707 label = "port1"; 708 phys = <&phy_gmii_sel 1>; 709 mac-address = [00 00 00 00 00 00]; 710 ti,syscon-efuse = <&main_conf 0x200>; 711 status = "disabled"; 712 }; 713 714 cpsw_port2: port@2 { 715 reg = <2>; 716 ti,mac-only; 717 label = "port2"; 718 phys = <&phy_gmii_sel 2>; 719 mac-address = [00 00 00 00 00 00]; 720 status = "disabled"; 721 }; 722 }; 723 724 cpsw3g_mdio: mdio@f00 { 725 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 726 reg = <0x0 0xf00 0x0 0x100>; 727 #address-cells = <1>; 728 #size-cells = <0>; 729 clocks = <&k3_clks 13 0>; 730 clock-names = "fck"; 731 bus_freq = <1000000>; 732 status = "disabled"; 733 }; 734 735 cpts@3d000 { 736 compatible = "ti,j721e-cpts"; 737 reg = <0x0 0x3d000 0x0 0x400>; 738 clocks = <&k3_clks 13 1>; 739 clock-names = "cpts"; 740 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 741 interrupt-names = "cpts"; 742 ti,cpts-ext-ts-inputs = <4>; 743 ti,cpts-periodic-outputs = <2>; 744 }; 745 }; 746 747 main_cpts0: cpts@39000000 { 748 compatible = "ti,j721e-cpts"; 749 reg = <0x0 0x39000000 0x0 0x400>; 750 reg-names = "cpts"; 751 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; 752 clocks = <&k3_clks 84 0>; 753 clock-names = "cpts"; 754 assigned-clocks = <&k3_clks 84 0>; 755 assigned-clock-parents = <&k3_clks 84 8>; 756 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 757 interrupt-names = "cpts"; 758 ti,cpts-periodic-outputs = <6>; 759 ti,cpts-ext-ts-inputs = <8>; 760 }; 761 762 timesync_router: pinctrl@a40000 { 763 compatible = "pinctrl-single"; 764 reg = <0x0 0xa40000 0x0 0x800>; 765 #pinctrl-cells = <1>; 766 pinctrl-single,register-width = <32>; 767 pinctrl-single,function-mask = <0x000107ff>; 768 }; 769 770 usbss0: cdns-usb@f900000 { 771 compatible = "ti,am64-usb", "ti,j721e-usb"; 772 reg = <0x00 0xf900000 0x00 0x100>; 773 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 774 clocks = <&k3_clks 161 9>, <&k3_clks 161 1>; 775 clock-names = "ref", "lpm"; 776 assigned-clocks = <&k3_clks 161 9>; /* USB2_REFCLK */ 777 assigned-clock-parents = <&k3_clks 161 10>; /* HF0SC0 */ 778 #address-cells = <2>; 779 #size-cells = <2>; 780 ranges; 781 usb0: usb@f400000 { 782 compatible = "cdns,usb3"; 783 reg = <0x00 0xf400000 0x00 0x10000>, 784 <0x00 0xf410000 0x00 0x10000>, 785 <0x00 0xf420000 0x00 0x10000>; 786 reg-names = "otg", 787 "xhci", 788 "dev"; 789 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 790 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 791 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */ 792 interrupt-names = "host", 793 "peripheral", 794 "otg"; 795 maximum-speed = "super-speed"; 796 dr_mode = "otg"; 797 }; 798 }; 799 800 tscadc0: tscadc@28001000 { 801 compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; 802 reg = <0x00 0x28001000 0x00 0x1000>; 803 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 804 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 805 clocks = <&k3_clks 0 0>; 806 assigned-clocks = <&k3_clks 0 0>; 807 assigned-clock-parents = <&k3_clks 0 3>; 808 assigned-clock-rates = <60000000>; 809 clock-names = "fck"; 810 status = "disabled"; 811 812 adc { 813 #io-channel-cells = <1>; 814 compatible = "ti,am654-adc", "ti,am3359-adc"; 815 }; 816 }; 817 818 fss: bus@fc00000 { 819 compatible = "simple-bus"; 820 reg = <0x00 0x0fc00000 0x00 0x70000>; 821 #address-cells = <2>; 822 #size-cells = <2>; 823 ranges; 824 825 ospi0: spi@fc40000 { 826 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 827 reg = <0x00 0x0fc40000 0x00 0x100>, 828 <0x05 0x00000000 0x01 0x00000000>; 829 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 830 cdns,fifo-depth = <256>; 831 cdns,fifo-width = <4>; 832 cdns,trigger-address = <0x0>; 833 #address-cells = <0x1>; 834 #size-cells = <0x0>; 835 clocks = <&k3_clks 75 6>; 836 assigned-clocks = <&k3_clks 75 6>; 837 assigned-clock-parents = <&k3_clks 75 7>; 838 assigned-clock-rates = <166666666>; 839 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 840 status = "disabled"; 841 }; 842 }; 843 844 hwspinlock: spinlock@2a000000 { 845 compatible = "ti,am64-hwspinlock"; 846 reg = <0x00 0x2a000000 0x00 0x1000>; 847 #hwlock-cells = <1>; 848 }; 849 850 mailbox0_cluster2: mailbox@29020000 { 851 compatible = "ti,am64-mailbox"; 852 reg = <0x00 0x29020000 0x00 0x200>; 853 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 854 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 855 #mbox-cells = <1>; 856 ti,mbox-num-users = <4>; 857 ti,mbox-num-fifos = <16>; 858 status = "disabled"; 859 }; 860 861 mailbox0_cluster3: mailbox@29030000 { 862 compatible = "ti,am64-mailbox"; 863 reg = <0x00 0x29030000 0x00 0x200>; 864 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 866 #mbox-cells = <1>; 867 ti,mbox-num-users = <4>; 868 ti,mbox-num-fifos = <16>; 869 status = "disabled"; 870 }; 871 872 mailbox0_cluster4: mailbox@29040000 { 873 compatible = "ti,am64-mailbox"; 874 reg = <0x00 0x29040000 0x00 0x200>; 875 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 876 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 877 #mbox-cells = <1>; 878 ti,mbox-num-users = <4>; 879 ti,mbox-num-fifos = <16>; 880 status = "disabled"; 881 }; 882 883 mailbox0_cluster5: mailbox@29050000 { 884 compatible = "ti,am64-mailbox"; 885 reg = <0x00 0x29050000 0x00 0x200>; 886 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 888 #mbox-cells = <1>; 889 ti,mbox-num-users = <4>; 890 ti,mbox-num-fifos = <16>; 891 status = "disabled"; 892 }; 893 894 mailbox0_cluster6: mailbox@29060000 { 895 compatible = "ti,am64-mailbox"; 896 reg = <0x00 0x29060000 0x00 0x200>; 897 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 898 #mbox-cells = <1>; 899 ti,mbox-num-users = <4>; 900 ti,mbox-num-fifos = <16>; 901 status = "disabled"; 902 }; 903 904 mailbox0_cluster7: mailbox@29070000 { 905 compatible = "ti,am64-mailbox"; 906 reg = <0x00 0x29070000 0x00 0x200>; 907 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 908 #mbox-cells = <1>; 909 ti,mbox-num-users = <4>; 910 ti,mbox-num-fifos = <16>; 911 status = "disabled"; 912 }; 913 914 main_r5fss0: r5fss@78000000 { 915 compatible = "ti,am64-r5fss"; 916 ti,cluster-mode = <0>; 917 #address-cells = <1>; 918 #size-cells = <1>; 919 ranges = <0x78000000 0x00 0x78000000 0x10000>, 920 <0x78100000 0x00 0x78100000 0x10000>, 921 <0x78200000 0x00 0x78200000 0x08000>, 922 <0x78300000 0x00 0x78300000 0x08000>; 923 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; 924 status = "disabled"; 925 926 main_r5fss0_core0: r5f@78000000 { 927 compatible = "ti,am64-r5f"; 928 reg = <0x78000000 0x00010000>, 929 <0x78100000 0x00010000>; 930 reg-names = "atcm", "btcm"; 931 ti,sci = <&dmsc>; 932 ti,sci-dev-id = <121>; 933 ti,sci-proc-ids = <0x01 0xff>; 934 resets = <&k3_reset 121 1>; 935 firmware-name = "am64-main-r5f0_0-fw"; 936 ti,atcm-enable = <1>; 937 ti,btcm-enable = <1>; 938 ti,loczrama = <1>; 939 status = "disabled"; 940 }; 941 942 main_r5fss0_core1: r5f@78200000 { 943 compatible = "ti,am64-r5f"; 944 reg = <0x78200000 0x00008000>, 945 <0x78300000 0x00008000>; 946 reg-names = "atcm", "btcm"; 947 ti,sci = <&dmsc>; 948 ti,sci-dev-id = <122>; 949 ti,sci-proc-ids = <0x02 0xff>; 950 resets = <&k3_reset 122 1>; 951 firmware-name = "am64-main-r5f0_1-fw"; 952 ti,atcm-enable = <1>; 953 ti,btcm-enable = <1>; 954 ti,loczrama = <1>; 955 status = "disabled"; 956 }; 957 }; 958 959 main_r5fss1: r5fss@78400000 { 960 compatible = "ti,am64-r5fss"; 961 ti,cluster-mode = <0>; 962 #address-cells = <1>; 963 #size-cells = <1>; 964 ranges = <0x78400000 0x00 0x78400000 0x10000>, 965 <0x78500000 0x00 0x78500000 0x10000>, 966 <0x78600000 0x00 0x78600000 0x08000>, 967 <0x78700000 0x00 0x78700000 0x08000>; 968 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 969 status = "disabled"; 970 971 main_r5fss1_core0: r5f@78400000 { 972 compatible = "ti,am64-r5f"; 973 reg = <0x78400000 0x00010000>, 974 <0x78500000 0x00010000>; 975 reg-names = "atcm", "btcm"; 976 ti,sci = <&dmsc>; 977 ti,sci-dev-id = <123>; 978 ti,sci-proc-ids = <0x06 0xff>; 979 resets = <&k3_reset 123 1>; 980 firmware-name = "am64-main-r5f1_0-fw"; 981 ti,atcm-enable = <1>; 982 ti,btcm-enable = <1>; 983 ti,loczrama = <1>; 984 status = "disabled"; 985 }; 986 987 main_r5fss1_core1: r5f@78600000 { 988 compatible = "ti,am64-r5f"; 989 reg = <0x78600000 0x00008000>, 990 <0x78700000 0x00008000>; 991 reg-names = "atcm", "btcm"; 992 ti,sci = <&dmsc>; 993 ti,sci-dev-id = <124>; 994 ti,sci-proc-ids = <0x07 0xff>; 995 resets = <&k3_reset 124 1>; 996 firmware-name = "am64-main-r5f1_1-fw"; 997 ti,atcm-enable = <1>; 998 ti,btcm-enable = <1>; 999 ti,loczrama = <1>; 1000 status = "disabled"; 1001 }; 1002 }; 1003 1004 serdes_wiz0: wiz@f000000 { 1005 compatible = "ti,am64-wiz-10g"; 1006 #address-cells = <1>; 1007 #size-cells = <1>; 1008 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 1009 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>; 1010 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 1011 num-lanes = <1>; 1012 #reset-cells = <1>; 1013 #clock-cells = <1>; 1014 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; 1015 1016 assigned-clocks = <&k3_clks 162 1>; 1017 assigned-clock-parents = <&k3_clks 162 5>; 1018 1019 serdes0: serdes@f000000 { 1020 compatible = "ti,j721e-serdes-10g"; 1021 reg = <0x0f000000 0x00010000>; 1022 reg-names = "torrent_phy"; 1023 resets = <&serdes_wiz0 0>; 1024 reset-names = "torrent_reset"; 1025 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1026 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; 1027 clock-names = "refclk", "phy_en_refclk"; 1028 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1029 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, 1030 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; 1031 assigned-clock-parents = <&k3_clks 162 1>, 1032 <&k3_clks 162 1>, 1033 <&k3_clks 162 1>; 1034 #address-cells = <1>; 1035 #size-cells = <0>; 1036 #clock-cells = <1>; 1037 }; 1038 }; 1039 1040 pcie0_rc: pcie@f102000 { 1041 compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host"; 1042 reg = <0x00 0x0f102000 0x00 0x1000>, 1043 <0x00 0x0f100000 0x00 0x400>, 1044 <0x00 0x0d000000 0x00 0x00800000>, 1045 <0x06 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ 1046 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1047 interrupt-names = "link_state"; 1048 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 1049 device_type = "pci"; 1050 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; 1051 max-link-speed = <2>; 1052 num-lanes = <1>; 1053 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 1054 clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; 1055 clock-names = "fck", "pcie_refclk"; 1056 #address-cells = <3>; 1057 #size-cells = <2>; 1058 bus-range = <0x0 0xff>; 1059 cdns,no-bar-match-nbits = <64>; 1060 vendor-id = <0x104c>; 1061 device-id = <0xb010>; 1062 msi-map = <0x0 &gic_its 0x0 0x10000>; 1063 ranges = <0x01000000 0x00 0x00001000 0x06 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ 1064 <0x02000000 0x00 0x00101000 0x06 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ 1065 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>; 1066 status = "disabled"; 1067 }; 1068 1069 epwm0: pwm@23000000 { 1070 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1071 #pwm-cells = <3>; 1072 reg = <0x0 0x23000000 0x0 0x100>; 1073 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 1074 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 1075 clock-names = "tbclk", "fck"; 1076 status = "disabled"; 1077 }; 1078 1079 epwm1: pwm@23010000 { 1080 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1081 #pwm-cells = <3>; 1082 reg = <0x0 0x23010000 0x0 0x100>; 1083 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 1084 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 1085 clock-names = "tbclk", "fck"; 1086 status = "disabled"; 1087 }; 1088 1089 epwm2: pwm@23020000 { 1090 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1091 #pwm-cells = <3>; 1092 reg = <0x0 0x23020000 0x0 0x100>; 1093 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 1094 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 1095 clock-names = "tbclk", "fck"; 1096 status = "disabled"; 1097 }; 1098 1099 epwm3: pwm@23030000 { 1100 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1101 #pwm-cells = <3>; 1102 reg = <0x0 0x23030000 0x0 0x100>; 1103 power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; 1104 clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>; 1105 clock-names = "tbclk", "fck"; 1106 status = "disabled"; 1107 }; 1108 1109 epwm4: pwm@23040000 { 1110 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1111 #pwm-cells = <3>; 1112 reg = <0x0 0x23040000 0x0 0x100>; 1113 power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; 1114 clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>; 1115 clock-names = "tbclk", "fck"; 1116 status = "disabled"; 1117 }; 1118 1119 epwm5: pwm@23050000 { 1120 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1121 #pwm-cells = <3>; 1122 reg = <0x0 0x23050000 0x0 0x100>; 1123 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 1124 clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>; 1125 clock-names = "tbclk", "fck"; 1126 status = "disabled"; 1127 }; 1128 1129 epwm6: pwm@23060000 { 1130 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1131 #pwm-cells = <3>; 1132 reg = <0x0 0x23060000 0x0 0x100>; 1133 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 1134 clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>; 1135 clock-names = "tbclk", "fck"; 1136 status = "disabled"; 1137 }; 1138 1139 epwm7: pwm@23070000 { 1140 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1141 #pwm-cells = <3>; 1142 reg = <0x0 0x23070000 0x0 0x100>; 1143 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 1144 clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>; 1145 clock-names = "tbclk", "fck"; 1146 status = "disabled"; 1147 }; 1148 1149 epwm8: pwm@23080000 { 1150 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1151 #pwm-cells = <3>; 1152 reg = <0x0 0x23080000 0x0 0x100>; 1153 power-domains = <&k3_pds 94 TI_SCI_PD_EXCLUSIVE>; 1154 clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>; 1155 clock-names = "tbclk", "fck"; 1156 status = "disabled"; 1157 }; 1158 1159 ecap0: pwm@23100000 { 1160 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 1161 #pwm-cells = <3>; 1162 reg = <0x0 0x23100000 0x0 0x60>; 1163 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 1164 clocks = <&k3_clks 51 0>; 1165 clock-names = "fck"; 1166 status = "disabled"; 1167 }; 1168 1169 ecap1: pwm@23110000 { 1170 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 1171 #pwm-cells = <3>; 1172 reg = <0x0 0x23110000 0x0 0x60>; 1173 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 1174 clocks = <&k3_clks 52 0>; 1175 clock-names = "fck"; 1176 status = "disabled"; 1177 }; 1178 1179 ecap2: pwm@23120000 { 1180 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 1181 #pwm-cells = <3>; 1182 reg = <0x0 0x23120000 0x0 0x60>; 1183 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 1184 clocks = <&k3_clks 53 0>; 1185 clock-names = "fck"; 1186 status = "disabled"; 1187 }; 1188 1189 eqep0: counter@23200000 { 1190 compatible = "ti,am62-eqep"; 1191 reg = <0x00 0x23200000 0x00 0x100>; 1192 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; 1193 clocks = <&k3_clks 59 0>; 1194 interrupts = <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>; 1195 status = "disabled"; 1196 }; 1197 1198 eqep1: counter@23210000 { 1199 compatible = "ti,am62-eqep"; 1200 reg = <0x00 0x23210000 0x00 0x100>; 1201 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; 1202 clocks = <&k3_clks 60 0>; 1203 interrupts = <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>; 1204 status = "disabled"; 1205 }; 1206 1207 eqep2: counter@23220000 { 1208 compatible = "ti,am62-eqep"; 1209 reg = <0x00 0x23220000 0x00 0x100>; 1210 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 1211 clocks = <&k3_clks 62 0>; 1212 interrupts = <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>; 1213 status = "disabled"; 1214 }; 1215 1216 main_rti0: watchdog@e000000 { 1217 compatible = "ti,j7-rti-wdt"; 1218 reg = <0x00 0xe000000 0x00 0x100>; 1219 clocks = <&k3_clks 125 0>; 1220 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 1221 assigned-clocks = <&k3_clks 125 0>; 1222 assigned-clock-parents = <&k3_clks 125 2>; 1223 }; 1224 1225 main_rti1: watchdog@e010000 { 1226 compatible = "ti,j7-rti-wdt"; 1227 reg = <0x00 0xe010000 0x00 0x100>; 1228 clocks = <&k3_clks 126 0>; 1229 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; 1230 assigned-clocks = <&k3_clks 126 0>; 1231 assigned-clock-parents = <&k3_clks 126 2>; 1232 }; 1233 1234 icssg0: icssg@30000000 { 1235 compatible = "ti,am642-icssg"; 1236 reg = <0x00 0x30000000 0x00 0x80000>; 1237 power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; 1238 #address-cells = <1>; 1239 #size-cells = <1>; 1240 ranges = <0x0 0x00 0x30000000 0x80000>; 1241 clocks = <&k3_clks 81 0>, /* icssg0_core_clk */ 1242 <&k3_clks 81 3>, /* icssg0_iep_clk */ 1243 <&k3_clks 81 16>, /* icssg0_rgmii_mhz_250_clk */ 1244 <&k3_clks 81 17>, /* icssg0_rgmii_mhz_50_clk */ 1245 <&k3_clks 81 18>, /* icssg0_rgmii_mhz_5_clk */ 1246 <&k3_clks 81 19>, /* icssg0_uart_clk */ 1247 <&k3_clks 81 20>; /* icssg0_iclk */ 1248 assigned-clocks = <&k3_clks 81 0>; 1249 assigned-clock-parents = <&k3_clks 81 2>; 1250 1251 icssg0_mem: memories@0 { 1252 reg = <0x0 0x2000>, 1253 <0x2000 0x2000>, 1254 <0x10000 0x10000>; 1255 reg-names = "dram0", "dram1", "shrdram2"; 1256 }; 1257 1258 icssg0_cfg: cfg@26000 { 1259 compatible = "ti,pruss-cfg", "syscon"; 1260 reg = <0x26000 0x200>; 1261 #address-cells = <1>; 1262 #size-cells = <1>; 1263 ranges = <0x0 0x26000 0x2000>; 1264 1265 clocks { 1266 #address-cells = <1>; 1267 #size-cells = <0>; 1268 1269 icssg0_coreclk_mux: coreclk-mux@3c { 1270 reg = <0x3c>; 1271 #clock-cells = <0>; 1272 clocks = <&k3_clks 81 0>, /* icssg0_core_clk */ 1273 <&k3_clks 81 20>; /* icssg0_iclk */ 1274 assigned-clocks = <&icssg0_coreclk_mux>; 1275 assigned-clock-parents = <&k3_clks 81 0>; 1276 }; 1277 1278 icssg0_iepclk_mux: iepclk-mux@30 { 1279 reg = <0x30>; 1280 #clock-cells = <0>; 1281 clocks = <&k3_clks 81 3>, /* icssg0_iep_clk */ 1282 <&icssg0_coreclk_mux>; /* icssg0_coreclk_mux */ 1283 assigned-clocks = <&icssg0_iepclk_mux>; 1284 assigned-clock-parents = <&icssg0_coreclk_mux>; 1285 }; 1286 }; 1287 }; 1288 1289 icssg0_iep0: iep@2e000 { 1290 compatible = "ti,am654-icss-iep"; 1291 reg = <0x2e000 0x1000>; 1292 clocks = <&icssg0_iepclk_mux>; 1293 }; 1294 1295 icssg0_iep1: iep@2f000 { 1296 compatible = "ti,am654-icss-iep"; 1297 reg = <0x2f000 0x1000>; 1298 clocks = <&icssg0_iepclk_mux>; 1299 }; 1300 1301 icssg0_mii_rt: mii-rt@32000 { 1302 compatible = "ti,pruss-mii", "syscon"; 1303 reg = <0x32000 0x100>; 1304 }; 1305 1306 icssg0_mii_g_rt: mii-g-rt@33000 { 1307 compatible = "ti,pruss-mii-g", "syscon"; 1308 reg = <0x33000 0x1000>; 1309 }; 1310 1311 icssg0_pa_stats: pa-stats@2c000 { 1312 compatible = "ti,pruss-pa-st", "syscon"; 1313 reg = <0x2c000 0x1000>; 1314 }; 1315 1316 icssg0_intc: interrupt-controller@20000 { 1317 compatible = "ti,icssg-intc"; 1318 reg = <0x20000 0x2000>; 1319 interrupt-controller; 1320 #interrupt-cells = <3>; 1321 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1322 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1323 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1324 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1325 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1326 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1327 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1328 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1329 interrupt-names = "host_intr0", "host_intr1", 1330 "host_intr2", "host_intr3", 1331 "host_intr4", "host_intr5", 1332 "host_intr6", "host_intr7"; 1333 }; 1334 1335 pru0_0: pru@34000 { 1336 compatible = "ti,am642-pru"; 1337 reg = <0x34000 0x3000>, 1338 <0x22000 0x100>, 1339 <0x22400 0x100>; 1340 reg-names = "iram", "control", "debug"; 1341 firmware-name = "am64x-pru0_0-fw"; 1342 interrupt-parent = <&icssg0_intc>; 1343 interrupts = <16 2 2>; 1344 interrupt-names = "vring"; 1345 }; 1346 1347 rtu0_0: rtu@4000 { 1348 compatible = "ti,am642-rtu"; 1349 reg = <0x4000 0x2000>, 1350 <0x23000 0x100>, 1351 <0x23400 0x100>; 1352 reg-names = "iram", "control", "debug"; 1353 firmware-name = "am64x-rtu0_0-fw"; 1354 interrupt-parent = <&icssg0_intc>; 1355 interrupts = <20 4 4>; 1356 interrupt-names = "vring"; 1357 }; 1358 1359 tx_pru0_0: txpru@a000 { 1360 compatible = "ti,am642-tx-pru"; 1361 reg = <0xa000 0x1800>, 1362 <0x25000 0x100>, 1363 <0x25400 0x100>; 1364 reg-names = "iram", "control", "debug"; 1365 firmware-name = "am64x-txpru0_0-fw"; 1366 }; 1367 1368 pru0_1: pru@38000 { 1369 compatible = "ti,am642-pru"; 1370 reg = <0x38000 0x3000>, 1371 <0x24000 0x100>, 1372 <0x24400 0x100>; 1373 reg-names = "iram", "control", "debug"; 1374 firmware-name = "am64x-pru0_1-fw"; 1375 interrupt-parent = <&icssg0_intc>; 1376 interrupts = <18 3 3>; 1377 interrupt-names = "vring"; 1378 }; 1379 1380 rtu0_1: rtu@6000 { 1381 compatible = "ti,am642-rtu"; 1382 reg = <0x6000 0x2000>, 1383 <0x23800 0x100>, 1384 <0x23c00 0x100>; 1385 reg-names = "iram", "control", "debug"; 1386 firmware-name = "am64x-rtu0_1-fw"; 1387 interrupt-parent = <&icssg0_intc>; 1388 interrupts = <22 5 5>; 1389 interrupt-names = "vring"; 1390 }; 1391 1392 tx_pru0_1: txpru@c000 { 1393 compatible = "ti,am642-tx-pru"; 1394 reg = <0xc000 0x1800>, 1395 <0x25800 0x100>, 1396 <0x25c00 0x100>; 1397 reg-names = "iram", "control", "debug"; 1398 firmware-name = "am64x-txpru0_1-fw"; 1399 }; 1400 1401 icssg0_mdio: mdio@32400 { 1402 compatible = "ti,davinci_mdio"; 1403 reg = <0x32400 0x100>; 1404 clocks = <&k3_clks 62 3>; 1405 clock-names = "fck"; 1406 #address-cells = <1>; 1407 #size-cells = <0>; 1408 bus_freq = <1000000>; 1409 status = "disabled"; 1410 }; 1411 }; 1412 1413 icssg1: icssg@30080000 { 1414 compatible = "ti,am642-icssg"; 1415 reg = <0x00 0x30080000 0x00 0x80000>; 1416 power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>; 1417 #address-cells = <1>; 1418 #size-cells = <1>; 1419 ranges = <0x0 0x00 0x30080000 0x80000>; 1420 clocks = <&k3_clks 82 0>, /* icssg1_core_clk */ 1421 <&k3_clks 82 3>, /* icssg1_iep_clk */ 1422 <&k3_clks 82 16>, /* icssg1_rgmii_mhz_250_clk */ 1423 <&k3_clks 82 17>, /* icssg1_rgmii_mhz_50_clk */ 1424 <&k3_clks 82 18>, /* icssg1_rgmii_mhz_5_clk */ 1425 <&k3_clks 82 19>, /* icssg1_uart_clk */ 1426 <&k3_clks 82 20>; /* icssg1_iclk */ 1427 assigned-clocks = <&k3_clks 82 0>; 1428 assigned-clock-parents = <&k3_clks 82 2>; 1429 1430 icssg1_mem: memories@0 { 1431 reg = <0x0 0x2000>, 1432 <0x2000 0x2000>, 1433 <0x10000 0x10000>; 1434 reg-names = "dram0", "dram1", "shrdram2"; 1435 }; 1436 1437 icssg1_cfg: cfg@26000 { 1438 compatible = "ti,pruss-cfg", "syscon"; 1439 reg = <0x26000 0x200>; 1440 #address-cells = <1>; 1441 #size-cells = <1>; 1442 ranges = <0x0 0x26000 0x2000>; 1443 1444 clocks { 1445 #address-cells = <1>; 1446 #size-cells = <0>; 1447 1448 icssg1_coreclk_mux: coreclk-mux@3c { 1449 reg = <0x3c>; 1450 #clock-cells = <0>; 1451 clocks = <&k3_clks 82 0>, /* icssg1_core_clk */ 1452 <&k3_clks 82 20>; /* icssg1_iclk */ 1453 assigned-clocks = <&icssg1_coreclk_mux>; 1454 assigned-clock-parents = <&k3_clks 82 0>; 1455 }; 1456 1457 icssg1_iepclk_mux: iepclk-mux@30 { 1458 reg = <0x30>; 1459 #clock-cells = <0>; 1460 clocks = <&k3_clks 82 3>, /* icssg1_iep_clk */ 1461 <&icssg1_coreclk_mux>; /* icssg1_coreclk_mux */ 1462 assigned-clocks = <&icssg1_iepclk_mux>; 1463 assigned-clock-parents = <&icssg1_coreclk_mux>; 1464 }; 1465 }; 1466 }; 1467 1468 icssg1_iep0: iep@2e000 { 1469 compatible = "ti,am654-icss-iep"; 1470 reg = <0x2e000 0x1000>; 1471 clocks = <&icssg1_iepclk_mux>; 1472 }; 1473 1474 icssg1_iep1: iep@2f000 { 1475 compatible = "ti,am654-icss-iep"; 1476 reg = <0x2f000 0x1000>; 1477 clocks = <&icssg1_iepclk_mux>; 1478 }; 1479 1480 icssg1_mii_rt: mii-rt@32000 { 1481 compatible = "ti,pruss-mii", "syscon"; 1482 reg = <0x32000 0x100>; 1483 }; 1484 1485 icssg1_mii_g_rt: mii-g-rt@33000 { 1486 compatible = "ti,pruss-mii-g", "syscon"; 1487 reg = <0x33000 0x1000>; 1488 }; 1489 1490 icssg1_pa_stats: pa-stats@2c000 { 1491 compatible = "ti,pruss-pa-st", "syscon"; 1492 reg = <0x2c000 0x1000>; 1493 }; 1494 1495 icssg1_intc: interrupt-controller@20000 { 1496 compatible = "ti,icssg-intc"; 1497 reg = <0x20000 0x2000>; 1498 interrupt-controller; 1499 #interrupt-cells = <3>; 1500 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1501 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1502 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1503 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1504 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1505 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 1506 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 1507 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1508 interrupt-names = "host_intr0", "host_intr1", 1509 "host_intr2", "host_intr3", 1510 "host_intr4", "host_intr5", 1511 "host_intr6", "host_intr7"; 1512 }; 1513 1514 pru1_0: pru@34000 { 1515 compatible = "ti,am642-pru"; 1516 reg = <0x34000 0x4000>, 1517 <0x22000 0x100>, 1518 <0x22400 0x100>; 1519 reg-names = "iram", "control", "debug"; 1520 firmware-name = "am64x-pru1_0-fw"; 1521 interrupt-parent = <&icssg1_intc>; 1522 interrupts = <16 2 2>; 1523 interrupt-names = "vring"; 1524 }; 1525 1526 rtu1_0: rtu@4000 { 1527 compatible = "ti,am642-rtu"; 1528 reg = <0x4000 0x2000>, 1529 <0x23000 0x100>, 1530 <0x23400 0x100>; 1531 reg-names = "iram", "control", "debug"; 1532 firmware-name = "am64x-rtu1_0-fw"; 1533 interrupt-parent = <&icssg1_intc>; 1534 interrupts = <20 4 4>; 1535 interrupt-names = "vring"; 1536 }; 1537 1538 tx_pru1_0: txpru@a000 { 1539 compatible = "ti,am642-tx-pru"; 1540 reg = <0xa000 0x1800>, 1541 <0x25000 0x100>, 1542 <0x25400 0x100>; 1543 reg-names = "iram", "control", "debug"; 1544 firmware-name = "am64x-txpru1_0-fw"; 1545 }; 1546 1547 pru1_1: pru@38000 { 1548 compatible = "ti,am642-pru"; 1549 reg = <0x38000 0x4000>, 1550 <0x24000 0x100>, 1551 <0x24400 0x100>; 1552 reg-names = "iram", "control", "debug"; 1553 firmware-name = "am64x-pru1_1-fw"; 1554 interrupt-parent = <&icssg1_intc>; 1555 interrupts = <18 3 3>; 1556 interrupt-names = "vring"; 1557 }; 1558 1559 rtu1_1: rtu@6000 { 1560 compatible = "ti,am642-rtu"; 1561 reg = <0x6000 0x2000>, 1562 <0x23800 0x100>, 1563 <0x23c00 0x100>; 1564 reg-names = "iram", "control", "debug"; 1565 firmware-name = "am64x-rtu1_1-fw"; 1566 interrupt-parent = <&icssg1_intc>; 1567 interrupts = <22 5 5>; 1568 interrupt-names = "vring"; 1569 }; 1570 1571 tx_pru1_1: txpru@c000 { 1572 compatible = "ti,am642-tx-pru"; 1573 reg = <0xc000 0x1800>, 1574 <0x25800 0x100>, 1575 <0x25c00 0x100>; 1576 reg-names = "iram", "control", "debug"; 1577 firmware-name = "am64x-txpru1_1-fw"; 1578 }; 1579 1580 icssg1_mdio: mdio@32400 { 1581 compatible = "ti,davinci_mdio"; 1582 reg = <0x32400 0x100>; 1583 #address-cells = <1>; 1584 #size-cells = <0>; 1585 clocks = <&k3_clks 82 0>; 1586 clock-names = "fck"; 1587 bus_freq = <1000000>; 1588 status = "disabled"; 1589 }; 1590 }; 1591 1592 main_mcan0: can@20701000 { 1593 compatible = "bosch,m_can"; 1594 reg = <0x00 0x20701000 0x00 0x200>, 1595 <0x00 0x20708000 0x00 0x8000>; 1596 reg-names = "m_can", "message_ram"; 1597 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 1598 clocks = <&k3_clks 98 5>, <&k3_clks 98 0>; 1599 clock-names = "hclk", "cclk"; 1600 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1602 interrupt-names = "int0", "int1"; 1603 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1604 status = "disabled"; 1605 }; 1606 1607 main_mcan1: can@20711000 { 1608 compatible = "bosch,m_can"; 1609 reg = <0x00 0x20711000 0x00 0x200>, 1610 <0x00 0x20718000 0x00 0x8000>; 1611 reg-names = "m_can", "message_ram"; 1612 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 1613 clocks = <&k3_clks 99 5>, <&k3_clks 99 0>; 1614 clock-names = "hclk", "cclk"; 1615 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1616 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1617 interrupt-names = "int0", "int1"; 1618 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1619 status = "disabled"; 1620 }; 1621 1622 crypto: crypto@40900000 { 1623 compatible = "ti,am64-sa2ul"; 1624 reg = <0x00 0x40900000 0x00 0x1200>; 1625 power-domains = <&k3_pds 133 TI_SCI_PD_SHARED>; 1626 #address-cells = <2>; 1627 #size-cells = <2>; 1628 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; 1629 dmas = <&main_pktdma 0xc001 0>, <&main_pktdma 0x4002 0>, 1630 <&main_pktdma 0x4003 0>; 1631 dma-names = "tx", "rx1", "rx2"; 1632 1633 rng: rng@40910000 { 1634 compatible = "inside-secure,safexcel-eip76"; 1635 reg = <0x00 0x40910000 0x00 0x7d>; 1636 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1637 status = "disabled"; /* Used by OP-TEE */ 1638 }; 1639 }; 1640 1641 gpmc0: memory-controller@3b000000 { 1642 compatible = "ti,am64-gpmc"; 1643 power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; 1644 clocks = <&k3_clks 80 0>; 1645 clock-names = "fck"; 1646 reg = <0x00 0x3b000000 0x00 0x400>, 1647 <0x00 0x50000000 0x00 0x8000000>; 1648 reg-names = "cfg", "data"; 1649 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1650 gpmc,num-cs = <3>; 1651 gpmc,num-waitpins = <2>; 1652 #address-cells = <2>; 1653 #size-cells = <1>; 1654 interrupt-controller; 1655 #interrupt-cells = <2>; 1656 gpio-controller; 1657 #gpio-cells = <2>; 1658 status = "disabled"; 1659 }; 1660 1661 elm0: ecc@25010000 { 1662 compatible = "ti,am64-elm"; 1663 reg = <0x00 0x25010000 0x00 0x2000>; 1664 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 1665 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; 1666 clocks = <&k3_clks 54 0>; 1667 clock-names = "fck"; 1668 status = "disabled"; 1669 }; 1670 1671 main_vtm0: temperature-sensor@b00000 { 1672 compatible = "ti,j7200-vtm"; 1673 reg = <0x00 0xb00000 0x00 0x400>, 1674 <0x00 0xb01000 0x00 0x400>; 1675 power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>; 1676 #thermal-sensor-cells = <1>; 1677 }; 1678}; 1679