1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for AM642 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/phy/phy-cadence.h> 9#include <dt-bindings/phy/phy-ti.h> 10 11/ { 12 serdes_refclk: clock-cmnrefclk { 13 #clock-cells = <0>; 14 compatible = "fixed-clock"; 15 clock-frequency = <0>; 16 }; 17}; 18 19&cbass_main { 20 oc_sram: sram@70000000 { 21 compatible = "mmio-sram"; 22 reg = <0x00 0x70000000 0x00 0x200000>; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 ranges = <0x0 0x00 0x70000000 0x200000>; 26 27 tfa-sram@1c0000 { 28 reg = <0x1c0000 0x20000>; 29 }; 30 31 dmsc-sram@1e0000 { 32 reg = <0x1e0000 0x1c000>; 33 }; 34 35 sproxy-sram@1fc000 { 36 reg = <0x1fc000 0x4000>; 37 }; 38 }; 39 40 main_conf: syscon@43000000 { 41 bootph-all; 42 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 43 reg = <0x0 0x43000000 0x0 0x20000>; 44 #address-cells = <1>; 45 #size-cells = <1>; 46 ranges = <0x0 0x0 0x43000000 0x20000>; 47 48 chipid@14 { 49 bootph-all; 50 compatible = "ti,am654-chipid"; 51 reg = <0x00000014 0x4>; 52 }; 53 54 serdes_ln_ctrl: mux-controller@4080 { 55 compatible = "reg-mux"; 56 reg = <0x4080 0x4>; 57 #mux-control-cells = <1>; 58 mux-reg-masks = <0x0 0x3>; /* SERDES0 lane0 select */ 59 }; 60 61 phy_gmii_sel: phy@4044 { 62 compatible = "ti,am654-phy-gmii-sel"; 63 reg = <0x4044 0x8>; 64 #phy-cells = <1>; 65 }; 66 67 epwm_tbclk: clock-controller@4130 { 68 compatible = "ti,am64-epwm-tbclk"; 69 reg = <0x4130 0x4>; 70 #clock-cells = <1>; 71 }; 72 }; 73 74 gic500: interrupt-controller@1800000 { 75 compatible = "arm,gic-v3"; 76 #address-cells = <2>; 77 #size-cells = <2>; 78 ranges; 79 #interrupt-cells = <3>; 80 interrupt-controller; 81 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 82 <0x00 0x01840000 0x00 0xC0000>, /* GICR */ 83 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 84 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 85 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 86 /* 87 * vcpumntirq: 88 * virtual CPU interface maintenance interrupt 89 */ 90 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 91 92 gic_its: msi-controller@1820000 { 93 compatible = "arm,gic-v3-its"; 94 reg = <0x00 0x01820000 0x00 0x10000>; 95 socionext,synquacer-pre-its = <0x1000000 0x400000>; 96 msi-controller; 97 #msi-cells = <1>; 98 }; 99 }; 100 101 dmss: bus@48000000 { 102 bootph-all; 103 compatible = "simple-bus"; 104 #address-cells = <2>; 105 #size-cells = <2>; 106 dma-ranges; 107 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; 108 109 ti,sci-dev-id = <25>; 110 111 secure_proxy_main: mailbox@4d000000 { 112 bootph-all; 113 compatible = "ti,am654-secure-proxy"; 114 #mbox-cells = <1>; 115 reg-names = "target_data", "rt", "scfg"; 116 reg = <0x00 0x4d000000 0x00 0x80000>, 117 <0x00 0x4a600000 0x00 0x80000>, 118 <0x00 0x4a400000 0x00 0x80000>; 119 interrupt-names = "rx_012"; 120 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 121 }; 122 123 inta_main_dmss: interrupt-controller@48000000 { 124 compatible = "ti,sci-inta"; 125 reg = <0x00 0x48000000 0x00 0x100000>; 126 #interrupt-cells = <0>; 127 interrupt-controller; 128 interrupt-parent = <&gic500>; 129 msi-controller; 130 ti,sci = <&dmsc>; 131 ti,sci-dev-id = <28>; 132 ti,interrupt-ranges = <4 68 36>; 133 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 134 }; 135 136 main_bcdma: dma-controller@485c0100 { 137 compatible = "ti,am64-dmss-bcdma"; 138 reg = <0x00 0x485c0100 0x00 0x100>, 139 <0x00 0x4c000000 0x00 0x20000>, 140 <0x00 0x4a820000 0x00 0x20000>, 141 <0x00 0x4aa40000 0x00 0x20000>, 142 <0x00 0x4bc00000 0x00 0x100000>, 143 <0x00 0x48600000 0x00 0x8000>, 144 <0x00 0x484a4000 0x00 0x2000>, 145 <0x00 0x484c2000 0x00 0x2000>, 146 <0x00 0x48420000 0x00 0x2000>; 147 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt", 148 "ring", "tchan", "rchan", "bchan"; 149 msi-parent = <&inta_main_dmss>; 150 #dma-cells = <3>; 151 152 ti,sci = <&dmsc>; 153 ti,sci-dev-id = <26>; 154 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 155 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 156 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 157 }; 158 159 main_pktdma: dma-controller@485c0000 { 160 compatible = "ti,am64-dmss-pktdma"; 161 reg = <0x00 0x485c0000 0x00 0x100>, 162 <0x00 0x4a800000 0x00 0x20000>, 163 <0x00 0x4aa00000 0x00 0x40000>, 164 <0x00 0x4b800000 0x00 0x400000>, 165 <0x00 0x485e0000 0x00 0x20000>, 166 <0x00 0x484a0000 0x00 0x4000>, 167 <0x00 0x484c0000 0x00 0x2000>, 168 <0x00 0x48430000 0x00 0x4000>; 169 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", 170 "ring", "tchan", "rchan", "rflow"; 171 msi-parent = <&inta_main_dmss>; 172 #dma-cells = <2>; 173 174 ti,sci = <&dmsc>; 175 ti,sci-dev-id = <30>; 176 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 177 <0x24>, /* CPSW_TX_CHAN */ 178 <0x25>, /* SAUL_TX_0_CHAN */ 179 <0x26>, /* SAUL_TX_1_CHAN */ 180 <0x27>, /* ICSSG_0_TX_CHAN */ 181 <0x28>; /* ICSSG_1_TX_CHAN */ 182 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 183 <0x11>, /* RING_CPSW_TX_CHAN */ 184 <0x12>, /* RING_SAUL_TX_0_CHAN */ 185 <0x13>, /* RING_SAUL_TX_1_CHAN */ 186 <0x14>, /* RING_ICSSG_0_TX_CHAN */ 187 <0x15>; /* RING_ICSSG_1_TX_CHAN */ 188 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 189 <0x2b>, /* CPSW_RX_CHAN */ 190 <0x2d>, /* SAUL_RX_0_CHAN */ 191 <0x2f>, /* SAUL_RX_1_CHAN */ 192 <0x31>, /* SAUL_RX_2_CHAN */ 193 <0x33>, /* SAUL_RX_3_CHAN */ 194 <0x35>, /* ICSSG_0_RX_CHAN */ 195 <0x37>; /* ICSSG_1_RX_CHAN */ 196 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 197 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 198 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 199 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */ 200 <0x36>, /* FLOW_ICSSG_0_RX_CHAN */ 201 <0x38>; /* FLOW_ICSSG_1_RX_CHAN */ 202 }; 203 }; 204 205 dmsc: system-controller@44043000 { 206 bootph-all; 207 compatible = "ti,k2g-sci"; 208 ti,host-id = <12>; 209 mbox-names = "rx", "tx"; 210 mboxes = <&secure_proxy_main 12>, 211 <&secure_proxy_main 13>; 212 reg-names = "debug_messages"; 213 reg = <0x00 0x44043000 0x00 0xfe0>; 214 215 k3_pds: power-controller { 216 bootph-all; 217 compatible = "ti,sci-pm-domain"; 218 #power-domain-cells = <2>; 219 }; 220 221 k3_clks: clock-controller { 222 bootph-all; 223 compatible = "ti,k2g-sci-clk"; 224 #clock-cells = <2>; 225 }; 226 227 k3_reset: reset-controller { 228 bootph-all; 229 compatible = "ti,sci-reset"; 230 #reset-cells = <2>; 231 }; 232 }; 233 234 main_pmx0: pinctrl@f4000 { 235 bootph-all; 236 compatible = "pinctrl-single"; 237 reg = <0x00 0xf4000 0x00 0x2d0>; 238 #pinctrl-cells = <1>; 239 pinctrl-single,register-width = <32>; 240 pinctrl-single,function-mask = <0xffffffff>; 241 }; 242 243 main_timer0: timer@2400000 { 244 bootph-all; 245 compatible = "ti,am654-timer"; 246 reg = <0x00 0x2400000 0x00 0x400>; 247 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&k3_clks 36 1>; 249 clock-names = "fck"; 250 assigned-clocks = <&k3_clks 36 1>; 251 assigned-clock-parents = <&k3_clks 36 2>; 252 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 253 ti,timer-pwm; 254 }; 255 256 main_timer1: timer@2410000 { 257 compatible = "ti,am654-timer"; 258 reg = <0x00 0x2410000 0x00 0x400>; 259 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 260 clocks = <&k3_clks 37 1>; 261 clock-names = "fck"; 262 assigned-clocks = <&k3_clks 37 1>; 263 assigned-clock-parents = <&k3_clks 37 2>; 264 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 265 ti,timer-pwm; 266 }; 267 268 main_timer2: timer@2420000 { 269 compatible = "ti,am654-timer"; 270 reg = <0x00 0x2420000 0x00 0x400>; 271 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 272 clocks = <&k3_clks 38 1>; 273 clock-names = "fck"; 274 assigned-clocks = <&k3_clks 38 1>; 275 assigned-clock-parents = <&k3_clks 38 2>; 276 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 277 ti,timer-pwm; 278 }; 279 280 main_timer3: timer@2430000 { 281 compatible = "ti,am654-timer"; 282 reg = <0x00 0x2430000 0x00 0x400>; 283 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&k3_clks 39 1>; 285 clock-names = "fck"; 286 assigned-clocks = <&k3_clks 39 1>; 287 assigned-clock-parents = <&k3_clks 39 2>; 288 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 289 ti,timer-pwm; 290 }; 291 292 main_timer4: timer@2440000 { 293 compatible = "ti,am654-timer"; 294 reg = <0x00 0x2440000 0x00 0x400>; 295 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&k3_clks 40 1>; 297 clock-names = "fck"; 298 assigned-clocks = <&k3_clks 40 1>; 299 assigned-clock-parents = <&k3_clks 40 2>; 300 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 301 ti,timer-pwm; 302 }; 303 304 main_timer5: timer@2450000 { 305 compatible = "ti,am654-timer"; 306 reg = <0x00 0x2450000 0x00 0x400>; 307 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 308 clocks = <&k3_clks 41 1>; 309 clock-names = "fck"; 310 assigned-clocks = <&k3_clks 41 1>; 311 assigned-clock-parents = <&k3_clks 41 2>; 312 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 313 ti,timer-pwm; 314 }; 315 316 main_timer6: timer@2460000 { 317 compatible = "ti,am654-timer"; 318 reg = <0x00 0x2460000 0x00 0x400>; 319 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 320 clocks = <&k3_clks 42 1>; 321 clock-names = "fck"; 322 assigned-clocks = <&k3_clks 42 1>; 323 assigned-clock-parents = <&k3_clks 42 2>; 324 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 325 ti,timer-pwm; 326 }; 327 328 main_timer7: timer@2470000 { 329 compatible = "ti,am654-timer"; 330 reg = <0x00 0x2470000 0x00 0x400>; 331 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&k3_clks 43 1>; 333 clock-names = "fck"; 334 assigned-clocks = <&k3_clks 43 1>; 335 assigned-clock-parents = <&k3_clks 43 2>; 336 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 337 ti,timer-pwm; 338 }; 339 340 main_timer8: timer@2480000 { 341 compatible = "ti,am654-timer"; 342 reg = <0x00 0x2480000 0x00 0x400>; 343 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&k3_clks 44 1>; 345 clock-names = "fck"; 346 assigned-clocks = <&k3_clks 44 1>; 347 assigned-clock-parents = <&k3_clks 44 2>; 348 power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>; 349 ti,timer-pwm; 350 }; 351 352 main_timer9: timer@2490000 { 353 compatible = "ti,am654-timer"; 354 reg = <0x00 0x2490000 0x00 0x400>; 355 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 356 clocks = <&k3_clks 45 1>; 357 clock-names = "fck"; 358 assigned-clocks = <&k3_clks 45 1>; 359 assigned-clock-parents = <&k3_clks 45 2>; 360 power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>; 361 ti,timer-pwm; 362 }; 363 364 main_timer10: timer@24a0000 { 365 compatible = "ti,am654-timer"; 366 reg = <0x00 0x24a0000 0x00 0x400>; 367 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 368 clocks = <&k3_clks 46 1>; 369 clock-names = "fck"; 370 assigned-clocks = <&k3_clks 46 1>; 371 assigned-clock-parents = <&k3_clks 46 2>; 372 power-domains = <&k3_pds 46 TI_SCI_PD_EXCLUSIVE>; 373 ti,timer-pwm; 374 }; 375 376 main_timer11: timer@24b0000 { 377 compatible = "ti,am654-timer"; 378 reg = <0x00 0x24b0000 0x00 0x400>; 379 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 380 clocks = <&k3_clks 47 1>; 381 clock-names = "fck"; 382 assigned-clocks = <&k3_clks 47 1>; 383 assigned-clock-parents = <&k3_clks 47 2>; 384 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; 385 ti,timer-pwm; 386 }; 387 388 main_esm: esm@420000 { 389 bootph-pre-ram; 390 compatible = "ti,j721e-esm"; 391 reg = <0x00 0x420000 0x00 0x1000>; 392 /* Interrupt sources: rti0, rti1, rti8, rti9, rti10, rti11 */ 393 ti,esm-pins = <160>, <161>, <162>, <163>, <164>, <165>; 394 }; 395 396 main_uart0: serial@2800000 { 397 compatible = "ti,am64-uart", "ti,am654-uart"; 398 reg = <0x00 0x02800000 0x00 0x100>; 399 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 400 clock-frequency = <48000000>; 401 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 402 clocks = <&k3_clks 146 0>; 403 clock-names = "fclk"; 404 status = "disabled"; 405 }; 406 407 main_uart1: serial@2810000 { 408 compatible = "ti,am64-uart", "ti,am654-uart"; 409 reg = <0x00 0x02810000 0x00 0x100>; 410 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 411 clock-frequency = <48000000>; 412 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 413 clocks = <&k3_clks 152 0>; 414 clock-names = "fclk"; 415 status = "disabled"; 416 }; 417 418 main_uart2: serial@2820000 { 419 compatible = "ti,am64-uart", "ti,am654-uart"; 420 reg = <0x00 0x02820000 0x00 0x100>; 421 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 422 clock-frequency = <48000000>; 423 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 424 clocks = <&k3_clks 153 0>; 425 clock-names = "fclk"; 426 status = "disabled"; 427 }; 428 429 main_uart3: serial@2830000 { 430 compatible = "ti,am64-uart", "ti,am654-uart"; 431 reg = <0x00 0x02830000 0x00 0x100>; 432 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 433 clock-frequency = <48000000>; 434 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 435 clocks = <&k3_clks 154 0>; 436 clock-names = "fclk"; 437 status = "disabled"; 438 }; 439 440 main_uart4: serial@2840000 { 441 compatible = "ti,am64-uart", "ti,am654-uart"; 442 reg = <0x00 0x02840000 0x00 0x100>; 443 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 444 clock-frequency = <48000000>; 445 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 446 clocks = <&k3_clks 155 0>; 447 clock-names = "fclk"; 448 status = "disabled"; 449 }; 450 451 main_uart5: serial@2850000 { 452 compatible = "ti,am64-uart", "ti,am654-uart"; 453 reg = <0x00 0x02850000 0x00 0x100>; 454 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 455 clock-frequency = <48000000>; 456 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 457 clocks = <&k3_clks 156 0>; 458 clock-names = "fclk"; 459 status = "disabled"; 460 }; 461 462 main_uart6: serial@2860000 { 463 compatible = "ti,am64-uart", "ti,am654-uart"; 464 reg = <0x00 0x02860000 0x00 0x100>; 465 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 466 clock-frequency = <48000000>; 467 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 468 clocks = <&k3_clks 158 0>; 469 clock-names = "fclk"; 470 status = "disabled"; 471 }; 472 473 main_i2c0: i2c@20000000 { 474 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 475 reg = <0x00 0x20000000 0x00 0x100>; 476 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 480 clocks = <&k3_clks 102 2>; 481 clock-names = "fck"; 482 status = "disabled"; 483 }; 484 485 main_i2c1: i2c@20010000 { 486 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 487 reg = <0x00 0x20010000 0x00 0x100>; 488 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 489 #address-cells = <1>; 490 #size-cells = <0>; 491 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 492 clocks = <&k3_clks 103 2>; 493 clock-names = "fck"; 494 status = "disabled"; 495 }; 496 497 main_i2c2: i2c@20020000 { 498 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 499 reg = <0x00 0x20020000 0x00 0x100>; 500 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 501 #address-cells = <1>; 502 #size-cells = <0>; 503 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 504 clocks = <&k3_clks 104 2>; 505 clock-names = "fck"; 506 status = "disabled"; 507 }; 508 509 main_i2c3: i2c@20030000 { 510 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 511 reg = <0x00 0x20030000 0x00 0x100>; 512 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 516 clocks = <&k3_clks 105 2>; 517 clock-names = "fck"; 518 status = "disabled"; 519 }; 520 521 main_spi0: spi@20100000 { 522 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 523 reg = <0x00 0x20100000 0x00 0x400>; 524 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 525 #address-cells = <1>; 526 #size-cells = <0>; 527 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 528 clocks = <&k3_clks 141 0>; 529 dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>; 530 dma-names = "tx0", "rx0"; 531 status = "disabled"; 532 }; 533 534 main_spi1: spi@20110000 { 535 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 536 reg = <0x00 0x20110000 0x00 0x400>; 537 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 541 clocks = <&k3_clks 142 0>; 542 status = "disabled"; 543 }; 544 545 main_spi2: spi@20120000 { 546 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 547 reg = <0x00 0x20120000 0x00 0x400>; 548 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 552 clocks = <&k3_clks 143 0>; 553 status = "disabled"; 554 }; 555 556 main_spi3: spi@20130000 { 557 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 558 reg = <0x00 0x20130000 0x00 0x400>; 559 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 560 #address-cells = <1>; 561 #size-cells = <0>; 562 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; 563 clocks = <&k3_clks 144 0>; 564 status = "disabled"; 565 }; 566 567 main_spi4: spi@20140000 { 568 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 569 reg = <0x00 0x20140000 0x00 0x400>; 570 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 571 #address-cells = <1>; 572 #size-cells = <0>; 573 power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>; 574 clocks = <&k3_clks 145 0>; 575 status = "disabled"; 576 }; 577 578 main_gpio_intr: interrupt-controller@a00000 { 579 compatible = "ti,sci-intr"; 580 reg = <0x00 0x00a00000 0x00 0x800>; 581 ti,intr-trigger-type = <1>; 582 interrupt-controller; 583 interrupt-parent = <&gic500>; 584 #interrupt-cells = <1>; 585 ti,sci = <&dmsc>; 586 ti,sci-dev-id = <3>; 587 ti,interrupt-ranges = <0 32 16>; 588 }; 589 590 main_gpio0: gpio@600000 { 591 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 592 reg = <0x0 0x00600000 0x0 0x100>; 593 gpio-controller; 594 #gpio-cells = <2>; 595 interrupt-parent = <&main_gpio_intr>; 596 interrupts = <190>, <191>, <192>, 597 <193>, <194>, <195>; 598 interrupt-controller; 599 #interrupt-cells = <2>; 600 ti,ngpio = <87>; 601 ti,davinci-gpio-unbanked = <0>; 602 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 603 clocks = <&k3_clks 77 0>; 604 clock-names = "gpio"; 605 }; 606 607 main_gpio1: gpio@601000 { 608 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 609 reg = <0x0 0x00601000 0x0 0x100>; 610 gpio-controller; 611 #gpio-cells = <2>; 612 interrupt-parent = <&main_gpio_intr>; 613 interrupts = <180>, <181>, <182>, 614 <183>, <184>, <185>; 615 interrupt-controller; 616 #interrupt-cells = <2>; 617 ti,ngpio = <88>; 618 ti,davinci-gpio-unbanked = <0>; 619 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 620 clocks = <&k3_clks 78 0>; 621 clock-names = "gpio"; 622 }; 623 624 sdhci0: mmc@fa10000 { 625 compatible = "ti,am64-sdhci-8bit"; 626 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; 627 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 628 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 629 clocks = <&k3_clks 57 0>, <&k3_clks 57 1>; 630 clock-names = "clk_ahb", "clk_xin"; 631 bus-width = <8>; 632 mmc-ddr-1_8v; 633 mmc-hs200-1_8v; 634 ti,clkbuf-sel = <0x7>; 635 ti,trm-icp = <0x2>; 636 ti,otap-del-sel-legacy = <0x0>; 637 ti,otap-del-sel-mmc-hs = <0x0>; 638 ti,otap-del-sel-ddr52 = <0x6>; 639 ti,otap-del-sel-hs200 = <0x7>; 640 ti,itap-del-sel-legacy = <0x10>; 641 ti,itap-del-sel-mmc-hs = <0xa>; 642 ti,itap-del-sel-ddr52 = <0x3>; 643 status = "disabled"; 644 }; 645 646 sdhci1: mmc@fa00000 { 647 compatible = "ti,am64-sdhci-4bit"; 648 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; 649 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 650 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 651 clocks = <&k3_clks 58 3>, <&k3_clks 58 4>; 652 clock-names = "clk_ahb", "clk_xin"; 653 bus-width = <4>; 654 ti,clkbuf-sel = <0x7>; 655 ti,otap-del-sel-legacy = <0x0>; 656 ti,otap-del-sel-sd-hs = <0x0>; 657 ti,otap-del-sel-sdr12 = <0xf>; 658 ti,otap-del-sel-sdr25 = <0xf>; 659 ti,otap-del-sel-sdr50 = <0xc>; 660 ti,otap-del-sel-sdr104 = <0x6>; 661 ti,otap-del-sel-ddr50 = <0x9>; 662 ti,itap-del-sel-legacy = <0x0>; 663 ti,itap-del-sel-sd-hs = <0x0>; 664 ti,itap-del-sel-sdr12 = <0x0>; 665 ti,itap-del-sel-sdr25 = <0x0>; 666 status = "disabled"; 667 }; 668 669 cpsw3g: ethernet@8000000 { 670 compatible = "ti,am642-cpsw-nuss"; 671 #address-cells = <2>; 672 #size-cells = <2>; 673 reg = <0x0 0x8000000 0x0 0x200000>; 674 reg-names = "cpsw_nuss"; 675 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>; 676 clocks = <&k3_clks 13 0>; 677 assigned-clocks = <&k3_clks 13 1>; 678 assigned-clock-parents = <&k3_clks 13 9>; 679 clock-names = "fck"; 680 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 681 status = "disabled"; 682 683 dmas = <&main_pktdma 0xC500 15>, 684 <&main_pktdma 0xC501 15>, 685 <&main_pktdma 0xC502 15>, 686 <&main_pktdma 0xC503 15>, 687 <&main_pktdma 0xC504 15>, 688 <&main_pktdma 0xC505 15>, 689 <&main_pktdma 0xC506 15>, 690 <&main_pktdma 0xC507 15>, 691 <&main_pktdma 0x4500 15>; 692 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 693 "tx7", "rx"; 694 695 ethernet-ports { 696 #address-cells = <1>; 697 #size-cells = <0>; 698 699 cpsw_port1: port@1 { 700 reg = <1>; 701 ti,mac-only; 702 label = "port1"; 703 phys = <&phy_gmii_sel 1>; 704 mac-address = [00 00 00 00 00 00]; 705 ti,syscon-efuse = <&main_conf 0x200>; 706 status = "disabled"; 707 }; 708 709 cpsw_port2: port@2 { 710 reg = <2>; 711 ti,mac-only; 712 label = "port2"; 713 phys = <&phy_gmii_sel 2>; 714 mac-address = [00 00 00 00 00 00]; 715 status = "disabled"; 716 }; 717 }; 718 719 cpsw3g_mdio: mdio@f00 { 720 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 721 reg = <0x0 0xf00 0x0 0x100>; 722 #address-cells = <1>; 723 #size-cells = <0>; 724 clocks = <&k3_clks 13 0>; 725 clock-names = "fck"; 726 bus_freq = <1000000>; 727 status = "disabled"; 728 }; 729 730 cpts@3d000 { 731 compatible = "ti,j721e-cpts"; 732 reg = <0x0 0x3d000 0x0 0x400>; 733 clocks = <&k3_clks 13 1>; 734 clock-names = "cpts"; 735 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 736 interrupt-names = "cpts"; 737 ti,cpts-ext-ts-inputs = <4>; 738 ti,cpts-periodic-outputs = <2>; 739 }; 740 }; 741 742 main_cpts0: cpts@39000000 { 743 compatible = "ti,j721e-cpts"; 744 reg = <0x0 0x39000000 0x0 0x400>; 745 reg-names = "cpts"; 746 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; 747 clocks = <&k3_clks 84 0>; 748 clock-names = "cpts"; 749 assigned-clocks = <&k3_clks 84 0>; 750 assigned-clock-parents = <&k3_clks 84 8>; 751 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 752 interrupt-names = "cpts"; 753 ti,cpts-periodic-outputs = <6>; 754 ti,cpts-ext-ts-inputs = <8>; 755 }; 756 757 timesync_router: pinctrl@a40000 { 758 compatible = "pinctrl-single"; 759 reg = <0x0 0xa40000 0x0 0x800>; 760 #pinctrl-cells = <1>; 761 pinctrl-single,register-width = <32>; 762 pinctrl-single,function-mask = <0x000107ff>; 763 }; 764 765 usbss0: cdns-usb@f900000 { 766 compatible = "ti,am64-usb", "ti,j721e-usb"; 767 reg = <0x00 0xf900000 0x00 0x100>; 768 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 769 clocks = <&k3_clks 161 9>, <&k3_clks 161 1>; 770 clock-names = "ref", "lpm"; 771 assigned-clocks = <&k3_clks 161 9>; /* USB2_REFCLK */ 772 assigned-clock-parents = <&k3_clks 161 10>; /* HF0SC0 */ 773 #address-cells = <2>; 774 #size-cells = <2>; 775 ranges; 776 usb0: usb@f400000 { 777 compatible = "cdns,usb3"; 778 reg = <0x00 0xf400000 0x00 0x10000>, 779 <0x00 0xf410000 0x00 0x10000>, 780 <0x00 0xf420000 0x00 0x10000>; 781 reg-names = "otg", 782 "xhci", 783 "dev"; 784 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 785 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 786 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */ 787 interrupt-names = "host", 788 "peripheral", 789 "otg"; 790 maximum-speed = "super-speed"; 791 dr_mode = "otg"; 792 }; 793 }; 794 795 tscadc0: tscadc@28001000 { 796 compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; 797 reg = <0x00 0x28001000 0x00 0x1000>; 798 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 799 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 800 clocks = <&k3_clks 0 0>; 801 assigned-clocks = <&k3_clks 0 0>; 802 assigned-clock-parents = <&k3_clks 0 3>; 803 assigned-clock-rates = <60000000>; 804 clock-names = "fck"; 805 status = "disabled"; 806 807 adc { 808 #io-channel-cells = <1>; 809 compatible = "ti,am654-adc", "ti,am3359-adc"; 810 }; 811 }; 812 813 fss: bus@fc00000 { 814 compatible = "simple-bus"; 815 reg = <0x00 0x0fc00000 0x00 0x70000>; 816 #address-cells = <2>; 817 #size-cells = <2>; 818 ranges; 819 820 ospi0: spi@fc40000 { 821 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 822 reg = <0x00 0x0fc40000 0x00 0x100>, 823 <0x05 0x00000000 0x01 0x00000000>; 824 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 825 cdns,fifo-depth = <256>; 826 cdns,fifo-width = <4>; 827 cdns,trigger-address = <0x0>; 828 #address-cells = <0x1>; 829 #size-cells = <0x0>; 830 clocks = <&k3_clks 75 6>; 831 assigned-clocks = <&k3_clks 75 6>; 832 assigned-clock-parents = <&k3_clks 75 7>; 833 assigned-clock-rates = <166666666>; 834 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 835 status = "disabled"; 836 }; 837 }; 838 839 hwspinlock: spinlock@2a000000 { 840 compatible = "ti,am64-hwspinlock"; 841 reg = <0x00 0x2a000000 0x00 0x1000>; 842 #hwlock-cells = <1>; 843 }; 844 845 mailbox0_cluster2: mailbox@29020000 { 846 compatible = "ti,am64-mailbox"; 847 reg = <0x00 0x29020000 0x00 0x200>; 848 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 849 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 850 #mbox-cells = <1>; 851 ti,mbox-num-users = <4>; 852 ti,mbox-num-fifos = <16>; 853 status = "disabled"; 854 }; 855 856 mailbox0_cluster3: mailbox@29030000 { 857 compatible = "ti,am64-mailbox"; 858 reg = <0x00 0x29030000 0x00 0x200>; 859 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 861 #mbox-cells = <1>; 862 ti,mbox-num-users = <4>; 863 ti,mbox-num-fifos = <16>; 864 status = "disabled"; 865 }; 866 867 mailbox0_cluster4: mailbox@29040000 { 868 compatible = "ti,am64-mailbox"; 869 reg = <0x00 0x29040000 0x00 0x200>; 870 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 872 #mbox-cells = <1>; 873 ti,mbox-num-users = <4>; 874 ti,mbox-num-fifos = <16>; 875 status = "disabled"; 876 }; 877 878 mailbox0_cluster5: mailbox@29050000 { 879 compatible = "ti,am64-mailbox"; 880 reg = <0x00 0x29050000 0x00 0x200>; 881 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 883 #mbox-cells = <1>; 884 ti,mbox-num-users = <4>; 885 ti,mbox-num-fifos = <16>; 886 status = "disabled"; 887 }; 888 889 mailbox0_cluster6: mailbox@29060000 { 890 compatible = "ti,am64-mailbox"; 891 reg = <0x00 0x29060000 0x00 0x200>; 892 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 893 #mbox-cells = <1>; 894 ti,mbox-num-users = <4>; 895 ti,mbox-num-fifos = <16>; 896 status = "disabled"; 897 }; 898 899 mailbox0_cluster7: mailbox@29070000 { 900 compatible = "ti,am64-mailbox"; 901 reg = <0x00 0x29070000 0x00 0x200>; 902 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 903 #mbox-cells = <1>; 904 ti,mbox-num-users = <4>; 905 ti,mbox-num-fifos = <16>; 906 status = "disabled"; 907 }; 908 909 main_r5fss0: r5fss@78000000 { 910 compatible = "ti,am64-r5fss"; 911 ti,cluster-mode = <0>; 912 #address-cells = <1>; 913 #size-cells = <1>; 914 ranges = <0x78000000 0x00 0x78000000 0x10000>, 915 <0x78100000 0x00 0x78100000 0x10000>, 916 <0x78200000 0x00 0x78200000 0x08000>, 917 <0x78300000 0x00 0x78300000 0x08000>; 918 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; 919 920 main_r5fss0_core0: r5f@78000000 { 921 compatible = "ti,am64-r5f"; 922 reg = <0x78000000 0x00010000>, 923 <0x78100000 0x00010000>; 924 reg-names = "atcm", "btcm"; 925 ti,sci = <&dmsc>; 926 ti,sci-dev-id = <121>; 927 ti,sci-proc-ids = <0x01 0xff>; 928 resets = <&k3_reset 121 1>; 929 firmware-name = "am64-main-r5f0_0-fw"; 930 ti,atcm-enable = <1>; 931 ti,btcm-enable = <1>; 932 ti,loczrama = <1>; 933 }; 934 935 main_r5fss0_core1: r5f@78200000 { 936 compatible = "ti,am64-r5f"; 937 reg = <0x78200000 0x00008000>, 938 <0x78300000 0x00008000>; 939 reg-names = "atcm", "btcm"; 940 ti,sci = <&dmsc>; 941 ti,sci-dev-id = <122>; 942 ti,sci-proc-ids = <0x02 0xff>; 943 resets = <&k3_reset 122 1>; 944 firmware-name = "am64-main-r5f0_1-fw"; 945 ti,atcm-enable = <1>; 946 ti,btcm-enable = <1>; 947 ti,loczrama = <1>; 948 }; 949 }; 950 951 main_r5fss1: r5fss@78400000 { 952 compatible = "ti,am64-r5fss"; 953 ti,cluster-mode = <0>; 954 #address-cells = <1>; 955 #size-cells = <1>; 956 ranges = <0x78400000 0x00 0x78400000 0x10000>, 957 <0x78500000 0x00 0x78500000 0x10000>, 958 <0x78600000 0x00 0x78600000 0x08000>, 959 <0x78700000 0x00 0x78700000 0x08000>; 960 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 961 962 main_r5fss1_core0: r5f@78400000 { 963 compatible = "ti,am64-r5f"; 964 reg = <0x78400000 0x00010000>, 965 <0x78500000 0x00010000>; 966 reg-names = "atcm", "btcm"; 967 ti,sci = <&dmsc>; 968 ti,sci-dev-id = <123>; 969 ti,sci-proc-ids = <0x06 0xff>; 970 resets = <&k3_reset 123 1>; 971 firmware-name = "am64-main-r5f1_0-fw"; 972 ti,atcm-enable = <1>; 973 ti,btcm-enable = <1>; 974 ti,loczrama = <1>; 975 }; 976 977 main_r5fss1_core1: r5f@78600000 { 978 compatible = "ti,am64-r5f"; 979 reg = <0x78600000 0x00008000>, 980 <0x78700000 0x00008000>; 981 reg-names = "atcm", "btcm"; 982 ti,sci = <&dmsc>; 983 ti,sci-dev-id = <124>; 984 ti,sci-proc-ids = <0x07 0xff>; 985 resets = <&k3_reset 124 1>; 986 firmware-name = "am64-main-r5f1_1-fw"; 987 ti,atcm-enable = <1>; 988 ti,btcm-enable = <1>; 989 ti,loczrama = <1>; 990 }; 991 }; 992 993 serdes_wiz0: wiz@f000000 { 994 compatible = "ti,am64-wiz-10g"; 995 #address-cells = <1>; 996 #size-cells = <1>; 997 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 998 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>; 999 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 1000 num-lanes = <1>; 1001 #reset-cells = <1>; 1002 #clock-cells = <1>; 1003 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; 1004 1005 assigned-clocks = <&k3_clks 162 1>; 1006 assigned-clock-parents = <&k3_clks 162 5>; 1007 1008 serdes0: serdes@f000000 { 1009 compatible = "ti,j721e-serdes-10g"; 1010 reg = <0x0f000000 0x00010000>; 1011 reg-names = "torrent_phy"; 1012 resets = <&serdes_wiz0 0>; 1013 reset-names = "torrent_reset"; 1014 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1015 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; 1016 clock-names = "refclk", "phy_en_refclk"; 1017 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1018 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, 1019 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; 1020 assigned-clock-parents = <&k3_clks 162 1>, 1021 <&k3_clks 162 1>, 1022 <&k3_clks 162 1>; 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 #clock-cells = <1>; 1026 }; 1027 }; 1028 1029 pcie0_rc: pcie@f102000 { 1030 compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host"; 1031 reg = <0x00 0x0f102000 0x00 0x1000>, 1032 <0x00 0x0f100000 0x00 0x400>, 1033 <0x00 0x0d000000 0x00 0x00800000>, 1034 <0x00 0x68000000 0x00 0x00001000>; 1035 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1036 interrupt-names = "link_state"; 1037 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 1038 device_type = "pci"; 1039 ti,syscon-pcie-ctrl = <&main_conf 0x4070>; 1040 max-link-speed = <2>; 1041 num-lanes = <1>; 1042 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 1043 clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; 1044 clock-names = "fck", "pcie_refclk"; 1045 #address-cells = <3>; 1046 #size-cells = <2>; 1047 bus-range = <0x0 0xff>; 1048 cdns,no-bar-match-nbits = <64>; 1049 vendor-id = <0x104c>; 1050 device-id = <0xb010>; 1051 msi-map = <0x0 &gic_its 0x0 0x10000>; 1052 ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, 1053 <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; 1054 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>; 1055 status = "disabled"; 1056 }; 1057 1058 epwm0: pwm@23000000 { 1059 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1060 #pwm-cells = <3>; 1061 reg = <0x0 0x23000000 0x0 0x100>; 1062 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 1063 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 1064 clock-names = "tbclk", "fck"; 1065 status = "disabled"; 1066 }; 1067 1068 epwm1: pwm@23010000 { 1069 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1070 #pwm-cells = <3>; 1071 reg = <0x0 0x23010000 0x0 0x100>; 1072 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 1073 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 1074 clock-names = "tbclk", "fck"; 1075 status = "disabled"; 1076 }; 1077 1078 epwm2: pwm@23020000 { 1079 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1080 #pwm-cells = <3>; 1081 reg = <0x0 0x23020000 0x0 0x100>; 1082 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 1083 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 1084 clock-names = "tbclk", "fck"; 1085 status = "disabled"; 1086 }; 1087 1088 epwm3: pwm@23030000 { 1089 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1090 #pwm-cells = <3>; 1091 reg = <0x0 0x23030000 0x0 0x100>; 1092 power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; 1093 clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>; 1094 clock-names = "tbclk", "fck"; 1095 status = "disabled"; 1096 }; 1097 1098 epwm4: pwm@23040000 { 1099 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1100 #pwm-cells = <3>; 1101 reg = <0x0 0x23040000 0x0 0x100>; 1102 power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; 1103 clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>; 1104 clock-names = "tbclk", "fck"; 1105 status = "disabled"; 1106 }; 1107 1108 epwm5: pwm@23050000 { 1109 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1110 #pwm-cells = <3>; 1111 reg = <0x0 0x23050000 0x0 0x100>; 1112 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 1113 clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>; 1114 clock-names = "tbclk", "fck"; 1115 status = "disabled"; 1116 }; 1117 1118 epwm6: pwm@23060000 { 1119 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1120 #pwm-cells = <3>; 1121 reg = <0x0 0x23060000 0x0 0x100>; 1122 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 1123 clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>; 1124 clock-names = "tbclk", "fck"; 1125 status = "disabled"; 1126 }; 1127 1128 epwm7: pwm@23070000 { 1129 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1130 #pwm-cells = <3>; 1131 reg = <0x0 0x23070000 0x0 0x100>; 1132 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 1133 clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>; 1134 clock-names = "tbclk", "fck"; 1135 status = "disabled"; 1136 }; 1137 1138 epwm8: pwm@23080000 { 1139 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1140 #pwm-cells = <3>; 1141 reg = <0x0 0x23080000 0x0 0x100>; 1142 power-domains = <&k3_pds 94 TI_SCI_PD_EXCLUSIVE>; 1143 clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>; 1144 clock-names = "tbclk", "fck"; 1145 status = "disabled"; 1146 }; 1147 1148 ecap0: pwm@23100000 { 1149 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 1150 #pwm-cells = <3>; 1151 reg = <0x0 0x23100000 0x0 0x60>; 1152 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 1153 clocks = <&k3_clks 51 0>; 1154 clock-names = "fck"; 1155 status = "disabled"; 1156 }; 1157 1158 ecap1: pwm@23110000 { 1159 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 1160 #pwm-cells = <3>; 1161 reg = <0x0 0x23110000 0x0 0x60>; 1162 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 1163 clocks = <&k3_clks 52 0>; 1164 clock-names = "fck"; 1165 status = "disabled"; 1166 }; 1167 1168 ecap2: pwm@23120000 { 1169 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 1170 #pwm-cells = <3>; 1171 reg = <0x0 0x23120000 0x0 0x60>; 1172 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 1173 clocks = <&k3_clks 53 0>; 1174 clock-names = "fck"; 1175 status = "disabled"; 1176 }; 1177 1178 main_rti0: watchdog@e000000 { 1179 compatible = "ti,j7-rti-wdt"; 1180 reg = <0x00 0xe000000 0x00 0x100>; 1181 clocks = <&k3_clks 125 0>; 1182 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 1183 assigned-clocks = <&k3_clks 125 0>; 1184 assigned-clock-parents = <&k3_clks 125 2>; 1185 }; 1186 1187 main_rti1: watchdog@e010000 { 1188 compatible = "ti,j7-rti-wdt"; 1189 reg = <0x00 0xe010000 0x00 0x100>; 1190 clocks = <&k3_clks 126 0>; 1191 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; 1192 assigned-clocks = <&k3_clks 126 0>; 1193 assigned-clock-parents = <&k3_clks 126 2>; 1194 }; 1195 1196 icssg0: icssg@30000000 { 1197 compatible = "ti,am642-icssg"; 1198 reg = <0x00 0x30000000 0x00 0x80000>; 1199 power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; 1200 #address-cells = <1>; 1201 #size-cells = <1>; 1202 ranges = <0x0 0x00 0x30000000 0x80000>; 1203 1204 icssg0_mem: memories@0 { 1205 reg = <0x0 0x2000>, 1206 <0x2000 0x2000>, 1207 <0x10000 0x10000>; 1208 reg-names = "dram0", "dram1", "shrdram2"; 1209 }; 1210 1211 icssg0_cfg: cfg@26000 { 1212 compatible = "ti,pruss-cfg", "syscon"; 1213 reg = <0x26000 0x200>; 1214 #address-cells = <1>; 1215 #size-cells = <1>; 1216 ranges = <0x0 0x26000 0x2000>; 1217 1218 clocks { 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 1222 icssg0_coreclk_mux: coreclk-mux@3c { 1223 reg = <0x3c>; 1224 #clock-cells = <0>; 1225 clocks = <&k3_clks 81 0>, /* icssg0_core_clk */ 1226 <&k3_clks 81 20>; /* icssg0_iclk */ 1227 assigned-clocks = <&icssg0_coreclk_mux>; 1228 assigned-clock-parents = <&k3_clks 81 20>; 1229 }; 1230 1231 icssg0_iepclk_mux: iepclk-mux@30 { 1232 reg = <0x30>; 1233 #clock-cells = <0>; 1234 clocks = <&k3_clks 81 3>, /* icssg0_iep_clk */ 1235 <&icssg0_coreclk_mux>; /* icssg0_coreclk_mux */ 1236 assigned-clocks = <&icssg0_iepclk_mux>; 1237 assigned-clock-parents = <&icssg0_coreclk_mux>; 1238 }; 1239 }; 1240 }; 1241 1242 icssg0_iep0: iep@2e000 { 1243 compatible = "ti,am654-icss-iep"; 1244 reg = <0x2e000 0x1000>; 1245 clocks = <&icssg0_iepclk_mux>; 1246 }; 1247 1248 icssg0_iep1: iep@2f000 { 1249 compatible = "ti,am654-icss-iep"; 1250 reg = <0x2f000 0x1000>; 1251 clocks = <&icssg0_iepclk_mux>; 1252 }; 1253 1254 icssg0_mii_rt: mii-rt@32000 { 1255 compatible = "ti,pruss-mii", "syscon"; 1256 reg = <0x32000 0x100>; 1257 }; 1258 1259 icssg0_mii_g_rt: mii-g-rt@33000 { 1260 compatible = "ti,pruss-mii-g", "syscon"; 1261 reg = <0x33000 0x1000>; 1262 }; 1263 1264 icssg0_intc: interrupt-controller@20000 { 1265 compatible = "ti,icssg-intc"; 1266 reg = <0x20000 0x2000>; 1267 interrupt-controller; 1268 #interrupt-cells = <3>; 1269 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1276 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1277 interrupt-names = "host_intr0", "host_intr1", 1278 "host_intr2", "host_intr3", 1279 "host_intr4", "host_intr5", 1280 "host_intr6", "host_intr7"; 1281 }; 1282 1283 pru0_0: pru@34000 { 1284 compatible = "ti,am642-pru"; 1285 reg = <0x34000 0x3000>, 1286 <0x22000 0x100>, 1287 <0x22400 0x100>; 1288 reg-names = "iram", "control", "debug"; 1289 firmware-name = "am64x-pru0_0-fw"; 1290 interrupt-parent = <&icssg0_intc>; 1291 interrupts = <16 2 2>; 1292 interrupt-names = "vring"; 1293 }; 1294 1295 rtu0_0: rtu@4000 { 1296 compatible = "ti,am642-rtu"; 1297 reg = <0x4000 0x2000>, 1298 <0x23000 0x100>, 1299 <0x23400 0x100>; 1300 reg-names = "iram", "control", "debug"; 1301 firmware-name = "am64x-rtu0_0-fw"; 1302 interrupt-parent = <&icssg0_intc>; 1303 interrupts = <20 4 4>; 1304 interrupt-names = "vring"; 1305 }; 1306 1307 tx_pru0_0: txpru@a000 { 1308 compatible = "ti,am642-tx-pru"; 1309 reg = <0xa000 0x1800>, 1310 <0x25000 0x100>, 1311 <0x25400 0x100>; 1312 reg-names = "iram", "control", "debug"; 1313 firmware-name = "am64x-txpru0_0-fw"; 1314 }; 1315 1316 pru0_1: pru@38000 { 1317 compatible = "ti,am642-pru"; 1318 reg = <0x38000 0x3000>, 1319 <0x24000 0x100>, 1320 <0x24400 0x100>; 1321 reg-names = "iram", "control", "debug"; 1322 firmware-name = "am64x-pru0_1-fw"; 1323 interrupt-parent = <&icssg0_intc>; 1324 interrupts = <18 3 3>; 1325 interrupt-names = "vring"; 1326 }; 1327 1328 rtu0_1: rtu@6000 { 1329 compatible = "ti,am642-rtu"; 1330 reg = <0x6000 0x2000>, 1331 <0x23800 0x100>, 1332 <0x23c00 0x100>; 1333 reg-names = "iram", "control", "debug"; 1334 firmware-name = "am64x-rtu0_1-fw"; 1335 interrupt-parent = <&icssg0_intc>; 1336 interrupts = <22 5 5>; 1337 interrupt-names = "vring"; 1338 }; 1339 1340 tx_pru0_1: txpru@c000 { 1341 compatible = "ti,am642-tx-pru"; 1342 reg = <0xc000 0x1800>, 1343 <0x25800 0x100>, 1344 <0x25c00 0x100>; 1345 reg-names = "iram", "control", "debug"; 1346 firmware-name = "am64x-txpru0_1-fw"; 1347 }; 1348 1349 icssg0_mdio: mdio@32400 { 1350 compatible = "ti,davinci_mdio"; 1351 reg = <0x32400 0x100>; 1352 clocks = <&k3_clks 62 3>; 1353 clock-names = "fck"; 1354 #address-cells = <1>; 1355 #size-cells = <0>; 1356 bus_freq = <1000000>; 1357 status = "disabled"; 1358 }; 1359 }; 1360 1361 icssg1: icssg@30080000 { 1362 compatible = "ti,am642-icssg"; 1363 reg = <0x00 0x30080000 0x00 0x80000>; 1364 power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>; 1365 #address-cells = <1>; 1366 #size-cells = <1>; 1367 ranges = <0x0 0x00 0x30080000 0x80000>; 1368 1369 icssg1_mem: memories@0 { 1370 reg = <0x0 0x2000>, 1371 <0x2000 0x2000>, 1372 <0x10000 0x10000>; 1373 reg-names = "dram0", "dram1", "shrdram2"; 1374 }; 1375 1376 icssg1_cfg: cfg@26000 { 1377 compatible = "ti,pruss-cfg", "syscon"; 1378 reg = <0x26000 0x200>; 1379 #address-cells = <1>; 1380 #size-cells = <1>; 1381 ranges = <0x0 0x26000 0x2000>; 1382 1383 clocks { 1384 #address-cells = <1>; 1385 #size-cells = <0>; 1386 1387 icssg1_coreclk_mux: coreclk-mux@3c { 1388 reg = <0x3c>; 1389 #clock-cells = <0>; 1390 clocks = <&k3_clks 82 0>, /* icssg1_core_clk */ 1391 <&k3_clks 82 20>; /* icssg1_iclk */ 1392 assigned-clocks = <&icssg1_coreclk_mux>; 1393 assigned-clock-parents = <&k3_clks 82 20>; 1394 }; 1395 1396 icssg1_iepclk_mux: iepclk-mux@30 { 1397 reg = <0x30>; 1398 #clock-cells = <0>; 1399 clocks = <&k3_clks 82 3>, /* icssg1_iep_clk */ 1400 <&icssg1_coreclk_mux>; /* icssg1_coreclk_mux */ 1401 assigned-clocks = <&icssg1_iepclk_mux>; 1402 assigned-clock-parents = <&icssg1_coreclk_mux>; 1403 }; 1404 }; 1405 }; 1406 1407 icssg1_iep0: iep@2e000 { 1408 compatible = "ti,am654-icss-iep"; 1409 reg = <0x2e000 0x1000>; 1410 clocks = <&icssg1_iepclk_mux>; 1411 }; 1412 1413 icssg1_iep1: iep@2f000 { 1414 compatible = "ti,am654-icss-iep"; 1415 reg = <0x2f000 0x1000>; 1416 clocks = <&icssg1_iepclk_mux>; 1417 }; 1418 1419 icssg1_mii_rt: mii-rt@32000 { 1420 compatible = "ti,pruss-mii", "syscon"; 1421 reg = <0x32000 0x100>; 1422 }; 1423 1424 icssg1_mii_g_rt: mii-g-rt@33000 { 1425 compatible = "ti,pruss-mii-g", "syscon"; 1426 reg = <0x33000 0x1000>; 1427 }; 1428 1429 icssg1_intc: interrupt-controller@20000 { 1430 compatible = "ti,icssg-intc"; 1431 reg = <0x20000 0x2000>; 1432 interrupt-controller; 1433 #interrupt-cells = <3>; 1434 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1435 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1436 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1437 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1438 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1439 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 1440 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 1441 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1442 interrupt-names = "host_intr0", "host_intr1", 1443 "host_intr2", "host_intr3", 1444 "host_intr4", "host_intr5", 1445 "host_intr6", "host_intr7"; 1446 }; 1447 1448 pru1_0: pru@34000 { 1449 compatible = "ti,am642-pru"; 1450 reg = <0x34000 0x4000>, 1451 <0x22000 0x100>, 1452 <0x22400 0x100>; 1453 reg-names = "iram", "control", "debug"; 1454 firmware-name = "am64x-pru1_0-fw"; 1455 interrupt-parent = <&icssg1_intc>; 1456 interrupts = <16 2 2>; 1457 interrupt-names = "vring"; 1458 }; 1459 1460 rtu1_0: rtu@4000 { 1461 compatible = "ti,am642-rtu"; 1462 reg = <0x4000 0x2000>, 1463 <0x23000 0x100>, 1464 <0x23400 0x100>; 1465 reg-names = "iram", "control", "debug"; 1466 firmware-name = "am64x-rtu1_0-fw"; 1467 interrupt-parent = <&icssg1_intc>; 1468 interrupts = <20 4 4>; 1469 interrupt-names = "vring"; 1470 }; 1471 1472 tx_pru1_0: txpru@a000 { 1473 compatible = "ti,am642-tx-pru"; 1474 reg = <0xa000 0x1800>, 1475 <0x25000 0x100>, 1476 <0x25400 0x100>; 1477 reg-names = "iram", "control", "debug"; 1478 firmware-name = "am64x-txpru1_0-fw"; 1479 }; 1480 1481 pru1_1: pru@38000 { 1482 compatible = "ti,am642-pru"; 1483 reg = <0x38000 0x4000>, 1484 <0x24000 0x100>, 1485 <0x24400 0x100>; 1486 reg-names = "iram", "control", "debug"; 1487 firmware-name = "am64x-pru1_1-fw"; 1488 interrupt-parent = <&icssg1_intc>; 1489 interrupts = <18 3 3>; 1490 interrupt-names = "vring"; 1491 }; 1492 1493 rtu1_1: rtu@6000 { 1494 compatible = "ti,am642-rtu"; 1495 reg = <0x6000 0x2000>, 1496 <0x23800 0x100>, 1497 <0x23c00 0x100>; 1498 reg-names = "iram", "control", "debug"; 1499 firmware-name = "am64x-rtu1_1-fw"; 1500 interrupt-parent = <&icssg1_intc>; 1501 interrupts = <22 5 5>; 1502 interrupt-names = "vring"; 1503 }; 1504 1505 tx_pru1_1: txpru@c000 { 1506 compatible = "ti,am642-tx-pru"; 1507 reg = <0xc000 0x1800>, 1508 <0x25800 0x100>, 1509 <0x25c00 0x100>; 1510 reg-names = "iram", "control", "debug"; 1511 firmware-name = "am64x-txpru1_1-fw"; 1512 }; 1513 1514 icssg1_mdio: mdio@32400 { 1515 compatible = "ti,davinci_mdio"; 1516 reg = <0x32400 0x100>; 1517 #address-cells = <1>; 1518 #size-cells = <0>; 1519 clocks = <&k3_clks 82 0>; 1520 clock-names = "fck"; 1521 bus_freq = <1000000>; 1522 status = "disabled"; 1523 }; 1524 }; 1525 1526 main_mcan0: can@20701000 { 1527 compatible = "bosch,m_can"; 1528 reg = <0x00 0x20701000 0x00 0x200>, 1529 <0x00 0x20708000 0x00 0x8000>; 1530 reg-names = "m_can", "message_ram"; 1531 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 1532 clocks = <&k3_clks 98 5>, <&k3_clks 98 0>; 1533 clock-names = "hclk", "cclk"; 1534 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1536 interrupt-names = "int0", "int1"; 1537 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1538 status = "disabled"; 1539 }; 1540 1541 main_mcan1: can@20711000 { 1542 compatible = "bosch,m_can"; 1543 reg = <0x00 0x20711000 0x00 0x200>, 1544 <0x00 0x20718000 0x00 0x8000>; 1545 reg-names = "m_can", "message_ram"; 1546 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 1547 clocks = <&k3_clks 99 5>, <&k3_clks 99 0>; 1548 clock-names = "hclk", "cclk"; 1549 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1550 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1551 interrupt-names = "int0", "int1"; 1552 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1553 status = "disabled"; 1554 }; 1555 1556 crypto: crypto@40900000 { 1557 compatible = "ti,am64-sa2ul"; 1558 reg = <0x00 0x40900000 0x00 0x1200>; 1559 power-domains = <&k3_pds 133 TI_SCI_PD_SHARED>; 1560 #address-cells = <2>; 1561 #size-cells = <2>; 1562 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; 1563 dmas = <&main_pktdma 0xc001 0>, <&main_pktdma 0x4002 0>, 1564 <&main_pktdma 0x4003 0>; 1565 dma-names = "tx", "rx1", "rx2"; 1566 1567 rng: rng@40910000 { 1568 compatible = "inside-secure,safexcel-eip76"; 1569 reg = <0x00 0x40910000 0x00 0x7d>; 1570 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1571 status = "disabled"; /* Used by OP-TEE */ 1572 }; 1573 }; 1574 1575 gpmc0: memory-controller@3b000000 { 1576 compatible = "ti,am64-gpmc"; 1577 power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; 1578 clocks = <&k3_clks 80 0>; 1579 clock-names = "fck"; 1580 reg = <0x00 0x3b000000 0x00 0x400>, 1581 <0x00 0x50000000 0x00 0x8000000>; 1582 reg-names = "cfg", "data"; 1583 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1584 gpmc,num-cs = <3>; 1585 gpmc,num-waitpins = <2>; 1586 #address-cells = <2>; 1587 #size-cells = <1>; 1588 interrupt-controller; 1589 #interrupt-cells = <2>; 1590 gpio-controller; 1591 #gpio-cells = <2>; 1592 status = "disabled"; 1593 }; 1594 1595 elm0: ecc@25010000 { 1596 compatible = "ti,am64-elm"; 1597 reg = <0x00 0x25010000 0x00 0x2000>; 1598 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 1599 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; 1600 clocks = <&k3_clks 54 0>; 1601 clock-names = "fck"; 1602 status = "disabled"; 1603 }; 1604 1605 main_vtm0: temperature-sensor@b00000 { 1606 compatible = "ti,j7200-vtm"; 1607 reg = <0x00 0xb00000 0x00 0x400>, 1608 <0x00 0xb01000 0x00 0x400>; 1609 power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>; 1610 #thermal-sensor-cells = <1>; 1611 }; 1612}; 1613