1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM642 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/phy/phy-cadence.h> 9#include <dt-bindings/phy/phy-ti.h> 10 11/ { 12 serdes_refclk: clock-cmnrefclk { 13 #clock-cells = <0>; 14 compatible = "fixed-clock"; 15 clock-frequency = <0>; 16 }; 17}; 18 19&cbass_main { 20 oc_sram: sram@70000000 { 21 compatible = "mmio-sram"; 22 reg = <0x00 0x70000000 0x00 0x200000>; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 ranges = <0x0 0x00 0x70000000 0x200000>; 26 27 tfa-sram@1c0000 { 28 reg = <0x1c0000 0x20000>; 29 }; 30 31 dmsc-sram@1e0000 { 32 reg = <0x1e0000 0x1c000>; 33 }; 34 35 sproxy-sram@1fc000 { 36 reg = <0x1fc000 0x4000>; 37 }; 38 }; 39 40 main_conf: syscon@43000000 { 41 bootph-all; 42 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 43 reg = <0x0 0x43000000 0x0 0x20000>; 44 #address-cells = <1>; 45 #size-cells = <1>; 46 ranges = <0x0 0x0 0x43000000 0x20000>; 47 48 chipid@14 { 49 bootph-all; 50 compatible = "ti,am654-chipid"; 51 reg = <0x00000014 0x4>; 52 }; 53 54 serdes_ln_ctrl: mux-controller { 55 compatible = "mmio-mux"; 56 #mux-control-cells = <1>; 57 mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */ 58 }; 59 60 phy_gmii_sel: phy@4044 { 61 compatible = "ti,am654-phy-gmii-sel"; 62 reg = <0x4044 0x8>; 63 #phy-cells = <1>; 64 }; 65 66 epwm_tbclk: clock-controller@4140 { 67 compatible = "ti,am64-epwm-tbclk"; 68 reg = <0x4130 0x4>; 69 #clock-cells = <1>; 70 }; 71 }; 72 73 gic500: interrupt-controller@1800000 { 74 compatible = "arm,gic-v3"; 75 #address-cells = <2>; 76 #size-cells = <2>; 77 ranges; 78 #interrupt-cells = <3>; 79 interrupt-controller; 80 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 81 <0x00 0x01840000 0x00 0xC0000>, /* GICR */ 82 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 83 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 84 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 85 /* 86 * vcpumntirq: 87 * virtual CPU interface maintenance interrupt 88 */ 89 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 90 91 gic_its: msi-controller@1820000 { 92 compatible = "arm,gic-v3-its"; 93 reg = <0x00 0x01820000 0x00 0x10000>; 94 socionext,synquacer-pre-its = <0x1000000 0x400000>; 95 msi-controller; 96 #msi-cells = <1>; 97 }; 98 }; 99 100 dmss: bus@48000000 { 101 bootph-all; 102 compatible = "simple-bus"; 103 #address-cells = <2>; 104 #size-cells = <2>; 105 dma-ranges; 106 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; 107 108 ti,sci-dev-id = <25>; 109 110 secure_proxy_main: mailbox@4d000000 { 111 bootph-all; 112 compatible = "ti,am654-secure-proxy"; 113 #mbox-cells = <1>; 114 reg-names = "target_data", "rt", "scfg"; 115 reg = <0x00 0x4d000000 0x00 0x80000>, 116 <0x00 0x4a600000 0x00 0x80000>, 117 <0x00 0x4a400000 0x00 0x80000>; 118 interrupt-names = "rx_012"; 119 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 120 }; 121 122 inta_main_dmss: interrupt-controller@48000000 { 123 compatible = "ti,sci-inta"; 124 reg = <0x00 0x48000000 0x00 0x100000>; 125 #interrupt-cells = <0>; 126 interrupt-controller; 127 interrupt-parent = <&gic500>; 128 msi-controller; 129 ti,sci = <&dmsc>; 130 ti,sci-dev-id = <28>; 131 ti,interrupt-ranges = <4 68 36>; 132 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 133 }; 134 135 main_bcdma: dma-controller@485c0100 { 136 compatible = "ti,am64-dmss-bcdma"; 137 reg = <0x00 0x485c0100 0x00 0x100>, 138 <0x00 0x4c000000 0x00 0x20000>, 139 <0x00 0x4a820000 0x00 0x20000>, 140 <0x00 0x4aa40000 0x00 0x20000>, 141 <0x00 0x4bc00000 0x00 0x100000>; 142 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; 143 msi-parent = <&inta_main_dmss>; 144 #dma-cells = <3>; 145 146 ti,sci = <&dmsc>; 147 ti,sci-dev-id = <26>; 148 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 149 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 150 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 151 }; 152 153 main_pktdma: dma-controller@485c0000 { 154 compatible = "ti,am64-dmss-pktdma"; 155 reg = <0x00 0x485c0000 0x00 0x100>, 156 <0x00 0x4a800000 0x00 0x20000>, 157 <0x00 0x4aa00000 0x00 0x40000>, 158 <0x00 0x4b800000 0x00 0x400000>; 159 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 160 msi-parent = <&inta_main_dmss>; 161 #dma-cells = <2>; 162 163 ti,sci = <&dmsc>; 164 ti,sci-dev-id = <30>; 165 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 166 <0x24>, /* CPSW_TX_CHAN */ 167 <0x25>, /* SAUL_TX_0_CHAN */ 168 <0x26>, /* SAUL_TX_1_CHAN */ 169 <0x27>, /* ICSSG_0_TX_CHAN */ 170 <0x28>; /* ICSSG_1_TX_CHAN */ 171 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 172 <0x11>, /* RING_CPSW_TX_CHAN */ 173 <0x12>, /* RING_SAUL_TX_0_CHAN */ 174 <0x13>, /* RING_SAUL_TX_1_CHAN */ 175 <0x14>, /* RING_ICSSG_0_TX_CHAN */ 176 <0x15>; /* RING_ICSSG_1_TX_CHAN */ 177 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 178 <0x2b>, /* CPSW_RX_CHAN */ 179 <0x2d>, /* SAUL_RX_0_CHAN */ 180 <0x2f>, /* SAUL_RX_1_CHAN */ 181 <0x31>, /* SAUL_RX_2_CHAN */ 182 <0x33>, /* SAUL_RX_3_CHAN */ 183 <0x35>, /* ICSSG_0_RX_CHAN */ 184 <0x37>; /* ICSSG_1_RX_CHAN */ 185 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 186 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 187 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 188 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */ 189 <0x36>, /* FLOW_ICSSG_0_RX_CHAN */ 190 <0x38>; /* FLOW_ICSSG_1_RX_CHAN */ 191 }; 192 }; 193 194 dmsc: system-controller@44043000 { 195 bootph-all; 196 compatible = "ti,k2g-sci"; 197 ti,host-id = <12>; 198 mbox-names = "rx", "tx"; 199 mboxes = <&secure_proxy_main 12>, 200 <&secure_proxy_main 13>; 201 reg-names = "debug_messages"; 202 reg = <0x00 0x44043000 0x00 0xfe0>; 203 204 k3_pds: power-controller { 205 bootph-all; 206 compatible = "ti,sci-pm-domain"; 207 #power-domain-cells = <2>; 208 }; 209 210 k3_clks: clock-controller { 211 bootph-all; 212 compatible = "ti,k2g-sci-clk"; 213 #clock-cells = <2>; 214 }; 215 216 k3_reset: reset-controller { 217 bootph-all; 218 compatible = "ti,sci-reset"; 219 #reset-cells = <2>; 220 }; 221 }; 222 223 main_pmx0: pinctrl@f4000 { 224 bootph-all; 225 compatible = "pinctrl-single"; 226 reg = <0x00 0xf4000 0x00 0x2d0>; 227 #pinctrl-cells = <1>; 228 pinctrl-single,register-width = <32>; 229 pinctrl-single,function-mask = <0xffffffff>; 230 }; 231 232 main_timer0: timer@2400000 { 233 bootph-all; 234 compatible = "ti,am654-timer"; 235 reg = <0x00 0x2400000 0x00 0x400>; 236 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&k3_clks 36 1>; 238 clock-names = "fck"; 239 assigned-clocks = <&k3_clks 36 1>; 240 assigned-clock-parents = <&k3_clks 36 2>; 241 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 242 ti,timer-pwm; 243 }; 244 245 main_timer1: timer@2410000 { 246 compatible = "ti,am654-timer"; 247 reg = <0x00 0x2410000 0x00 0x400>; 248 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&k3_clks 37 1>; 250 clock-names = "fck"; 251 assigned-clocks = <&k3_clks 37 1>; 252 assigned-clock-parents = <&k3_clks 37 2>; 253 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 254 ti,timer-pwm; 255 }; 256 257 main_timer2: timer@2420000 { 258 compatible = "ti,am654-timer"; 259 reg = <0x00 0x2420000 0x00 0x400>; 260 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&k3_clks 38 1>; 262 clock-names = "fck"; 263 assigned-clocks = <&k3_clks 38 1>; 264 assigned-clock-parents = <&k3_clks 38 2>; 265 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 266 ti,timer-pwm; 267 }; 268 269 main_timer3: timer@2430000 { 270 compatible = "ti,am654-timer"; 271 reg = <0x00 0x2430000 0x00 0x400>; 272 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&k3_clks 39 1>; 274 clock-names = "fck"; 275 assigned-clocks = <&k3_clks 39 1>; 276 assigned-clock-parents = <&k3_clks 39 2>; 277 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 278 ti,timer-pwm; 279 }; 280 281 main_timer4: timer@2440000 { 282 compatible = "ti,am654-timer"; 283 reg = <0x00 0x2440000 0x00 0x400>; 284 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&k3_clks 40 1>; 286 clock-names = "fck"; 287 assigned-clocks = <&k3_clks 40 1>; 288 assigned-clock-parents = <&k3_clks 40 2>; 289 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 290 ti,timer-pwm; 291 }; 292 293 main_timer5: timer@2450000 { 294 compatible = "ti,am654-timer"; 295 reg = <0x00 0x2450000 0x00 0x400>; 296 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&k3_clks 41 1>; 298 clock-names = "fck"; 299 assigned-clocks = <&k3_clks 41 1>; 300 assigned-clock-parents = <&k3_clks 41 2>; 301 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 302 ti,timer-pwm; 303 }; 304 305 main_timer6: timer@2460000 { 306 compatible = "ti,am654-timer"; 307 reg = <0x00 0x2460000 0x00 0x400>; 308 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 309 clocks = <&k3_clks 42 1>; 310 clock-names = "fck"; 311 assigned-clocks = <&k3_clks 42 1>; 312 assigned-clock-parents = <&k3_clks 42 2>; 313 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 314 ti,timer-pwm; 315 }; 316 317 main_timer7: timer@2470000 { 318 compatible = "ti,am654-timer"; 319 reg = <0x00 0x2470000 0x00 0x400>; 320 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&k3_clks 43 1>; 322 clock-names = "fck"; 323 assigned-clocks = <&k3_clks 43 1>; 324 assigned-clock-parents = <&k3_clks 43 2>; 325 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 326 ti,timer-pwm; 327 }; 328 329 main_timer8: timer@2480000 { 330 compatible = "ti,am654-timer"; 331 reg = <0x00 0x2480000 0x00 0x400>; 332 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&k3_clks 44 1>; 334 clock-names = "fck"; 335 assigned-clocks = <&k3_clks 44 1>; 336 assigned-clock-parents = <&k3_clks 44 2>; 337 power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>; 338 ti,timer-pwm; 339 }; 340 341 main_timer9: timer@2490000 { 342 compatible = "ti,am654-timer"; 343 reg = <0x00 0x2490000 0x00 0x400>; 344 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&k3_clks 45 1>; 346 clock-names = "fck"; 347 assigned-clocks = <&k3_clks 45 1>; 348 assigned-clock-parents = <&k3_clks 45 2>; 349 power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>; 350 ti,timer-pwm; 351 }; 352 353 main_timer10: timer@24a0000 { 354 compatible = "ti,am654-timer"; 355 reg = <0x00 0x24a0000 0x00 0x400>; 356 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&k3_clks 46 1>; 358 clock-names = "fck"; 359 assigned-clocks = <&k3_clks 46 1>; 360 assigned-clock-parents = <&k3_clks 46 2>; 361 power-domains = <&k3_pds 46 TI_SCI_PD_EXCLUSIVE>; 362 ti,timer-pwm; 363 }; 364 365 main_timer11: timer@24b0000 { 366 compatible = "ti,am654-timer"; 367 reg = <0x00 0x24b0000 0x00 0x400>; 368 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&k3_clks 47 1>; 370 clock-names = "fck"; 371 assigned-clocks = <&k3_clks 47 1>; 372 assigned-clock-parents = <&k3_clks 47 2>; 373 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; 374 ti,timer-pwm; 375 }; 376 377 main_esm: esm@420000 { 378 bootph-pre-ram; 379 compatible = "ti,j721e-esm"; 380 reg = <0x00 0x420000 0x00 0x1000>; 381 ti,esm-pins = <160>, <161>; 382 }; 383 384 main_uart0: serial@2800000 { 385 compatible = "ti,am64-uart", "ti,am654-uart"; 386 reg = <0x00 0x02800000 0x00 0x100>; 387 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 388 clock-frequency = <48000000>; 389 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 390 clocks = <&k3_clks 146 0>; 391 clock-names = "fclk"; 392 status = "disabled"; 393 }; 394 395 main_uart1: serial@2810000 { 396 compatible = "ti,am64-uart", "ti,am654-uart"; 397 reg = <0x00 0x02810000 0x00 0x100>; 398 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 399 clock-frequency = <48000000>; 400 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 401 clocks = <&k3_clks 152 0>; 402 clock-names = "fclk"; 403 status = "disabled"; 404 }; 405 406 main_uart2: serial@2820000 { 407 compatible = "ti,am64-uart", "ti,am654-uart"; 408 reg = <0x00 0x02820000 0x00 0x100>; 409 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 410 clock-frequency = <48000000>; 411 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 412 clocks = <&k3_clks 153 0>; 413 clock-names = "fclk"; 414 status = "disabled"; 415 }; 416 417 main_uart3: serial@2830000 { 418 compatible = "ti,am64-uart", "ti,am654-uart"; 419 reg = <0x00 0x02830000 0x00 0x100>; 420 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 421 clock-frequency = <48000000>; 422 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 423 clocks = <&k3_clks 154 0>; 424 clock-names = "fclk"; 425 status = "disabled"; 426 }; 427 428 main_uart4: serial@2840000 { 429 compatible = "ti,am64-uart", "ti,am654-uart"; 430 reg = <0x00 0x02840000 0x00 0x100>; 431 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 432 clock-frequency = <48000000>; 433 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 434 clocks = <&k3_clks 155 0>; 435 clock-names = "fclk"; 436 status = "disabled"; 437 }; 438 439 main_uart5: serial@2850000 { 440 compatible = "ti,am64-uart", "ti,am654-uart"; 441 reg = <0x00 0x02850000 0x00 0x100>; 442 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 443 clock-frequency = <48000000>; 444 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 445 clocks = <&k3_clks 156 0>; 446 clock-names = "fclk"; 447 status = "disabled"; 448 }; 449 450 main_uart6: serial@2860000 { 451 compatible = "ti,am64-uart", "ti,am654-uart"; 452 reg = <0x00 0x02860000 0x00 0x100>; 453 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 454 clock-frequency = <48000000>; 455 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 456 clocks = <&k3_clks 158 0>; 457 clock-names = "fclk"; 458 status = "disabled"; 459 }; 460 461 main_i2c0: i2c@20000000 { 462 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 463 reg = <0x00 0x20000000 0x00 0x100>; 464 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 468 clocks = <&k3_clks 102 2>; 469 clock-names = "fck"; 470 status = "disabled"; 471 }; 472 473 main_i2c1: i2c@20010000 { 474 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 475 reg = <0x00 0x20010000 0x00 0x100>; 476 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 480 clocks = <&k3_clks 103 2>; 481 clock-names = "fck"; 482 status = "disabled"; 483 }; 484 485 main_i2c2: i2c@20020000 { 486 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 487 reg = <0x00 0x20020000 0x00 0x100>; 488 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 489 #address-cells = <1>; 490 #size-cells = <0>; 491 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 492 clocks = <&k3_clks 104 2>; 493 clock-names = "fck"; 494 status = "disabled"; 495 }; 496 497 main_i2c3: i2c@20030000 { 498 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 499 reg = <0x00 0x20030000 0x00 0x100>; 500 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 501 #address-cells = <1>; 502 #size-cells = <0>; 503 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 504 clocks = <&k3_clks 105 2>; 505 clock-names = "fck"; 506 status = "disabled"; 507 }; 508 509 main_spi0: spi@20100000 { 510 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 511 reg = <0x00 0x20100000 0x00 0x400>; 512 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 516 clocks = <&k3_clks 141 0>; 517 dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>; 518 dma-names = "tx0", "rx0"; 519 status = "disabled"; 520 }; 521 522 main_spi1: spi@20110000 { 523 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 524 reg = <0x00 0x20110000 0x00 0x400>; 525 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 526 #address-cells = <1>; 527 #size-cells = <0>; 528 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 529 clocks = <&k3_clks 142 0>; 530 status = "disabled"; 531 }; 532 533 main_spi2: spi@20120000 { 534 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 535 reg = <0x00 0x20120000 0x00 0x400>; 536 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 537 #address-cells = <1>; 538 #size-cells = <0>; 539 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 540 clocks = <&k3_clks 143 0>; 541 status = "disabled"; 542 }; 543 544 main_spi3: spi@20130000 { 545 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 546 reg = <0x00 0x20130000 0x00 0x400>; 547 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 548 #address-cells = <1>; 549 #size-cells = <0>; 550 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; 551 clocks = <&k3_clks 144 0>; 552 status = "disabled"; 553 }; 554 555 main_spi4: spi@20140000 { 556 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 557 reg = <0x00 0x20140000 0x00 0x400>; 558 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>; 562 clocks = <&k3_clks 145 0>; 563 status = "disabled"; 564 }; 565 566 main_gpio_intr: interrupt-controller@a00000 { 567 compatible = "ti,sci-intr"; 568 reg = <0x00 0x00a00000 0x00 0x800>; 569 ti,intr-trigger-type = <1>; 570 interrupt-controller; 571 interrupt-parent = <&gic500>; 572 #interrupt-cells = <1>; 573 ti,sci = <&dmsc>; 574 ti,sci-dev-id = <3>; 575 ti,interrupt-ranges = <0 32 16>; 576 }; 577 578 main_gpio0: gpio@600000 { 579 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 580 reg = <0x0 0x00600000 0x0 0x100>; 581 gpio-controller; 582 #gpio-cells = <2>; 583 interrupt-parent = <&main_gpio_intr>; 584 interrupts = <190>, <191>, <192>, 585 <193>, <194>, <195>; 586 interrupt-controller; 587 #interrupt-cells = <2>; 588 ti,ngpio = <87>; 589 ti,davinci-gpio-unbanked = <0>; 590 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 591 clocks = <&k3_clks 77 0>; 592 clock-names = "gpio"; 593 }; 594 595 main_gpio1: gpio@601000 { 596 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 597 reg = <0x0 0x00601000 0x0 0x100>; 598 gpio-controller; 599 #gpio-cells = <2>; 600 interrupt-parent = <&main_gpio_intr>; 601 interrupts = <180>, <181>, <182>, 602 <183>, <184>, <185>; 603 interrupt-controller; 604 #interrupt-cells = <2>; 605 ti,ngpio = <88>; 606 ti,davinci-gpio-unbanked = <0>; 607 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 608 clocks = <&k3_clks 78 0>; 609 clock-names = "gpio"; 610 }; 611 612 sdhci0: mmc@fa10000 { 613 compatible = "ti,am64-sdhci-8bit"; 614 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; 615 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 616 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 617 clocks = <&k3_clks 57 0>, <&k3_clks 57 1>; 618 clock-names = "clk_ahb", "clk_xin"; 619 mmc-ddr-1_8v; 620 mmc-hs200-1_8v; 621 ti,trm-icp = <0x2>; 622 ti,otap-del-sel-legacy = <0x0>; 623 ti,otap-del-sel-mmc-hs = <0x0>; 624 ti,otap-del-sel-ddr52 = <0x6>; 625 ti,otap-del-sel-hs200 = <0x7>; 626 }; 627 628 sdhci1: mmc@fa00000 { 629 compatible = "ti,am64-sdhci-4bit"; 630 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; 631 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 632 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 633 clocks = <&k3_clks 58 3>, <&k3_clks 58 4>; 634 clock-names = "clk_ahb", "clk_xin"; 635 ti,trm-icp = <0x2>; 636 ti,otap-del-sel-legacy = <0x0>; 637 ti,otap-del-sel-sd-hs = <0xf>; 638 ti,otap-del-sel-sdr12 = <0xf>; 639 ti,otap-del-sel-sdr25 = <0xf>; 640 ti,otap-del-sel-sdr50 = <0xc>; 641 ti,otap-del-sel-sdr104 = <0x6>; 642 ti,otap-del-sel-ddr50 = <0x9>; 643 ti,clkbuf-sel = <0x7>; 644 }; 645 646 cpsw3g: ethernet@8000000 { 647 compatible = "ti,am642-cpsw-nuss"; 648 #address-cells = <2>; 649 #size-cells = <2>; 650 reg = <0x0 0x8000000 0x0 0x200000>; 651 reg-names = "cpsw_nuss"; 652 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>; 653 clocks = <&k3_clks 13 0>; 654 assigned-clocks = <&k3_clks 13 1>; 655 assigned-clock-parents = <&k3_clks 13 9>; 656 clock-names = "fck"; 657 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 658 659 dmas = <&main_pktdma 0xC500 15>, 660 <&main_pktdma 0xC501 15>, 661 <&main_pktdma 0xC502 15>, 662 <&main_pktdma 0xC503 15>, 663 <&main_pktdma 0xC504 15>, 664 <&main_pktdma 0xC505 15>, 665 <&main_pktdma 0xC506 15>, 666 <&main_pktdma 0xC507 15>, 667 <&main_pktdma 0x4500 15>; 668 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 669 "tx7", "rx"; 670 671 ethernet-ports { 672 #address-cells = <1>; 673 #size-cells = <0>; 674 675 cpsw_port1: port@1 { 676 reg = <1>; 677 ti,mac-only; 678 label = "port1"; 679 phys = <&phy_gmii_sel 1>; 680 mac-address = [00 00 00 00 00 00]; 681 ti,syscon-efuse = <&main_conf 0x200>; 682 }; 683 684 cpsw_port2: port@2 { 685 reg = <2>; 686 ti,mac-only; 687 label = "port2"; 688 phys = <&phy_gmii_sel 2>; 689 mac-address = [00 00 00 00 00 00]; 690 }; 691 }; 692 693 cpsw3g_mdio: mdio@f00 { 694 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 695 reg = <0x0 0xf00 0x0 0x100>; 696 #address-cells = <1>; 697 #size-cells = <0>; 698 clocks = <&k3_clks 13 0>; 699 clock-names = "fck"; 700 bus_freq = <1000000>; 701 status = "disabled"; 702 }; 703 704 cpts@3d000 { 705 compatible = "ti,j721e-cpts"; 706 reg = <0x0 0x3d000 0x0 0x400>; 707 clocks = <&k3_clks 13 1>; 708 clock-names = "cpts"; 709 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 710 interrupt-names = "cpts"; 711 ti,cpts-ext-ts-inputs = <4>; 712 ti,cpts-periodic-outputs = <2>; 713 }; 714 }; 715 716 main_cpts0: cpts@39000000 { 717 compatible = "ti,j721e-cpts"; 718 reg = <0x0 0x39000000 0x0 0x400>; 719 reg-names = "cpts"; 720 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; 721 clocks = <&k3_clks 84 0>; 722 clock-names = "cpts"; 723 assigned-clocks = <&k3_clks 84 0>; 724 assigned-clock-parents = <&k3_clks 84 8>; 725 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 726 interrupt-names = "cpts"; 727 ti,cpts-periodic-outputs = <6>; 728 ti,cpts-ext-ts-inputs = <8>; 729 }; 730 731 timesync_router: pinctrl@a40000 { 732 compatible = "pinctrl-single"; 733 reg = <0x0 0xa40000 0x0 0x800>; 734 #pinctrl-cells = <1>; 735 pinctrl-single,register-width = <32>; 736 pinctrl-single,function-mask = <0x000107ff>; 737 }; 738 739 usbss0: cdns-usb@f900000 { 740 compatible = "ti,am64-usb"; 741 reg = <0x00 0xf900000 0x00 0x100>; 742 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 743 clocks = <&k3_clks 161 9>, <&k3_clks 161 1>; 744 clock-names = "ref", "lpm"; 745 assigned-clocks = <&k3_clks 161 9>; /* USB2_REFCLK */ 746 assigned-clock-parents = <&k3_clks 161 10>; /* HF0SC0 */ 747 #address-cells = <2>; 748 #size-cells = <2>; 749 ranges; 750 usb0: usb@f400000 { 751 compatible = "cdns,usb3"; 752 reg = <0x00 0xf400000 0x00 0x10000>, 753 <0x00 0xf410000 0x00 0x10000>, 754 <0x00 0xf420000 0x00 0x10000>; 755 reg-names = "otg", 756 "xhci", 757 "dev"; 758 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 759 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 760 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */ 761 interrupt-names = "host", 762 "peripheral", 763 "otg"; 764 maximum-speed = "super-speed"; 765 dr_mode = "otg"; 766 }; 767 }; 768 769 tscadc0: tscadc@28001000 { 770 compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; 771 reg = <0x00 0x28001000 0x00 0x1000>; 772 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 773 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 774 clocks = <&k3_clks 0 0>; 775 assigned-clocks = <&k3_clks 0 0>; 776 assigned-clock-parents = <&k3_clks 0 3>; 777 assigned-clock-rates = <60000000>; 778 clock-names = "fck"; 779 status = "disabled"; 780 781 adc { 782 #io-channel-cells = <1>; 783 compatible = "ti,am654-adc", "ti,am3359-adc"; 784 }; 785 }; 786 787 fss: bus@fc00000 { 788 compatible = "simple-bus"; 789 reg = <0x00 0x0fc00000 0x00 0x70000>; 790 #address-cells = <2>; 791 #size-cells = <2>; 792 ranges; 793 794 ospi0: spi@fc40000 { 795 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 796 reg = <0x00 0x0fc40000 0x00 0x100>, 797 <0x05 0x00000000 0x01 0x00000000>; 798 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 799 cdns,fifo-depth = <256>; 800 cdns,fifo-width = <4>; 801 cdns,trigger-address = <0x0>; 802 #address-cells = <0x1>; 803 #size-cells = <0x0>; 804 clocks = <&k3_clks 75 6>; 805 assigned-clocks = <&k3_clks 75 6>; 806 assigned-clock-parents = <&k3_clks 75 7>; 807 assigned-clock-rates = <166666666>; 808 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 809 status = "disabled"; 810 }; 811 }; 812 813 hwspinlock: spinlock@2a000000 { 814 compatible = "ti,am64-hwspinlock"; 815 reg = <0x00 0x2a000000 0x00 0x1000>; 816 #hwlock-cells = <1>; 817 }; 818 819 mailbox0_cluster2: mailbox@29020000 { 820 compatible = "ti,am64-mailbox"; 821 reg = <0x00 0x29020000 0x00 0x200>; 822 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 824 #mbox-cells = <1>; 825 ti,mbox-num-users = <4>; 826 ti,mbox-num-fifos = <16>; 827 status = "disabled"; 828 }; 829 830 mailbox0_cluster3: mailbox@29030000 { 831 compatible = "ti,am64-mailbox"; 832 reg = <0x00 0x29030000 0x00 0x200>; 833 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 835 #mbox-cells = <1>; 836 ti,mbox-num-users = <4>; 837 ti,mbox-num-fifos = <16>; 838 status = "disabled"; 839 }; 840 841 mailbox0_cluster4: mailbox@29040000 { 842 compatible = "ti,am64-mailbox"; 843 reg = <0x00 0x29040000 0x00 0x200>; 844 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 846 #mbox-cells = <1>; 847 ti,mbox-num-users = <4>; 848 ti,mbox-num-fifos = <16>; 849 status = "disabled"; 850 }; 851 852 mailbox0_cluster5: mailbox@29050000 { 853 compatible = "ti,am64-mailbox"; 854 reg = <0x00 0x29050000 0x00 0x200>; 855 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 857 #mbox-cells = <1>; 858 ti,mbox-num-users = <4>; 859 ti,mbox-num-fifos = <16>; 860 status = "disabled"; 861 }; 862 863 mailbox0_cluster6: mailbox@29060000 { 864 compatible = "ti,am64-mailbox"; 865 reg = <0x00 0x29060000 0x00 0x200>; 866 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 867 #mbox-cells = <1>; 868 ti,mbox-num-users = <4>; 869 ti,mbox-num-fifos = <16>; 870 status = "disabled"; 871 }; 872 873 mailbox0_cluster7: mailbox@29070000 { 874 compatible = "ti,am64-mailbox"; 875 reg = <0x00 0x29070000 0x00 0x200>; 876 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 877 #mbox-cells = <1>; 878 ti,mbox-num-users = <4>; 879 ti,mbox-num-fifos = <16>; 880 status = "disabled"; 881 }; 882 883 main_r5fss0: r5fss@78000000 { 884 compatible = "ti,am64-r5fss"; 885 ti,cluster-mode = <0>; 886 #address-cells = <1>; 887 #size-cells = <1>; 888 ranges = <0x78000000 0x00 0x78000000 0x10000>, 889 <0x78100000 0x00 0x78100000 0x10000>, 890 <0x78200000 0x00 0x78200000 0x08000>, 891 <0x78300000 0x00 0x78300000 0x08000>; 892 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; 893 894 main_r5fss0_core0: r5f@78000000 { 895 compatible = "ti,am64-r5f"; 896 reg = <0x78000000 0x00010000>, 897 <0x78100000 0x00010000>; 898 reg-names = "atcm", "btcm"; 899 ti,sci = <&dmsc>; 900 ti,sci-dev-id = <121>; 901 ti,sci-proc-ids = <0x01 0xff>; 902 resets = <&k3_reset 121 1>; 903 firmware-name = "am64-main-r5f0_0-fw"; 904 ti,atcm-enable = <1>; 905 ti,btcm-enable = <1>; 906 ti,loczrama = <1>; 907 }; 908 909 main_r5fss0_core1: r5f@78200000 { 910 compatible = "ti,am64-r5f"; 911 reg = <0x78200000 0x00008000>, 912 <0x78300000 0x00008000>; 913 reg-names = "atcm", "btcm"; 914 ti,sci = <&dmsc>; 915 ti,sci-dev-id = <122>; 916 ti,sci-proc-ids = <0x02 0xff>; 917 resets = <&k3_reset 122 1>; 918 firmware-name = "am64-main-r5f0_1-fw"; 919 ti,atcm-enable = <1>; 920 ti,btcm-enable = <1>; 921 ti,loczrama = <1>; 922 }; 923 }; 924 925 main_r5fss1: r5fss@78400000 { 926 compatible = "ti,am64-r5fss"; 927 ti,cluster-mode = <0>; 928 #address-cells = <1>; 929 #size-cells = <1>; 930 ranges = <0x78400000 0x00 0x78400000 0x10000>, 931 <0x78500000 0x00 0x78500000 0x10000>, 932 <0x78600000 0x00 0x78600000 0x08000>, 933 <0x78700000 0x00 0x78700000 0x08000>; 934 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 935 936 main_r5fss1_core0: r5f@78400000 { 937 compatible = "ti,am64-r5f"; 938 reg = <0x78400000 0x00010000>, 939 <0x78500000 0x00010000>; 940 reg-names = "atcm", "btcm"; 941 ti,sci = <&dmsc>; 942 ti,sci-dev-id = <123>; 943 ti,sci-proc-ids = <0x06 0xff>; 944 resets = <&k3_reset 123 1>; 945 firmware-name = "am64-main-r5f1_0-fw"; 946 ti,atcm-enable = <1>; 947 ti,btcm-enable = <1>; 948 ti,loczrama = <1>; 949 }; 950 951 main_r5fss1_core1: r5f@78600000 { 952 compatible = "ti,am64-r5f"; 953 reg = <0x78600000 0x00008000>, 954 <0x78700000 0x00008000>; 955 reg-names = "atcm", "btcm"; 956 ti,sci = <&dmsc>; 957 ti,sci-dev-id = <124>; 958 ti,sci-proc-ids = <0x07 0xff>; 959 resets = <&k3_reset 124 1>; 960 firmware-name = "am64-main-r5f1_1-fw"; 961 ti,atcm-enable = <1>; 962 ti,btcm-enable = <1>; 963 ti,loczrama = <1>; 964 }; 965 }; 966 967 serdes_wiz0: wiz@f000000 { 968 compatible = "ti,am64-wiz-10g"; 969 #address-cells = <1>; 970 #size-cells = <1>; 971 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 972 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>; 973 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 974 num-lanes = <1>; 975 #reset-cells = <1>; 976 #clock-cells = <1>; 977 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; 978 979 assigned-clocks = <&k3_clks 162 1>; 980 assigned-clock-parents = <&k3_clks 162 5>; 981 982 serdes0: serdes@f000000 { 983 compatible = "ti,j721e-serdes-10g"; 984 reg = <0x0f000000 0x00010000>; 985 reg-names = "torrent_phy"; 986 resets = <&serdes_wiz0 0>; 987 reset-names = "torrent_reset"; 988 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 989 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; 990 clock-names = "refclk", "phy_en_refclk"; 991 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 992 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, 993 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; 994 assigned-clock-parents = <&k3_clks 162 1>, 995 <&k3_clks 162 1>, 996 <&k3_clks 162 1>; 997 #address-cells = <1>; 998 #size-cells = <0>; 999 #clock-cells = <1>; 1000 }; 1001 }; 1002 1003 pcie0_rc: pcie@f102000 { 1004 compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host"; 1005 reg = <0x00 0x0f102000 0x00 0x1000>, 1006 <0x00 0x0f100000 0x00 0x400>, 1007 <0x00 0x0d000000 0x00 0x00800000>, 1008 <0x00 0x68000000 0x00 0x00001000>; 1009 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1010 interrupt-names = "link_state"; 1011 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 1012 device_type = "pci"; 1013 ti,syscon-pcie-ctrl = <&main_conf 0x4070>; 1014 max-link-speed = <2>; 1015 num-lanes = <1>; 1016 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 1017 clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; 1018 clock-names = "fck", "pcie_refclk"; 1019 #address-cells = <3>; 1020 #size-cells = <2>; 1021 bus-range = <0x0 0xff>; 1022 cdns,no-bar-match-nbits = <64>; 1023 vendor-id = <0x104c>; 1024 device-id = <0xb010>; 1025 msi-map = <0x0 &gic_its 0x0 0x10000>; 1026 ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, 1027 <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; 1028 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>; 1029 status = "disabled"; 1030 }; 1031 1032 pcie0_ep: pcie-ep@f102000 { 1033 compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep"; 1034 reg = <0x00 0x0f102000 0x00 0x1000>, 1035 <0x00 0x0f100000 0x00 0x400>, 1036 <0x00 0x0d000000 0x00 0x00800000>, 1037 <0x00 0x68000000 0x00 0x08000000>; 1038 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 1039 interrupt-names = "link_state"; 1040 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 1041 ti,syscon-pcie-ctrl = <&main_conf 0x4070>; 1042 max-link-speed = <2>; 1043 num-lanes = <1>; 1044 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 1045 clocks = <&k3_clks 114 0>; 1046 clock-names = "fck"; 1047 max-functions = /bits/ 8 <1>; 1048 status = "disabled"; 1049 }; 1050 1051 epwm0: pwm@23000000 { 1052 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1053 #pwm-cells = <3>; 1054 reg = <0x0 0x23000000 0x0 0x100>; 1055 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 1056 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 1057 clock-names = "tbclk", "fck"; 1058 status = "disabled"; 1059 }; 1060 1061 epwm1: pwm@23010000 { 1062 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1063 #pwm-cells = <3>; 1064 reg = <0x0 0x23010000 0x0 0x100>; 1065 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 1066 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 1067 clock-names = "tbclk", "fck"; 1068 status = "disabled"; 1069 }; 1070 1071 epwm2: pwm@23020000 { 1072 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1073 #pwm-cells = <3>; 1074 reg = <0x0 0x23020000 0x0 0x100>; 1075 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 1076 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 1077 clock-names = "tbclk", "fck"; 1078 status = "disabled"; 1079 }; 1080 1081 epwm3: pwm@23030000 { 1082 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1083 #pwm-cells = <3>; 1084 reg = <0x0 0x23030000 0x0 0x100>; 1085 power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; 1086 clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>; 1087 clock-names = "tbclk", "fck"; 1088 status = "disabled"; 1089 }; 1090 1091 epwm4: pwm@23040000 { 1092 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1093 #pwm-cells = <3>; 1094 reg = <0x0 0x23040000 0x0 0x100>; 1095 power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; 1096 clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>; 1097 clock-names = "tbclk", "fck"; 1098 status = "disabled"; 1099 }; 1100 1101 epwm5: pwm@23050000 { 1102 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1103 #pwm-cells = <3>; 1104 reg = <0x0 0x23050000 0x0 0x100>; 1105 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 1106 clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>; 1107 clock-names = "tbclk", "fck"; 1108 status = "disabled"; 1109 }; 1110 1111 epwm6: pwm@23060000 { 1112 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1113 #pwm-cells = <3>; 1114 reg = <0x0 0x23060000 0x0 0x100>; 1115 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 1116 clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>; 1117 clock-names = "tbclk", "fck"; 1118 status = "disabled"; 1119 }; 1120 1121 epwm7: pwm@23070000 { 1122 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1123 #pwm-cells = <3>; 1124 reg = <0x0 0x23070000 0x0 0x100>; 1125 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 1126 clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>; 1127 clock-names = "tbclk", "fck"; 1128 status = "disabled"; 1129 }; 1130 1131 epwm8: pwm@23080000 { 1132 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1133 #pwm-cells = <3>; 1134 reg = <0x0 0x23080000 0x0 0x100>; 1135 power-domains = <&k3_pds 94 TI_SCI_PD_EXCLUSIVE>; 1136 clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>; 1137 clock-names = "tbclk", "fck"; 1138 status = "disabled"; 1139 }; 1140 1141 ecap0: pwm@23100000 { 1142 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 1143 #pwm-cells = <3>; 1144 reg = <0x0 0x23100000 0x0 0x60>; 1145 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 1146 clocks = <&k3_clks 51 0>; 1147 clock-names = "fck"; 1148 status = "disabled"; 1149 }; 1150 1151 ecap1: pwm@23110000 { 1152 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 1153 #pwm-cells = <3>; 1154 reg = <0x0 0x23110000 0x0 0x60>; 1155 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 1156 clocks = <&k3_clks 52 0>; 1157 clock-names = "fck"; 1158 status = "disabled"; 1159 }; 1160 1161 ecap2: pwm@23120000 { 1162 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 1163 #pwm-cells = <3>; 1164 reg = <0x0 0x23120000 0x0 0x60>; 1165 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 1166 clocks = <&k3_clks 53 0>; 1167 clock-names = "fck"; 1168 status = "disabled"; 1169 }; 1170 1171 main_rti0: watchdog@e000000 { 1172 compatible = "ti,j7-rti-wdt"; 1173 reg = <0x00 0xe000000 0x00 0x100>; 1174 clocks = <&k3_clks 125 0>; 1175 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 1176 assigned-clocks = <&k3_clks 125 0>; 1177 assigned-clock-parents = <&k3_clks 125 2>; 1178 }; 1179 1180 main_rti1: watchdog@e010000 { 1181 compatible = "ti,j7-rti-wdt"; 1182 reg = <0x00 0xe010000 0x00 0x100>; 1183 clocks = <&k3_clks 126 0>; 1184 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; 1185 assigned-clocks = <&k3_clks 126 0>; 1186 assigned-clock-parents = <&k3_clks 126 2>; 1187 }; 1188 1189 icssg0: icssg@30000000 { 1190 compatible = "ti,am642-icssg"; 1191 reg = <0x00 0x30000000 0x00 0x80000>; 1192 power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; 1193 #address-cells = <1>; 1194 #size-cells = <1>; 1195 ranges = <0x0 0x00 0x30000000 0x80000>; 1196 1197 icssg0_mem: memories@0 { 1198 reg = <0x0 0x2000>, 1199 <0x2000 0x2000>, 1200 <0x10000 0x10000>; 1201 reg-names = "dram0", "dram1", "shrdram2"; 1202 }; 1203 1204 icssg0_cfg: cfg@26000 { 1205 compatible = "ti,pruss-cfg", "syscon"; 1206 reg = <0x26000 0x200>; 1207 #address-cells = <1>; 1208 #size-cells = <1>; 1209 ranges = <0x0 0x26000 0x2000>; 1210 1211 clocks { 1212 #address-cells = <1>; 1213 #size-cells = <0>; 1214 1215 icssg0_coreclk_mux: coreclk-mux@3c { 1216 reg = <0x3c>; 1217 #clock-cells = <0>; 1218 clocks = <&k3_clks 81 0>, /* icssg0_core_clk */ 1219 <&k3_clks 81 20>; /* icssg0_iclk */ 1220 assigned-clocks = <&icssg0_coreclk_mux>; 1221 assigned-clock-parents = <&k3_clks 81 20>; 1222 }; 1223 1224 icssg0_iepclk_mux: iepclk-mux@30 { 1225 reg = <0x30>; 1226 #clock-cells = <0>; 1227 clocks = <&k3_clks 81 3>, /* icssg0_iep_clk */ 1228 <&icssg0_coreclk_mux>; /* icssg0_coreclk_mux */ 1229 assigned-clocks = <&icssg0_iepclk_mux>; 1230 assigned-clock-parents = <&icssg0_coreclk_mux>; 1231 }; 1232 }; 1233 }; 1234 1235 icssg0_mii_rt: mii-rt@32000 { 1236 compatible = "ti,pruss-mii", "syscon"; 1237 reg = <0x32000 0x100>; 1238 }; 1239 1240 icssg0_mii_g_rt: mii-g-rt@33000 { 1241 compatible = "ti,pruss-mii-g", "syscon"; 1242 reg = <0x33000 0x1000>; 1243 }; 1244 1245 icssg0_intc: interrupt-controller@20000 { 1246 compatible = "ti,icssg-intc"; 1247 reg = <0x20000 0x2000>; 1248 interrupt-controller; 1249 #interrupt-cells = <3>; 1250 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1255 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1256 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1257 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1258 interrupt-names = "host_intr0", "host_intr1", 1259 "host_intr2", "host_intr3", 1260 "host_intr4", "host_intr5", 1261 "host_intr6", "host_intr7"; 1262 }; 1263 1264 pru0_0: pru@34000 { 1265 compatible = "ti,am642-pru"; 1266 reg = <0x34000 0x3000>, 1267 <0x22000 0x100>, 1268 <0x22400 0x100>; 1269 reg-names = "iram", "control", "debug"; 1270 firmware-name = "am64x-pru0_0-fw"; 1271 }; 1272 1273 rtu0_0: rtu@4000 { 1274 compatible = "ti,am642-rtu"; 1275 reg = <0x4000 0x2000>, 1276 <0x23000 0x100>, 1277 <0x23400 0x100>; 1278 reg-names = "iram", "control", "debug"; 1279 firmware-name = "am64x-rtu0_0-fw"; 1280 }; 1281 1282 tx_pru0_0: txpru@a000 { 1283 compatible = "ti,am642-tx-pru"; 1284 reg = <0xa000 0x1800>, 1285 <0x25000 0x100>, 1286 <0x25400 0x100>; 1287 reg-names = "iram", "control", "debug"; 1288 firmware-name = "am64x-txpru0_0-fw"; 1289 }; 1290 1291 pru0_1: pru@38000 { 1292 compatible = "ti,am642-pru"; 1293 reg = <0x38000 0x3000>, 1294 <0x24000 0x100>, 1295 <0x24400 0x100>; 1296 reg-names = "iram", "control", "debug"; 1297 firmware-name = "am64x-pru0_1-fw"; 1298 }; 1299 1300 rtu0_1: rtu@6000 { 1301 compatible = "ti,am642-rtu"; 1302 reg = <0x6000 0x2000>, 1303 <0x23800 0x100>, 1304 <0x23c00 0x100>; 1305 reg-names = "iram", "control", "debug"; 1306 firmware-name = "am64x-rtu0_1-fw"; 1307 }; 1308 1309 tx_pru0_1: txpru@c000 { 1310 compatible = "ti,am642-tx-pru"; 1311 reg = <0xc000 0x1800>, 1312 <0x25800 0x100>, 1313 <0x25c00 0x100>; 1314 reg-names = "iram", "control", "debug"; 1315 firmware-name = "am64x-txpru0_1-fw"; 1316 }; 1317 1318 icssg0_mdio: mdio@32400 { 1319 compatible = "ti,davinci_mdio"; 1320 reg = <0x32400 0x100>; 1321 clocks = <&k3_clks 62 3>; 1322 clock-names = "fck"; 1323 #address-cells = <1>; 1324 #size-cells = <0>; 1325 bus_freq = <1000000>; 1326 status = "disabled"; 1327 }; 1328 }; 1329 1330 icssg1: icssg@30080000 { 1331 compatible = "ti,am642-icssg"; 1332 reg = <0x00 0x30080000 0x00 0x80000>; 1333 power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>; 1334 #address-cells = <1>; 1335 #size-cells = <1>; 1336 ranges = <0x0 0x00 0x30080000 0x80000>; 1337 1338 icssg1_mem: memories@0 { 1339 reg = <0x0 0x2000>, 1340 <0x2000 0x2000>, 1341 <0x10000 0x10000>; 1342 reg-names = "dram0", "dram1", "shrdram2"; 1343 }; 1344 1345 icssg1_cfg: cfg@26000 { 1346 compatible = "ti,pruss-cfg", "syscon"; 1347 reg = <0x26000 0x200>; 1348 #address-cells = <1>; 1349 #size-cells = <1>; 1350 ranges = <0x0 0x26000 0x2000>; 1351 1352 clocks { 1353 #address-cells = <1>; 1354 #size-cells = <0>; 1355 1356 icssg1_coreclk_mux: coreclk-mux@3c { 1357 reg = <0x3c>; 1358 #clock-cells = <0>; 1359 clocks = <&k3_clks 82 0>, /* icssg1_core_clk */ 1360 <&k3_clks 82 20>; /* icssg1_iclk */ 1361 assigned-clocks = <&icssg1_coreclk_mux>; 1362 assigned-clock-parents = <&k3_clks 82 20>; 1363 }; 1364 1365 icssg1_iepclk_mux: iepclk-mux@30 { 1366 reg = <0x30>; 1367 #clock-cells = <0>; 1368 clocks = <&k3_clks 82 3>, /* icssg1_iep_clk */ 1369 <&icssg1_coreclk_mux>; /* icssg1_coreclk_mux */ 1370 assigned-clocks = <&icssg1_iepclk_mux>; 1371 assigned-clock-parents = <&icssg1_coreclk_mux>; 1372 }; 1373 }; 1374 }; 1375 1376 icssg1_mii_rt: mii-rt@32000 { 1377 compatible = "ti,pruss-mii", "syscon"; 1378 reg = <0x32000 0x100>; 1379 }; 1380 1381 icssg1_mii_g_rt: mii-g-rt@33000 { 1382 compatible = "ti,pruss-mii-g", "syscon"; 1383 reg = <0x33000 0x1000>; 1384 }; 1385 1386 icssg1_intc: interrupt-controller@20000 { 1387 compatible = "ti,icssg-intc"; 1388 reg = <0x20000 0x2000>; 1389 interrupt-controller; 1390 #interrupt-cells = <3>; 1391 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1392 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1393 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1394 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1395 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1396 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 1397 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 1398 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1399 interrupt-names = "host_intr0", "host_intr1", 1400 "host_intr2", "host_intr3", 1401 "host_intr4", "host_intr5", 1402 "host_intr6", "host_intr7"; 1403 }; 1404 1405 pru1_0: pru@34000 { 1406 compatible = "ti,am642-pru"; 1407 reg = <0x34000 0x4000>, 1408 <0x22000 0x100>, 1409 <0x22400 0x100>; 1410 reg-names = "iram", "control", "debug"; 1411 firmware-name = "am64x-pru1_0-fw"; 1412 }; 1413 1414 rtu1_0: rtu@4000 { 1415 compatible = "ti,am642-rtu"; 1416 reg = <0x4000 0x2000>, 1417 <0x23000 0x100>, 1418 <0x23400 0x100>; 1419 reg-names = "iram", "control", "debug"; 1420 firmware-name = "am64x-rtu1_0-fw"; 1421 }; 1422 1423 tx_pru1_0: txpru@a000 { 1424 compatible = "ti,am642-tx-pru"; 1425 reg = <0xa000 0x1800>, 1426 <0x25000 0x100>, 1427 <0x25400 0x100>; 1428 reg-names = "iram", "control", "debug"; 1429 firmware-name = "am64x-txpru1_0-fw"; 1430 }; 1431 1432 pru1_1: pru@38000 { 1433 compatible = "ti,am642-pru"; 1434 reg = <0x38000 0x4000>, 1435 <0x24000 0x100>, 1436 <0x24400 0x100>; 1437 reg-names = "iram", "control", "debug"; 1438 firmware-name = "am64x-pru1_1-fw"; 1439 }; 1440 1441 rtu1_1: rtu@6000 { 1442 compatible = "ti,am642-rtu"; 1443 reg = <0x6000 0x2000>, 1444 <0x23800 0x100>, 1445 <0x23c00 0x100>; 1446 reg-names = "iram", "control", "debug"; 1447 firmware-name = "am64x-rtu1_1-fw"; 1448 }; 1449 1450 tx_pru1_1: txpru@c000 { 1451 compatible = "ti,am642-tx-pru"; 1452 reg = <0xc000 0x1800>, 1453 <0x25800 0x100>, 1454 <0x25c00 0x100>; 1455 reg-names = "iram", "control", "debug"; 1456 firmware-name = "am64x-txpru1_1-fw"; 1457 }; 1458 1459 icssg1_mdio: mdio@32400 { 1460 compatible = "ti,davinci_mdio"; 1461 reg = <0x32400 0x100>; 1462 #address-cells = <1>; 1463 #size-cells = <0>; 1464 clocks = <&k3_clks 82 0>; 1465 clock-names = "fck"; 1466 bus_freq = <1000000>; 1467 status = "disabled"; 1468 }; 1469 }; 1470 1471 main_mcan0: can@20701000 { 1472 compatible = "bosch,m_can"; 1473 reg = <0x00 0x20701000 0x00 0x200>, 1474 <0x00 0x20708000 0x00 0x8000>; 1475 reg-names = "m_can", "message_ram"; 1476 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 1477 clocks = <&k3_clks 98 5>, <&k3_clks 98 0>; 1478 clock-names = "hclk", "cclk"; 1479 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1481 interrupt-names = "int0", "int1"; 1482 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1483 status = "disabled"; 1484 }; 1485 1486 main_mcan1: can@20711000 { 1487 compatible = "bosch,m_can"; 1488 reg = <0x00 0x20711000 0x00 0x200>, 1489 <0x00 0x20718000 0x00 0x8000>; 1490 reg-names = "m_can", "message_ram"; 1491 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 1492 clocks = <&k3_clks 99 5>, <&k3_clks 99 0>; 1493 clock-names = "hclk", "cclk"; 1494 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1496 interrupt-names = "int0", "int1"; 1497 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1498 status = "disabled"; 1499 }; 1500 1501 crypto: crypto@40900000 { 1502 compatible = "ti,am64-sa2ul"; 1503 reg = <0x00 0x40900000 0x00 0x1200>; 1504 power-domains = <&k3_pds 133 TI_SCI_PD_SHARED>; 1505 #address-cells = <2>; 1506 #size-cells = <2>; 1507 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; 1508 dmas = <&main_pktdma 0xc001 0>, <&main_pktdma 0x4002 0>, 1509 <&main_pktdma 0x4003 0>; 1510 dma-names = "tx", "rx1", "rx2"; 1511 1512 rng: rng@40910000 { 1513 compatible = "inside-secure,safexcel-eip76"; 1514 reg = <0x00 0x40910000 0x00 0x7d>; 1515 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1516 status = "disabled"; /* Used by OP-TEE */ 1517 }; 1518 }; 1519 1520 gpmc0: memory-controller@3b000000 { 1521 compatible = "ti,am64-gpmc"; 1522 power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; 1523 clocks = <&k3_clks 80 0>; 1524 clock-names = "fck"; 1525 reg = <0x00 0x3b000000 0x00 0x400>, 1526 <0x00 0x50000000 0x00 0x8000000>; 1527 reg-names = "cfg", "data"; 1528 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1529 gpmc,num-cs = <3>; 1530 gpmc,num-waitpins = <2>; 1531 #address-cells = <2>; 1532 #size-cells = <1>; 1533 interrupt-controller; 1534 #interrupt-cells = <2>; 1535 gpio-controller; 1536 #gpio-cells = <2>; 1537 status = "disabled"; 1538 }; 1539 1540 elm0: ecc@25010000 { 1541 compatible = "ti,am64-elm"; 1542 reg = <0x00 0x25010000 0x00 0x2000>; 1543 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 1544 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; 1545 clocks = <&k3_clks 54 0>; 1546 clock-names = "fck"; 1547 status = "disabled"; 1548 }; 1549 1550 main_vtm0: temperature-sensor@b00000 { 1551 compatible = "ti,j7200-vtm"; 1552 reg = <0x00 0xb00000 0x00 0x400>, 1553 <0x00 0xb01000 0x00 0x400>; 1554 power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>; 1555 #thermal-sensor-cells = <1>; 1556 }; 1557}; 1558