1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for AM642 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/phy/phy-cadence.h> 9#include <dt-bindings/phy/phy-ti.h> 10 11/ { 12 serdes_refclk: clock-cmnrefclk { 13 #clock-cells = <0>; 14 compatible = "fixed-clock"; 15 clock-frequency = <0>; 16 }; 17}; 18 19&cbass_main { 20 oc_sram: sram@70000000 { 21 compatible = "mmio-sram"; 22 reg = <0x00 0x70000000 0x00 0x200000>; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 ranges = <0x0 0x00 0x70000000 0x200000>; 26 27 tfa-sram@1c0000 { 28 reg = <0x1c0000 0x20000>; 29 }; 30 31 dmsc-sram@1e0000 { 32 reg = <0x1e0000 0x1c000>; 33 }; 34 35 sproxy-sram@1fc000 { 36 reg = <0x1fc000 0x4000>; 37 }; 38 }; 39 40 main_conf: syscon@43000000 { 41 bootph-all; 42 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 43 reg = <0x0 0x43000000 0x0 0x20000>; 44 #address-cells = <1>; 45 #size-cells = <1>; 46 ranges = <0x0 0x0 0x43000000 0x20000>; 47 48 chipid@14 { 49 bootph-all; 50 compatible = "ti,am654-chipid"; 51 reg = <0x00000014 0x4>; 52 }; 53 54 serdes_ln_ctrl: mux-controller@4080 { 55 compatible = "reg-mux"; 56 reg = <0x4080 0x4>; 57 #mux-control-cells = <1>; 58 mux-reg-masks = <0x0 0x3>; /* SERDES0 lane0 select */ 59 }; 60 61 phy_gmii_sel: phy@4044 { 62 compatible = "ti,am654-phy-gmii-sel"; 63 reg = <0x4044 0x8>; 64 #phy-cells = <1>; 65 }; 66 67 epwm_tbclk: clock-controller@4130 { 68 compatible = "ti,am64-epwm-tbclk"; 69 reg = <0x4130 0x4>; 70 #clock-cells = <1>; 71 }; 72 }; 73 74 gic500: interrupt-controller@1800000 { 75 compatible = "arm,gic-v3"; 76 #address-cells = <2>; 77 #size-cells = <2>; 78 ranges; 79 #interrupt-cells = <3>; 80 interrupt-controller; 81 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 82 <0x00 0x01840000 0x00 0xC0000>, /* GICR */ 83 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 84 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 85 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 86 /* 87 * vcpumntirq: 88 * virtual CPU interface maintenance interrupt 89 */ 90 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 91 92 gic_its: msi-controller@1820000 { 93 compatible = "arm,gic-v3-its"; 94 reg = <0x00 0x01820000 0x00 0x10000>; 95 socionext,synquacer-pre-its = <0x1000000 0x400000>; 96 msi-controller; 97 #msi-cells = <1>; 98 }; 99 }; 100 101 dmss: bus@48000000 { 102 bootph-all; 103 compatible = "simple-bus"; 104 #address-cells = <2>; 105 #size-cells = <2>; 106 dma-ranges; 107 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; 108 109 ti,sci-dev-id = <25>; 110 111 secure_proxy_main: mailbox@4d000000 { 112 bootph-all; 113 compatible = "ti,am654-secure-proxy"; 114 #mbox-cells = <1>; 115 reg-names = "target_data", "rt", "scfg"; 116 reg = <0x00 0x4d000000 0x00 0x80000>, 117 <0x00 0x4a600000 0x00 0x80000>, 118 <0x00 0x4a400000 0x00 0x80000>; 119 interrupt-names = "rx_012"; 120 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 121 }; 122 123 inta_main_dmss: interrupt-controller@48000000 { 124 compatible = "ti,sci-inta"; 125 reg = <0x00 0x48000000 0x00 0x100000>; 126 #interrupt-cells = <0>; 127 interrupt-controller; 128 interrupt-parent = <&gic500>; 129 msi-controller; 130 ti,sci = <&dmsc>; 131 ti,sci-dev-id = <28>; 132 ti,interrupt-ranges = <4 68 36>; 133 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 134 }; 135 136 main_bcdma: dma-controller@485c0100 { 137 compatible = "ti,am64-dmss-bcdma"; 138 reg = <0x00 0x485c0100 0x00 0x100>, 139 <0x00 0x4c000000 0x00 0x20000>, 140 <0x00 0x4a820000 0x00 0x20000>, 141 <0x00 0x4aa40000 0x00 0x20000>, 142 <0x00 0x4bc00000 0x00 0x100000>, 143 <0x00 0x48600000 0x00 0x8000>, 144 <0x00 0x484a4000 0x00 0x2000>, 145 <0x00 0x484c2000 0x00 0x2000>, 146 <0x00 0x48420000 0x00 0x2000>; 147 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt", 148 "ring", "tchan", "rchan", "bchan"; 149 msi-parent = <&inta_main_dmss>; 150 #dma-cells = <3>; 151 152 ti,sci = <&dmsc>; 153 ti,sci-dev-id = <26>; 154 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 155 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 156 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 157 }; 158 159 main_pktdma: dma-controller@485c0000 { 160 compatible = "ti,am64-dmss-pktdma"; 161 reg = <0x00 0x485c0000 0x00 0x100>, 162 <0x00 0x4a800000 0x00 0x20000>, 163 <0x00 0x4aa00000 0x00 0x40000>, 164 <0x00 0x4b800000 0x00 0x400000>, 165 <0x00 0x485e0000 0x00 0x20000>, 166 <0x00 0x484a0000 0x00 0x4000>, 167 <0x00 0x484c0000 0x00 0x2000>, 168 <0x00 0x48430000 0x00 0x4000>; 169 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", 170 "ring", "tchan", "rchan", "rflow"; 171 msi-parent = <&inta_main_dmss>; 172 #dma-cells = <2>; 173 174 ti,sci = <&dmsc>; 175 ti,sci-dev-id = <30>; 176 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 177 <0x24>, /* CPSW_TX_CHAN */ 178 <0x25>, /* SAUL_TX_0_CHAN */ 179 <0x26>, /* SAUL_TX_1_CHAN */ 180 <0x27>, /* ICSSG_0_TX_CHAN */ 181 <0x28>; /* ICSSG_1_TX_CHAN */ 182 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 183 <0x11>, /* RING_CPSW_TX_CHAN */ 184 <0x12>, /* RING_SAUL_TX_0_CHAN */ 185 <0x13>, /* RING_SAUL_TX_1_CHAN */ 186 <0x14>, /* RING_ICSSG_0_TX_CHAN */ 187 <0x15>; /* RING_ICSSG_1_TX_CHAN */ 188 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 189 <0x2b>, /* CPSW_RX_CHAN */ 190 <0x2d>, /* SAUL_RX_0_CHAN */ 191 <0x2f>, /* SAUL_RX_1_CHAN */ 192 <0x31>, /* SAUL_RX_2_CHAN */ 193 <0x33>, /* SAUL_RX_3_CHAN */ 194 <0x35>, /* ICSSG_0_RX_CHAN */ 195 <0x37>; /* ICSSG_1_RX_CHAN */ 196 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 197 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 198 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 199 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */ 200 <0x36>, /* FLOW_ICSSG_0_RX_CHAN */ 201 <0x38>; /* FLOW_ICSSG_1_RX_CHAN */ 202 }; 203 }; 204 205 dmsc: system-controller@44043000 { 206 bootph-all; 207 compatible = "ti,k2g-sci"; 208 ti,host-id = <12>; 209 mbox-names = "rx", "tx"; 210 mboxes = <&secure_proxy_main 12>, 211 <&secure_proxy_main 13>; 212 reg-names = "debug_messages"; 213 reg = <0x00 0x44043000 0x00 0xfe0>; 214 215 k3_pds: power-controller { 216 bootph-all; 217 compatible = "ti,sci-pm-domain"; 218 #power-domain-cells = <2>; 219 }; 220 221 k3_clks: clock-controller { 222 bootph-all; 223 compatible = "ti,k2g-sci-clk"; 224 #clock-cells = <2>; 225 }; 226 227 k3_reset: reset-controller { 228 bootph-all; 229 compatible = "ti,sci-reset"; 230 #reset-cells = <2>; 231 }; 232 }; 233 234 main_pmx0: pinctrl@f4000 { 235 bootph-all; 236 compatible = "pinctrl-single"; 237 reg = <0x00 0xf4000 0x00 0x2d0>; 238 #pinctrl-cells = <1>; 239 pinctrl-single,register-width = <32>; 240 pinctrl-single,function-mask = <0xffffffff>; 241 }; 242 243 main_timer0: timer@2400000 { 244 bootph-all; 245 compatible = "ti,am654-timer"; 246 reg = <0x00 0x2400000 0x00 0x400>; 247 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&k3_clks 36 1>; 249 clock-names = "fck"; 250 assigned-clocks = <&k3_clks 36 1>; 251 assigned-clock-parents = <&k3_clks 36 2>; 252 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 253 ti,timer-pwm; 254 }; 255 256 main_timer1: timer@2410000 { 257 compatible = "ti,am654-timer"; 258 reg = <0x00 0x2410000 0x00 0x400>; 259 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 260 clocks = <&k3_clks 37 1>; 261 clock-names = "fck"; 262 assigned-clocks = <&k3_clks 37 1>; 263 assigned-clock-parents = <&k3_clks 37 2>; 264 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 265 ti,timer-pwm; 266 }; 267 268 main_timer2: timer@2420000 { 269 compatible = "ti,am654-timer"; 270 reg = <0x00 0x2420000 0x00 0x400>; 271 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 272 clocks = <&k3_clks 38 1>; 273 clock-names = "fck"; 274 assigned-clocks = <&k3_clks 38 1>; 275 assigned-clock-parents = <&k3_clks 38 2>; 276 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 277 ti,timer-pwm; 278 }; 279 280 main_timer3: timer@2430000 { 281 compatible = "ti,am654-timer"; 282 reg = <0x00 0x2430000 0x00 0x400>; 283 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&k3_clks 39 1>; 285 clock-names = "fck"; 286 assigned-clocks = <&k3_clks 39 1>; 287 assigned-clock-parents = <&k3_clks 39 2>; 288 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 289 ti,timer-pwm; 290 }; 291 292 main_timer4: timer@2440000 { 293 compatible = "ti,am654-timer"; 294 reg = <0x00 0x2440000 0x00 0x400>; 295 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&k3_clks 40 1>; 297 clock-names = "fck"; 298 assigned-clocks = <&k3_clks 40 1>; 299 assigned-clock-parents = <&k3_clks 40 2>; 300 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 301 ti,timer-pwm; 302 }; 303 304 main_timer5: timer@2450000 { 305 compatible = "ti,am654-timer"; 306 reg = <0x00 0x2450000 0x00 0x400>; 307 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 308 clocks = <&k3_clks 41 1>; 309 clock-names = "fck"; 310 assigned-clocks = <&k3_clks 41 1>; 311 assigned-clock-parents = <&k3_clks 41 2>; 312 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 313 ti,timer-pwm; 314 }; 315 316 main_timer6: timer@2460000 { 317 compatible = "ti,am654-timer"; 318 reg = <0x00 0x2460000 0x00 0x400>; 319 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 320 clocks = <&k3_clks 42 1>; 321 clock-names = "fck"; 322 assigned-clocks = <&k3_clks 42 1>; 323 assigned-clock-parents = <&k3_clks 42 2>; 324 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 325 ti,timer-pwm; 326 }; 327 328 main_timer7: timer@2470000 { 329 compatible = "ti,am654-timer"; 330 reg = <0x00 0x2470000 0x00 0x400>; 331 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&k3_clks 43 1>; 333 clock-names = "fck"; 334 assigned-clocks = <&k3_clks 43 1>; 335 assigned-clock-parents = <&k3_clks 43 2>; 336 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 337 ti,timer-pwm; 338 }; 339 340 main_timer8: timer@2480000 { 341 compatible = "ti,am654-timer"; 342 reg = <0x00 0x2480000 0x00 0x400>; 343 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&k3_clks 44 1>; 345 clock-names = "fck"; 346 assigned-clocks = <&k3_clks 44 1>; 347 assigned-clock-parents = <&k3_clks 44 2>; 348 power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>; 349 ti,timer-pwm; 350 }; 351 352 main_timer9: timer@2490000 { 353 compatible = "ti,am654-timer"; 354 reg = <0x00 0x2490000 0x00 0x400>; 355 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 356 clocks = <&k3_clks 45 1>; 357 clock-names = "fck"; 358 assigned-clocks = <&k3_clks 45 1>; 359 assigned-clock-parents = <&k3_clks 45 2>; 360 power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>; 361 ti,timer-pwm; 362 }; 363 364 main_timer10: timer@24a0000 { 365 compatible = "ti,am654-timer"; 366 reg = <0x00 0x24a0000 0x00 0x400>; 367 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 368 clocks = <&k3_clks 46 1>; 369 clock-names = "fck"; 370 assigned-clocks = <&k3_clks 46 1>; 371 assigned-clock-parents = <&k3_clks 46 2>; 372 power-domains = <&k3_pds 46 TI_SCI_PD_EXCLUSIVE>; 373 ti,timer-pwm; 374 }; 375 376 main_timer11: timer@24b0000 { 377 compatible = "ti,am654-timer"; 378 reg = <0x00 0x24b0000 0x00 0x400>; 379 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 380 clocks = <&k3_clks 47 1>; 381 clock-names = "fck"; 382 assigned-clocks = <&k3_clks 47 1>; 383 assigned-clock-parents = <&k3_clks 47 2>; 384 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; 385 ti,timer-pwm; 386 }; 387 388 main_esm: esm@420000 { 389 bootph-pre-ram; 390 compatible = "ti,j721e-esm"; 391 reg = <0x00 0x420000 0x00 0x1000>; 392 ti,esm-pins = <160>, <161>; 393 }; 394 395 main_uart0: serial@2800000 { 396 compatible = "ti,am64-uart", "ti,am654-uart"; 397 reg = <0x00 0x02800000 0x00 0x100>; 398 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 399 clock-frequency = <48000000>; 400 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 401 clocks = <&k3_clks 146 0>; 402 clock-names = "fclk"; 403 status = "disabled"; 404 }; 405 406 main_uart1: serial@2810000 { 407 compatible = "ti,am64-uart", "ti,am654-uart"; 408 reg = <0x00 0x02810000 0x00 0x100>; 409 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 410 clock-frequency = <48000000>; 411 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 412 clocks = <&k3_clks 152 0>; 413 clock-names = "fclk"; 414 status = "disabled"; 415 }; 416 417 main_uart2: serial@2820000 { 418 compatible = "ti,am64-uart", "ti,am654-uart"; 419 reg = <0x00 0x02820000 0x00 0x100>; 420 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 421 clock-frequency = <48000000>; 422 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 423 clocks = <&k3_clks 153 0>; 424 clock-names = "fclk"; 425 status = "disabled"; 426 }; 427 428 main_uart3: serial@2830000 { 429 compatible = "ti,am64-uart", "ti,am654-uart"; 430 reg = <0x00 0x02830000 0x00 0x100>; 431 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 432 clock-frequency = <48000000>; 433 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 434 clocks = <&k3_clks 154 0>; 435 clock-names = "fclk"; 436 status = "disabled"; 437 }; 438 439 main_uart4: serial@2840000 { 440 compatible = "ti,am64-uart", "ti,am654-uart"; 441 reg = <0x00 0x02840000 0x00 0x100>; 442 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 443 clock-frequency = <48000000>; 444 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 445 clocks = <&k3_clks 155 0>; 446 clock-names = "fclk"; 447 status = "disabled"; 448 }; 449 450 main_uart5: serial@2850000 { 451 compatible = "ti,am64-uart", "ti,am654-uart"; 452 reg = <0x00 0x02850000 0x00 0x100>; 453 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 454 clock-frequency = <48000000>; 455 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 456 clocks = <&k3_clks 156 0>; 457 clock-names = "fclk"; 458 status = "disabled"; 459 }; 460 461 main_uart6: serial@2860000 { 462 compatible = "ti,am64-uart", "ti,am654-uart"; 463 reg = <0x00 0x02860000 0x00 0x100>; 464 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 465 clock-frequency = <48000000>; 466 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 467 clocks = <&k3_clks 158 0>; 468 clock-names = "fclk"; 469 status = "disabled"; 470 }; 471 472 main_i2c0: i2c@20000000 { 473 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 474 reg = <0x00 0x20000000 0x00 0x100>; 475 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 479 clocks = <&k3_clks 102 2>; 480 clock-names = "fck"; 481 status = "disabled"; 482 }; 483 484 main_i2c1: i2c@20010000 { 485 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 486 reg = <0x00 0x20010000 0x00 0x100>; 487 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 488 #address-cells = <1>; 489 #size-cells = <0>; 490 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 491 clocks = <&k3_clks 103 2>; 492 clock-names = "fck"; 493 status = "disabled"; 494 }; 495 496 main_i2c2: i2c@20020000 { 497 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 498 reg = <0x00 0x20020000 0x00 0x100>; 499 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 500 #address-cells = <1>; 501 #size-cells = <0>; 502 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 503 clocks = <&k3_clks 104 2>; 504 clock-names = "fck"; 505 status = "disabled"; 506 }; 507 508 main_i2c3: i2c@20030000 { 509 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 510 reg = <0x00 0x20030000 0x00 0x100>; 511 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 512 #address-cells = <1>; 513 #size-cells = <0>; 514 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 515 clocks = <&k3_clks 105 2>; 516 clock-names = "fck"; 517 status = "disabled"; 518 }; 519 520 main_spi0: spi@20100000 { 521 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 522 reg = <0x00 0x20100000 0x00 0x400>; 523 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 524 #address-cells = <1>; 525 #size-cells = <0>; 526 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 527 clocks = <&k3_clks 141 0>; 528 dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>; 529 dma-names = "tx0", "rx0"; 530 status = "disabled"; 531 }; 532 533 main_spi1: spi@20110000 { 534 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 535 reg = <0x00 0x20110000 0x00 0x400>; 536 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 537 #address-cells = <1>; 538 #size-cells = <0>; 539 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 540 clocks = <&k3_clks 142 0>; 541 status = "disabled"; 542 }; 543 544 main_spi2: spi@20120000 { 545 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 546 reg = <0x00 0x20120000 0x00 0x400>; 547 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 548 #address-cells = <1>; 549 #size-cells = <0>; 550 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 551 clocks = <&k3_clks 143 0>; 552 status = "disabled"; 553 }; 554 555 main_spi3: spi@20130000 { 556 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 557 reg = <0x00 0x20130000 0x00 0x400>; 558 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; 562 clocks = <&k3_clks 144 0>; 563 status = "disabled"; 564 }; 565 566 main_spi4: spi@20140000 { 567 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 568 reg = <0x00 0x20140000 0x00 0x400>; 569 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 570 #address-cells = <1>; 571 #size-cells = <0>; 572 power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>; 573 clocks = <&k3_clks 145 0>; 574 status = "disabled"; 575 }; 576 577 main_gpio_intr: interrupt-controller@a00000 { 578 compatible = "ti,sci-intr"; 579 reg = <0x00 0x00a00000 0x00 0x800>; 580 ti,intr-trigger-type = <1>; 581 interrupt-controller; 582 interrupt-parent = <&gic500>; 583 #interrupt-cells = <1>; 584 ti,sci = <&dmsc>; 585 ti,sci-dev-id = <3>; 586 ti,interrupt-ranges = <0 32 16>; 587 }; 588 589 main_gpio0: gpio@600000 { 590 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 591 reg = <0x0 0x00600000 0x0 0x100>; 592 gpio-controller; 593 #gpio-cells = <2>; 594 interrupt-parent = <&main_gpio_intr>; 595 interrupts = <190>, <191>, <192>, 596 <193>, <194>, <195>; 597 interrupt-controller; 598 #interrupt-cells = <2>; 599 ti,ngpio = <87>; 600 ti,davinci-gpio-unbanked = <0>; 601 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 602 clocks = <&k3_clks 77 0>; 603 clock-names = "gpio"; 604 }; 605 606 main_gpio1: gpio@601000 { 607 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 608 reg = <0x0 0x00601000 0x0 0x100>; 609 gpio-controller; 610 #gpio-cells = <2>; 611 interrupt-parent = <&main_gpio_intr>; 612 interrupts = <180>, <181>, <182>, 613 <183>, <184>, <185>; 614 interrupt-controller; 615 #interrupt-cells = <2>; 616 ti,ngpio = <88>; 617 ti,davinci-gpio-unbanked = <0>; 618 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 619 clocks = <&k3_clks 78 0>; 620 clock-names = "gpio"; 621 }; 622 623 sdhci0: mmc@fa10000 { 624 compatible = "ti,am64-sdhci-8bit"; 625 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; 626 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 627 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 628 clocks = <&k3_clks 57 0>, <&k3_clks 57 1>; 629 clock-names = "clk_ahb", "clk_xin"; 630 bus-width = <8>; 631 mmc-ddr-1_8v; 632 mmc-hs200-1_8v; 633 ti,clkbuf-sel = <0x7>; 634 ti,trm-icp = <0x2>; 635 ti,otap-del-sel-legacy = <0x0>; 636 ti,otap-del-sel-mmc-hs = <0x0>; 637 ti,otap-del-sel-ddr52 = <0x6>; 638 ti,otap-del-sel-hs200 = <0x7>; 639 ti,itap-del-sel-legacy = <0x10>; 640 ti,itap-del-sel-mmc-hs = <0xa>; 641 ti,itap-del-sel-ddr52 = <0x3>; 642 status = "disabled"; 643 }; 644 645 sdhci1: mmc@fa00000 { 646 compatible = "ti,am64-sdhci-4bit"; 647 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; 648 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 649 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 650 clocks = <&k3_clks 58 3>, <&k3_clks 58 4>; 651 clock-names = "clk_ahb", "clk_xin"; 652 bus-width = <4>; 653 ti,clkbuf-sel = <0x7>; 654 ti,otap-del-sel-legacy = <0x0>; 655 ti,otap-del-sel-sd-hs = <0x0>; 656 ti,otap-del-sel-sdr12 = <0xf>; 657 ti,otap-del-sel-sdr25 = <0xf>; 658 ti,otap-del-sel-sdr50 = <0xc>; 659 ti,otap-del-sel-sdr104 = <0x6>; 660 ti,otap-del-sel-ddr50 = <0x9>; 661 ti,itap-del-sel-legacy = <0x0>; 662 ti,itap-del-sel-sd-hs = <0x0>; 663 ti,itap-del-sel-sdr12 = <0x0>; 664 ti,itap-del-sel-sdr25 = <0x0>; 665 status = "disabled"; 666 }; 667 668 cpsw3g: ethernet@8000000 { 669 compatible = "ti,am642-cpsw-nuss"; 670 #address-cells = <2>; 671 #size-cells = <2>; 672 reg = <0x0 0x8000000 0x0 0x200000>; 673 reg-names = "cpsw_nuss"; 674 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>; 675 clocks = <&k3_clks 13 0>; 676 assigned-clocks = <&k3_clks 13 1>; 677 assigned-clock-parents = <&k3_clks 13 9>; 678 clock-names = "fck"; 679 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 680 681 dmas = <&main_pktdma 0xC500 15>, 682 <&main_pktdma 0xC501 15>, 683 <&main_pktdma 0xC502 15>, 684 <&main_pktdma 0xC503 15>, 685 <&main_pktdma 0xC504 15>, 686 <&main_pktdma 0xC505 15>, 687 <&main_pktdma 0xC506 15>, 688 <&main_pktdma 0xC507 15>, 689 <&main_pktdma 0x4500 15>; 690 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 691 "tx7", "rx"; 692 693 ethernet-ports { 694 #address-cells = <1>; 695 #size-cells = <0>; 696 697 cpsw_port1: port@1 { 698 reg = <1>; 699 ti,mac-only; 700 label = "port1"; 701 phys = <&phy_gmii_sel 1>; 702 mac-address = [00 00 00 00 00 00]; 703 ti,syscon-efuse = <&main_conf 0x200>; 704 }; 705 706 cpsw_port2: port@2 { 707 reg = <2>; 708 ti,mac-only; 709 label = "port2"; 710 phys = <&phy_gmii_sel 2>; 711 mac-address = [00 00 00 00 00 00]; 712 }; 713 }; 714 715 cpsw3g_mdio: mdio@f00 { 716 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 717 reg = <0x0 0xf00 0x0 0x100>; 718 #address-cells = <1>; 719 #size-cells = <0>; 720 clocks = <&k3_clks 13 0>; 721 clock-names = "fck"; 722 bus_freq = <1000000>; 723 status = "disabled"; 724 }; 725 726 cpts@3d000 { 727 compatible = "ti,j721e-cpts"; 728 reg = <0x0 0x3d000 0x0 0x400>; 729 clocks = <&k3_clks 13 1>; 730 clock-names = "cpts"; 731 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 732 interrupt-names = "cpts"; 733 ti,cpts-ext-ts-inputs = <4>; 734 ti,cpts-periodic-outputs = <2>; 735 }; 736 }; 737 738 main_cpts0: cpts@39000000 { 739 compatible = "ti,j721e-cpts"; 740 reg = <0x0 0x39000000 0x0 0x400>; 741 reg-names = "cpts"; 742 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; 743 clocks = <&k3_clks 84 0>; 744 clock-names = "cpts"; 745 assigned-clocks = <&k3_clks 84 0>; 746 assigned-clock-parents = <&k3_clks 84 8>; 747 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 748 interrupt-names = "cpts"; 749 ti,cpts-periodic-outputs = <6>; 750 ti,cpts-ext-ts-inputs = <8>; 751 }; 752 753 timesync_router: pinctrl@a40000 { 754 compatible = "pinctrl-single"; 755 reg = <0x0 0xa40000 0x0 0x800>; 756 #pinctrl-cells = <1>; 757 pinctrl-single,register-width = <32>; 758 pinctrl-single,function-mask = <0x000107ff>; 759 }; 760 761 usbss0: cdns-usb@f900000 { 762 compatible = "ti,am64-usb"; 763 reg = <0x00 0xf900000 0x00 0x100>; 764 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 765 clocks = <&k3_clks 161 9>, <&k3_clks 161 1>; 766 clock-names = "ref", "lpm"; 767 assigned-clocks = <&k3_clks 161 9>; /* USB2_REFCLK */ 768 assigned-clock-parents = <&k3_clks 161 10>; /* HF0SC0 */ 769 #address-cells = <2>; 770 #size-cells = <2>; 771 ranges; 772 usb0: usb@f400000 { 773 compatible = "cdns,usb3"; 774 reg = <0x00 0xf400000 0x00 0x10000>, 775 <0x00 0xf410000 0x00 0x10000>, 776 <0x00 0xf420000 0x00 0x10000>; 777 reg-names = "otg", 778 "xhci", 779 "dev"; 780 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 781 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 782 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */ 783 interrupt-names = "host", 784 "peripheral", 785 "otg"; 786 maximum-speed = "super-speed"; 787 dr_mode = "otg"; 788 }; 789 }; 790 791 tscadc0: tscadc@28001000 { 792 compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; 793 reg = <0x00 0x28001000 0x00 0x1000>; 794 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 795 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 796 clocks = <&k3_clks 0 0>; 797 assigned-clocks = <&k3_clks 0 0>; 798 assigned-clock-parents = <&k3_clks 0 3>; 799 assigned-clock-rates = <60000000>; 800 clock-names = "fck"; 801 status = "disabled"; 802 803 adc { 804 #io-channel-cells = <1>; 805 compatible = "ti,am654-adc", "ti,am3359-adc"; 806 }; 807 }; 808 809 fss: bus@fc00000 { 810 compatible = "simple-bus"; 811 reg = <0x00 0x0fc00000 0x00 0x70000>; 812 #address-cells = <2>; 813 #size-cells = <2>; 814 ranges; 815 816 ospi0: spi@fc40000 { 817 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 818 reg = <0x00 0x0fc40000 0x00 0x100>, 819 <0x05 0x00000000 0x01 0x00000000>; 820 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 821 cdns,fifo-depth = <256>; 822 cdns,fifo-width = <4>; 823 cdns,trigger-address = <0x0>; 824 #address-cells = <0x1>; 825 #size-cells = <0x0>; 826 clocks = <&k3_clks 75 6>; 827 assigned-clocks = <&k3_clks 75 6>; 828 assigned-clock-parents = <&k3_clks 75 7>; 829 assigned-clock-rates = <166666666>; 830 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 831 status = "disabled"; 832 }; 833 }; 834 835 hwspinlock: spinlock@2a000000 { 836 compatible = "ti,am64-hwspinlock"; 837 reg = <0x00 0x2a000000 0x00 0x1000>; 838 #hwlock-cells = <1>; 839 }; 840 841 mailbox0_cluster2: mailbox@29020000 { 842 compatible = "ti,am64-mailbox"; 843 reg = <0x00 0x29020000 0x00 0x200>; 844 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 846 #mbox-cells = <1>; 847 ti,mbox-num-users = <4>; 848 ti,mbox-num-fifos = <16>; 849 status = "disabled"; 850 }; 851 852 mailbox0_cluster3: mailbox@29030000 { 853 compatible = "ti,am64-mailbox"; 854 reg = <0x00 0x29030000 0x00 0x200>; 855 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 857 #mbox-cells = <1>; 858 ti,mbox-num-users = <4>; 859 ti,mbox-num-fifos = <16>; 860 status = "disabled"; 861 }; 862 863 mailbox0_cluster4: mailbox@29040000 { 864 compatible = "ti,am64-mailbox"; 865 reg = <0x00 0x29040000 0x00 0x200>; 866 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 867 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 868 #mbox-cells = <1>; 869 ti,mbox-num-users = <4>; 870 ti,mbox-num-fifos = <16>; 871 status = "disabled"; 872 }; 873 874 mailbox0_cluster5: mailbox@29050000 { 875 compatible = "ti,am64-mailbox"; 876 reg = <0x00 0x29050000 0x00 0x200>; 877 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 879 #mbox-cells = <1>; 880 ti,mbox-num-users = <4>; 881 ti,mbox-num-fifos = <16>; 882 status = "disabled"; 883 }; 884 885 mailbox0_cluster6: mailbox@29060000 { 886 compatible = "ti,am64-mailbox"; 887 reg = <0x00 0x29060000 0x00 0x200>; 888 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 889 #mbox-cells = <1>; 890 ti,mbox-num-users = <4>; 891 ti,mbox-num-fifos = <16>; 892 status = "disabled"; 893 }; 894 895 mailbox0_cluster7: mailbox@29070000 { 896 compatible = "ti,am64-mailbox"; 897 reg = <0x00 0x29070000 0x00 0x200>; 898 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 899 #mbox-cells = <1>; 900 ti,mbox-num-users = <4>; 901 ti,mbox-num-fifos = <16>; 902 status = "disabled"; 903 }; 904 905 main_r5fss0: r5fss@78000000 { 906 compatible = "ti,am64-r5fss"; 907 ti,cluster-mode = <0>; 908 #address-cells = <1>; 909 #size-cells = <1>; 910 ranges = <0x78000000 0x00 0x78000000 0x10000>, 911 <0x78100000 0x00 0x78100000 0x10000>, 912 <0x78200000 0x00 0x78200000 0x08000>, 913 <0x78300000 0x00 0x78300000 0x08000>; 914 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; 915 916 main_r5fss0_core0: r5f@78000000 { 917 compatible = "ti,am64-r5f"; 918 reg = <0x78000000 0x00010000>, 919 <0x78100000 0x00010000>; 920 reg-names = "atcm", "btcm"; 921 ti,sci = <&dmsc>; 922 ti,sci-dev-id = <121>; 923 ti,sci-proc-ids = <0x01 0xff>; 924 resets = <&k3_reset 121 1>; 925 firmware-name = "am64-main-r5f0_0-fw"; 926 ti,atcm-enable = <1>; 927 ti,btcm-enable = <1>; 928 ti,loczrama = <1>; 929 }; 930 931 main_r5fss0_core1: r5f@78200000 { 932 compatible = "ti,am64-r5f"; 933 reg = <0x78200000 0x00008000>, 934 <0x78300000 0x00008000>; 935 reg-names = "atcm", "btcm"; 936 ti,sci = <&dmsc>; 937 ti,sci-dev-id = <122>; 938 ti,sci-proc-ids = <0x02 0xff>; 939 resets = <&k3_reset 122 1>; 940 firmware-name = "am64-main-r5f0_1-fw"; 941 ti,atcm-enable = <1>; 942 ti,btcm-enable = <1>; 943 ti,loczrama = <1>; 944 }; 945 }; 946 947 main_r5fss1: r5fss@78400000 { 948 compatible = "ti,am64-r5fss"; 949 ti,cluster-mode = <0>; 950 #address-cells = <1>; 951 #size-cells = <1>; 952 ranges = <0x78400000 0x00 0x78400000 0x10000>, 953 <0x78500000 0x00 0x78500000 0x10000>, 954 <0x78600000 0x00 0x78600000 0x08000>, 955 <0x78700000 0x00 0x78700000 0x08000>; 956 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 957 958 main_r5fss1_core0: r5f@78400000 { 959 compatible = "ti,am64-r5f"; 960 reg = <0x78400000 0x00010000>, 961 <0x78500000 0x00010000>; 962 reg-names = "atcm", "btcm"; 963 ti,sci = <&dmsc>; 964 ti,sci-dev-id = <123>; 965 ti,sci-proc-ids = <0x06 0xff>; 966 resets = <&k3_reset 123 1>; 967 firmware-name = "am64-main-r5f1_0-fw"; 968 ti,atcm-enable = <1>; 969 ti,btcm-enable = <1>; 970 ti,loczrama = <1>; 971 }; 972 973 main_r5fss1_core1: r5f@78600000 { 974 compatible = "ti,am64-r5f"; 975 reg = <0x78600000 0x00008000>, 976 <0x78700000 0x00008000>; 977 reg-names = "atcm", "btcm"; 978 ti,sci = <&dmsc>; 979 ti,sci-dev-id = <124>; 980 ti,sci-proc-ids = <0x07 0xff>; 981 resets = <&k3_reset 124 1>; 982 firmware-name = "am64-main-r5f1_1-fw"; 983 ti,atcm-enable = <1>; 984 ti,btcm-enable = <1>; 985 ti,loczrama = <1>; 986 }; 987 }; 988 989 serdes_wiz0: wiz@f000000 { 990 compatible = "ti,am64-wiz-10g"; 991 #address-cells = <1>; 992 #size-cells = <1>; 993 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 994 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>; 995 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 996 num-lanes = <1>; 997 #reset-cells = <1>; 998 #clock-cells = <1>; 999 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; 1000 1001 assigned-clocks = <&k3_clks 162 1>; 1002 assigned-clock-parents = <&k3_clks 162 5>; 1003 1004 serdes0: serdes@f000000 { 1005 compatible = "ti,j721e-serdes-10g"; 1006 reg = <0x0f000000 0x00010000>; 1007 reg-names = "torrent_phy"; 1008 resets = <&serdes_wiz0 0>; 1009 reset-names = "torrent_reset"; 1010 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1011 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; 1012 clock-names = "refclk", "phy_en_refclk"; 1013 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1014 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, 1015 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; 1016 assigned-clock-parents = <&k3_clks 162 1>, 1017 <&k3_clks 162 1>, 1018 <&k3_clks 162 1>; 1019 #address-cells = <1>; 1020 #size-cells = <0>; 1021 #clock-cells = <1>; 1022 }; 1023 }; 1024 1025 pcie0_rc: pcie@f102000 { 1026 compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host"; 1027 reg = <0x00 0x0f102000 0x00 0x1000>, 1028 <0x00 0x0f100000 0x00 0x400>, 1029 <0x00 0x0d000000 0x00 0x00800000>, 1030 <0x00 0x68000000 0x00 0x00001000>; 1031 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1032 interrupt-names = "link_state"; 1033 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 1034 device_type = "pci"; 1035 ti,syscon-pcie-ctrl = <&main_conf 0x4070>; 1036 max-link-speed = <2>; 1037 num-lanes = <1>; 1038 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 1039 clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; 1040 clock-names = "fck", "pcie_refclk"; 1041 #address-cells = <3>; 1042 #size-cells = <2>; 1043 bus-range = <0x0 0xff>; 1044 cdns,no-bar-match-nbits = <64>; 1045 vendor-id = <0x104c>; 1046 device-id = <0xb010>; 1047 msi-map = <0x0 &gic_its 0x0 0x10000>; 1048 ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, 1049 <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; 1050 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>; 1051 status = "disabled"; 1052 }; 1053 1054 epwm0: pwm@23000000 { 1055 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1056 #pwm-cells = <3>; 1057 reg = <0x0 0x23000000 0x0 0x100>; 1058 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 1059 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 1060 clock-names = "tbclk", "fck"; 1061 status = "disabled"; 1062 }; 1063 1064 epwm1: pwm@23010000 { 1065 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1066 #pwm-cells = <3>; 1067 reg = <0x0 0x23010000 0x0 0x100>; 1068 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 1069 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 1070 clock-names = "tbclk", "fck"; 1071 status = "disabled"; 1072 }; 1073 1074 epwm2: pwm@23020000 { 1075 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1076 #pwm-cells = <3>; 1077 reg = <0x0 0x23020000 0x0 0x100>; 1078 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 1079 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 1080 clock-names = "tbclk", "fck"; 1081 status = "disabled"; 1082 }; 1083 1084 epwm3: pwm@23030000 { 1085 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1086 #pwm-cells = <3>; 1087 reg = <0x0 0x23030000 0x0 0x100>; 1088 power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; 1089 clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>; 1090 clock-names = "tbclk", "fck"; 1091 status = "disabled"; 1092 }; 1093 1094 epwm4: pwm@23040000 { 1095 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1096 #pwm-cells = <3>; 1097 reg = <0x0 0x23040000 0x0 0x100>; 1098 power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; 1099 clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>; 1100 clock-names = "tbclk", "fck"; 1101 status = "disabled"; 1102 }; 1103 1104 epwm5: pwm@23050000 { 1105 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1106 #pwm-cells = <3>; 1107 reg = <0x0 0x23050000 0x0 0x100>; 1108 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 1109 clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>; 1110 clock-names = "tbclk", "fck"; 1111 status = "disabled"; 1112 }; 1113 1114 epwm6: pwm@23060000 { 1115 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1116 #pwm-cells = <3>; 1117 reg = <0x0 0x23060000 0x0 0x100>; 1118 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 1119 clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>; 1120 clock-names = "tbclk", "fck"; 1121 status = "disabled"; 1122 }; 1123 1124 epwm7: pwm@23070000 { 1125 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1126 #pwm-cells = <3>; 1127 reg = <0x0 0x23070000 0x0 0x100>; 1128 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 1129 clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>; 1130 clock-names = "tbclk", "fck"; 1131 status = "disabled"; 1132 }; 1133 1134 epwm8: pwm@23080000 { 1135 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1136 #pwm-cells = <3>; 1137 reg = <0x0 0x23080000 0x0 0x100>; 1138 power-domains = <&k3_pds 94 TI_SCI_PD_EXCLUSIVE>; 1139 clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>; 1140 clock-names = "tbclk", "fck"; 1141 status = "disabled"; 1142 }; 1143 1144 ecap0: pwm@23100000 { 1145 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 1146 #pwm-cells = <3>; 1147 reg = <0x0 0x23100000 0x0 0x60>; 1148 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 1149 clocks = <&k3_clks 51 0>; 1150 clock-names = "fck"; 1151 status = "disabled"; 1152 }; 1153 1154 ecap1: pwm@23110000 { 1155 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 1156 #pwm-cells = <3>; 1157 reg = <0x0 0x23110000 0x0 0x60>; 1158 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 1159 clocks = <&k3_clks 52 0>; 1160 clock-names = "fck"; 1161 status = "disabled"; 1162 }; 1163 1164 ecap2: pwm@23120000 { 1165 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 1166 #pwm-cells = <3>; 1167 reg = <0x0 0x23120000 0x0 0x60>; 1168 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 1169 clocks = <&k3_clks 53 0>; 1170 clock-names = "fck"; 1171 status = "disabled"; 1172 }; 1173 1174 main_rti0: watchdog@e000000 { 1175 compatible = "ti,j7-rti-wdt"; 1176 reg = <0x00 0xe000000 0x00 0x100>; 1177 clocks = <&k3_clks 125 0>; 1178 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 1179 assigned-clocks = <&k3_clks 125 0>; 1180 assigned-clock-parents = <&k3_clks 125 2>; 1181 }; 1182 1183 main_rti1: watchdog@e010000 { 1184 compatible = "ti,j7-rti-wdt"; 1185 reg = <0x00 0xe010000 0x00 0x100>; 1186 clocks = <&k3_clks 126 0>; 1187 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; 1188 assigned-clocks = <&k3_clks 126 0>; 1189 assigned-clock-parents = <&k3_clks 126 2>; 1190 }; 1191 1192 icssg0: icssg@30000000 { 1193 compatible = "ti,am642-icssg"; 1194 reg = <0x00 0x30000000 0x00 0x80000>; 1195 power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; 1196 #address-cells = <1>; 1197 #size-cells = <1>; 1198 ranges = <0x0 0x00 0x30000000 0x80000>; 1199 1200 icssg0_mem: memories@0 { 1201 reg = <0x0 0x2000>, 1202 <0x2000 0x2000>, 1203 <0x10000 0x10000>; 1204 reg-names = "dram0", "dram1", "shrdram2"; 1205 }; 1206 1207 icssg0_cfg: cfg@26000 { 1208 compatible = "ti,pruss-cfg", "syscon"; 1209 reg = <0x26000 0x200>; 1210 #address-cells = <1>; 1211 #size-cells = <1>; 1212 ranges = <0x0 0x26000 0x2000>; 1213 1214 clocks { 1215 #address-cells = <1>; 1216 #size-cells = <0>; 1217 1218 icssg0_coreclk_mux: coreclk-mux@3c { 1219 reg = <0x3c>; 1220 #clock-cells = <0>; 1221 clocks = <&k3_clks 81 0>, /* icssg0_core_clk */ 1222 <&k3_clks 81 20>; /* icssg0_iclk */ 1223 assigned-clocks = <&icssg0_coreclk_mux>; 1224 assigned-clock-parents = <&k3_clks 81 20>; 1225 }; 1226 1227 icssg0_iepclk_mux: iepclk-mux@30 { 1228 reg = <0x30>; 1229 #clock-cells = <0>; 1230 clocks = <&k3_clks 81 3>, /* icssg0_iep_clk */ 1231 <&icssg0_coreclk_mux>; /* icssg0_coreclk_mux */ 1232 assigned-clocks = <&icssg0_iepclk_mux>; 1233 assigned-clock-parents = <&icssg0_coreclk_mux>; 1234 }; 1235 }; 1236 }; 1237 1238 icssg0_iep0: iep@2e000 { 1239 compatible = "ti,am654-icss-iep"; 1240 reg = <0x2e000 0x1000>; 1241 clocks = <&icssg0_iepclk_mux>; 1242 }; 1243 1244 icssg0_iep1: iep@2f000 { 1245 compatible = "ti,am654-icss-iep"; 1246 reg = <0x2f000 0x1000>; 1247 clocks = <&icssg0_iepclk_mux>; 1248 }; 1249 1250 icssg0_mii_rt: mii-rt@32000 { 1251 compatible = "ti,pruss-mii", "syscon"; 1252 reg = <0x32000 0x100>; 1253 }; 1254 1255 icssg0_mii_g_rt: mii-g-rt@33000 { 1256 compatible = "ti,pruss-mii-g", "syscon"; 1257 reg = <0x33000 0x1000>; 1258 }; 1259 1260 icssg0_intc: interrupt-controller@20000 { 1261 compatible = "ti,icssg-intc"; 1262 reg = <0x20000 0x2000>; 1263 interrupt-controller; 1264 #interrupt-cells = <3>; 1265 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1266 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1273 interrupt-names = "host_intr0", "host_intr1", 1274 "host_intr2", "host_intr3", 1275 "host_intr4", "host_intr5", 1276 "host_intr6", "host_intr7"; 1277 }; 1278 1279 pru0_0: pru@34000 { 1280 compatible = "ti,am642-pru"; 1281 reg = <0x34000 0x3000>, 1282 <0x22000 0x100>, 1283 <0x22400 0x100>; 1284 reg-names = "iram", "control", "debug"; 1285 firmware-name = "am64x-pru0_0-fw"; 1286 }; 1287 1288 rtu0_0: rtu@4000 { 1289 compatible = "ti,am642-rtu"; 1290 reg = <0x4000 0x2000>, 1291 <0x23000 0x100>, 1292 <0x23400 0x100>; 1293 reg-names = "iram", "control", "debug"; 1294 firmware-name = "am64x-rtu0_0-fw"; 1295 }; 1296 1297 tx_pru0_0: txpru@a000 { 1298 compatible = "ti,am642-tx-pru"; 1299 reg = <0xa000 0x1800>, 1300 <0x25000 0x100>, 1301 <0x25400 0x100>; 1302 reg-names = "iram", "control", "debug"; 1303 firmware-name = "am64x-txpru0_0-fw"; 1304 }; 1305 1306 pru0_1: pru@38000 { 1307 compatible = "ti,am642-pru"; 1308 reg = <0x38000 0x3000>, 1309 <0x24000 0x100>, 1310 <0x24400 0x100>; 1311 reg-names = "iram", "control", "debug"; 1312 firmware-name = "am64x-pru0_1-fw"; 1313 }; 1314 1315 rtu0_1: rtu@6000 { 1316 compatible = "ti,am642-rtu"; 1317 reg = <0x6000 0x2000>, 1318 <0x23800 0x100>, 1319 <0x23c00 0x100>; 1320 reg-names = "iram", "control", "debug"; 1321 firmware-name = "am64x-rtu0_1-fw"; 1322 }; 1323 1324 tx_pru0_1: txpru@c000 { 1325 compatible = "ti,am642-tx-pru"; 1326 reg = <0xc000 0x1800>, 1327 <0x25800 0x100>, 1328 <0x25c00 0x100>; 1329 reg-names = "iram", "control", "debug"; 1330 firmware-name = "am64x-txpru0_1-fw"; 1331 }; 1332 1333 icssg0_mdio: mdio@32400 { 1334 compatible = "ti,davinci_mdio"; 1335 reg = <0x32400 0x100>; 1336 clocks = <&k3_clks 62 3>; 1337 clock-names = "fck"; 1338 #address-cells = <1>; 1339 #size-cells = <0>; 1340 bus_freq = <1000000>; 1341 status = "disabled"; 1342 }; 1343 }; 1344 1345 icssg1: icssg@30080000 { 1346 compatible = "ti,am642-icssg"; 1347 reg = <0x00 0x30080000 0x00 0x80000>; 1348 power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>; 1349 #address-cells = <1>; 1350 #size-cells = <1>; 1351 ranges = <0x0 0x00 0x30080000 0x80000>; 1352 1353 icssg1_mem: memories@0 { 1354 reg = <0x0 0x2000>, 1355 <0x2000 0x2000>, 1356 <0x10000 0x10000>; 1357 reg-names = "dram0", "dram1", "shrdram2"; 1358 }; 1359 1360 icssg1_cfg: cfg@26000 { 1361 compatible = "ti,pruss-cfg", "syscon"; 1362 reg = <0x26000 0x200>; 1363 #address-cells = <1>; 1364 #size-cells = <1>; 1365 ranges = <0x0 0x26000 0x2000>; 1366 1367 clocks { 1368 #address-cells = <1>; 1369 #size-cells = <0>; 1370 1371 icssg1_coreclk_mux: coreclk-mux@3c { 1372 reg = <0x3c>; 1373 #clock-cells = <0>; 1374 clocks = <&k3_clks 82 0>, /* icssg1_core_clk */ 1375 <&k3_clks 82 20>; /* icssg1_iclk */ 1376 assigned-clocks = <&icssg1_coreclk_mux>; 1377 assigned-clock-parents = <&k3_clks 82 20>; 1378 }; 1379 1380 icssg1_iepclk_mux: iepclk-mux@30 { 1381 reg = <0x30>; 1382 #clock-cells = <0>; 1383 clocks = <&k3_clks 82 3>, /* icssg1_iep_clk */ 1384 <&icssg1_coreclk_mux>; /* icssg1_coreclk_mux */ 1385 assigned-clocks = <&icssg1_iepclk_mux>; 1386 assigned-clock-parents = <&icssg1_coreclk_mux>; 1387 }; 1388 }; 1389 }; 1390 1391 icssg1_iep0: iep@2e000 { 1392 compatible = "ti,am654-icss-iep"; 1393 reg = <0x2e000 0x1000>; 1394 clocks = <&icssg1_iepclk_mux>; 1395 }; 1396 1397 icssg1_iep1: iep@2f000 { 1398 compatible = "ti,am654-icss-iep"; 1399 reg = <0x2f000 0x1000>; 1400 clocks = <&icssg1_iepclk_mux>; 1401 }; 1402 1403 icssg1_mii_rt: mii-rt@32000 { 1404 compatible = "ti,pruss-mii", "syscon"; 1405 reg = <0x32000 0x100>; 1406 }; 1407 1408 icssg1_mii_g_rt: mii-g-rt@33000 { 1409 compatible = "ti,pruss-mii-g", "syscon"; 1410 reg = <0x33000 0x1000>; 1411 }; 1412 1413 icssg1_intc: interrupt-controller@20000 { 1414 compatible = "ti,icssg-intc"; 1415 reg = <0x20000 0x2000>; 1416 interrupt-controller; 1417 #interrupt-cells = <3>; 1418 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1419 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1420 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1421 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1422 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1423 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 1424 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1426 interrupt-names = "host_intr0", "host_intr1", 1427 "host_intr2", "host_intr3", 1428 "host_intr4", "host_intr5", 1429 "host_intr6", "host_intr7"; 1430 }; 1431 1432 pru1_0: pru@34000 { 1433 compatible = "ti,am642-pru"; 1434 reg = <0x34000 0x4000>, 1435 <0x22000 0x100>, 1436 <0x22400 0x100>; 1437 reg-names = "iram", "control", "debug"; 1438 firmware-name = "am64x-pru1_0-fw"; 1439 }; 1440 1441 rtu1_0: rtu@4000 { 1442 compatible = "ti,am642-rtu"; 1443 reg = <0x4000 0x2000>, 1444 <0x23000 0x100>, 1445 <0x23400 0x100>; 1446 reg-names = "iram", "control", "debug"; 1447 firmware-name = "am64x-rtu1_0-fw"; 1448 }; 1449 1450 tx_pru1_0: txpru@a000 { 1451 compatible = "ti,am642-tx-pru"; 1452 reg = <0xa000 0x1800>, 1453 <0x25000 0x100>, 1454 <0x25400 0x100>; 1455 reg-names = "iram", "control", "debug"; 1456 firmware-name = "am64x-txpru1_0-fw"; 1457 }; 1458 1459 pru1_1: pru@38000 { 1460 compatible = "ti,am642-pru"; 1461 reg = <0x38000 0x4000>, 1462 <0x24000 0x100>, 1463 <0x24400 0x100>; 1464 reg-names = "iram", "control", "debug"; 1465 firmware-name = "am64x-pru1_1-fw"; 1466 }; 1467 1468 rtu1_1: rtu@6000 { 1469 compatible = "ti,am642-rtu"; 1470 reg = <0x6000 0x2000>, 1471 <0x23800 0x100>, 1472 <0x23c00 0x100>; 1473 reg-names = "iram", "control", "debug"; 1474 firmware-name = "am64x-rtu1_1-fw"; 1475 }; 1476 1477 tx_pru1_1: txpru@c000 { 1478 compatible = "ti,am642-tx-pru"; 1479 reg = <0xc000 0x1800>, 1480 <0x25800 0x100>, 1481 <0x25c00 0x100>; 1482 reg-names = "iram", "control", "debug"; 1483 firmware-name = "am64x-txpru1_1-fw"; 1484 }; 1485 1486 icssg1_mdio: mdio@32400 { 1487 compatible = "ti,davinci_mdio"; 1488 reg = <0x32400 0x100>; 1489 #address-cells = <1>; 1490 #size-cells = <0>; 1491 clocks = <&k3_clks 82 0>; 1492 clock-names = "fck"; 1493 bus_freq = <1000000>; 1494 status = "disabled"; 1495 }; 1496 }; 1497 1498 main_mcan0: can@20701000 { 1499 compatible = "bosch,m_can"; 1500 reg = <0x00 0x20701000 0x00 0x200>, 1501 <0x00 0x20708000 0x00 0x8000>; 1502 reg-names = "m_can", "message_ram"; 1503 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 1504 clocks = <&k3_clks 98 5>, <&k3_clks 98 0>; 1505 clock-names = "hclk", "cclk"; 1506 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1507 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1508 interrupt-names = "int0", "int1"; 1509 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1510 status = "disabled"; 1511 }; 1512 1513 main_mcan1: can@20711000 { 1514 compatible = "bosch,m_can"; 1515 reg = <0x00 0x20711000 0x00 0x200>, 1516 <0x00 0x20718000 0x00 0x8000>; 1517 reg-names = "m_can", "message_ram"; 1518 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 1519 clocks = <&k3_clks 99 5>, <&k3_clks 99 0>; 1520 clock-names = "hclk", "cclk"; 1521 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1523 interrupt-names = "int0", "int1"; 1524 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1525 status = "disabled"; 1526 }; 1527 1528 crypto: crypto@40900000 { 1529 compatible = "ti,am64-sa2ul"; 1530 reg = <0x00 0x40900000 0x00 0x1200>; 1531 power-domains = <&k3_pds 133 TI_SCI_PD_SHARED>; 1532 #address-cells = <2>; 1533 #size-cells = <2>; 1534 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; 1535 dmas = <&main_pktdma 0xc001 0>, <&main_pktdma 0x4002 0>, 1536 <&main_pktdma 0x4003 0>; 1537 dma-names = "tx", "rx1", "rx2"; 1538 1539 rng: rng@40910000 { 1540 compatible = "inside-secure,safexcel-eip76"; 1541 reg = <0x00 0x40910000 0x00 0x7d>; 1542 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1543 status = "disabled"; /* Used by OP-TEE */ 1544 }; 1545 }; 1546 1547 gpmc0: memory-controller@3b000000 { 1548 compatible = "ti,am64-gpmc"; 1549 power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; 1550 clocks = <&k3_clks 80 0>; 1551 clock-names = "fck"; 1552 reg = <0x00 0x3b000000 0x00 0x400>, 1553 <0x00 0x50000000 0x00 0x8000000>; 1554 reg-names = "cfg", "data"; 1555 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1556 gpmc,num-cs = <3>; 1557 gpmc,num-waitpins = <2>; 1558 #address-cells = <2>; 1559 #size-cells = <1>; 1560 interrupt-controller; 1561 #interrupt-cells = <2>; 1562 gpio-controller; 1563 #gpio-cells = <2>; 1564 status = "disabled"; 1565 }; 1566 1567 elm0: ecc@25010000 { 1568 compatible = "ti,am64-elm"; 1569 reg = <0x00 0x25010000 0x00 0x2000>; 1570 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 1571 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; 1572 clocks = <&k3_clks 54 0>; 1573 clock-names = "fck"; 1574 status = "disabled"; 1575 }; 1576 1577 main_vtm0: temperature-sensor@b00000 { 1578 compatible = "ti,j7200-vtm"; 1579 reg = <0x00 0xb00000 0x00 0x400>, 1580 <0x00 0xb01000 0x00 0x400>; 1581 power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>; 1582 #thermal-sensor-cells = <1>; 1583 }; 1584}; 1585