1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree file for the AM62P5 SoC family (quad core) 4 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 * TRM: https://www.ti.com/lit/pdf/spruj83 7 */ 8 9/dts-v1/; 10 11#include "k3-am62p.dtsi" 12 13/ { 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu-map { 19 cluster0: cluster0 { 20 core0 { 21 cpu = <&cpu0>; 22 }; 23 24 core1 { 25 cpu = <&cpu1>; 26 }; 27 28 core2 { 29 cpu = <&cpu2>; 30 }; 31 32 core3 { 33 cpu = <&cpu3>; 34 }; 35 }; 36 }; 37 38 cpu0: cpu@0 { 39 compatible = "arm,cortex-a53"; 40 reg = <0x000>; 41 device_type = "cpu"; 42 enable-method = "psci"; 43 i-cache-size = <0x8000>; 44 i-cache-line-size = <64>; 45 i-cache-sets = <256>; 46 d-cache-size = <0x8000>; 47 d-cache-line-size = <64>; 48 d-cache-sets = <128>; 49 next-level-cache = <&l2_0>; 50 operating-points-v2 = <&a53_opp_table>; 51 clocks = <&k3_clks 135 0>; 52 }; 53 54 cpu1: cpu@1 { 55 compatible = "arm,cortex-a53"; 56 reg = <0x001>; 57 device_type = "cpu"; 58 enable-method = "psci"; 59 i-cache-size = <0x8000>; 60 i-cache-line-size = <64>; 61 i-cache-sets = <256>; 62 d-cache-size = <0x8000>; 63 d-cache-line-size = <64>; 64 d-cache-sets = <128>; 65 next-level-cache = <&l2_0>; 66 operating-points-v2 = <&a53_opp_table>; 67 clocks = <&k3_clks 136 0>; 68 }; 69 70 cpu2: cpu@2 { 71 compatible = "arm,cortex-a53"; 72 reg = <0x002>; 73 device_type = "cpu"; 74 enable-method = "psci"; 75 i-cache-size = <0x8000>; 76 i-cache-line-size = <64>; 77 i-cache-sets = <256>; 78 d-cache-size = <0x8000>; 79 d-cache-line-size = <64>; 80 d-cache-sets = <128>; 81 next-level-cache = <&l2_0>; 82 operating-points-v2 = <&a53_opp_table>; 83 clocks = <&k3_clks 137 0>; 84 }; 85 86 cpu3: cpu@3 { 87 compatible = "arm,cortex-a53"; 88 reg = <0x003>; 89 device_type = "cpu"; 90 enable-method = "psci"; 91 i-cache-size = <0x8000>; 92 i-cache-line-size = <64>; 93 i-cache-sets = <256>; 94 d-cache-size = <0x8000>; 95 d-cache-line-size = <64>; 96 d-cache-sets = <128>; 97 next-level-cache = <&l2_0>; 98 operating-points-v2 = <&a53_opp_table>; 99 clocks = <&k3_clks 138 0>; 100 }; 101 }; 102 103 a53_opp_table: opp-table { 104 compatible = "operating-points-v2-ti-cpu"; 105 opp-shared; 106 syscon = <&opp_efuse_table>; 107 108 opp-200000000 { 109 opp-hz = /bits/ 64 <200000000>; 110 opp-supported-hw = <0x01 0x0007>; 111 clock-latency-ns = <6000000>; 112 }; 113 114 opp-400000000 { 115 opp-hz = /bits/ 64 <400000000>; 116 opp-supported-hw = <0x01 0x0007>; 117 clock-latency-ns = <6000000>; 118 }; 119 120 opp-600000000 { 121 opp-hz = /bits/ 64 <600000000>; 122 opp-supported-hw = <0x01 0x0007>; 123 clock-latency-ns = <6000000>; 124 }; 125 126 opp-800000000 { 127 opp-hz = /bits/ 64 <800000000>; 128 opp-supported-hw = <0x01 0x0007>; 129 clock-latency-ns = <6000000>; 130 }; 131 132 opp-1000000000 { 133 opp-hz = /bits/ 64 <1000000000>; 134 opp-supported-hw = <0x01 0x0006>; 135 clock-latency-ns = <6000000>; 136 }; 137 138 opp-1250000000 { 139 opp-hz = /bits/ 64 <1250000000>; 140 opp-supported-hw = <0x01 0x0004>; 141 clock-latency-ns = <6000000>; 142 opp-suspend; 143 }; 144 }; 145 146 l2_0: l2-cache0 { 147 compatible = "cache"; 148 cache-unified; 149 cache-level = <2>; 150 cache-size = <0x80000>; 151 cache-line-size = <64>; 152 cache-sets = <512>; 153 }; 154}; 155