1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree file for the AM62P5 SoC family (quad core) 4 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 * TRM: https://www.ti.com/lit/pdf/spruj83 7 */ 8 9/dts-v1/; 10 11#include "k3-am62p.dtsi" 12 13/ { 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu-map { 19 cluster0: cluster0 { 20 core0 { 21 cpu = <&cpu0>; 22 }; 23 24 core1 { 25 cpu = <&cpu1>; 26 }; 27 28 core2 { 29 cpu = <&cpu2>; 30 }; 31 32 core3 { 33 cpu = <&cpu3>; 34 }; 35 }; 36 }; 37 38 cpu0: cpu@0 { 39 compatible = "arm,cortex-a53"; 40 reg = <0x000>; 41 device_type = "cpu"; 42 enable-method = "psci"; 43 i-cache-size = <0x8000>; 44 i-cache-line-size = <64>; 45 i-cache-sets = <256>; 46 d-cache-size = <0x8000>; 47 d-cache-line-size = <64>; 48 d-cache-sets = <128>; 49 next-level-cache = <&l2_0>; 50 clocks = <&k3_clks 135 0>; 51 }; 52 53 cpu1: cpu@1 { 54 compatible = "arm,cortex-a53"; 55 reg = <0x001>; 56 device_type = "cpu"; 57 enable-method = "psci"; 58 i-cache-size = <0x8000>; 59 i-cache-line-size = <64>; 60 i-cache-sets = <256>; 61 d-cache-size = <0x8000>; 62 d-cache-line-size = <64>; 63 d-cache-sets = <128>; 64 next-level-cache = <&l2_0>; 65 clocks = <&k3_clks 136 0>; 66 }; 67 68 cpu2: cpu@2 { 69 compatible = "arm,cortex-a53"; 70 reg = <0x002>; 71 device_type = "cpu"; 72 enable-method = "psci"; 73 i-cache-size = <0x8000>; 74 i-cache-line-size = <64>; 75 i-cache-sets = <256>; 76 d-cache-size = <0x8000>; 77 d-cache-line-size = <64>; 78 d-cache-sets = <128>; 79 next-level-cache = <&l2_0>; 80 clocks = <&k3_clks 137 0>; 81 }; 82 83 cpu3: cpu@3 { 84 compatible = "arm,cortex-a53"; 85 reg = <0x003>; 86 device_type = "cpu"; 87 enable-method = "psci"; 88 i-cache-size = <0x8000>; 89 i-cache-line-size = <64>; 90 i-cache-sets = <256>; 91 d-cache-size = <0x8000>; 92 d-cache-line-size = <64>; 93 d-cache-sets = <128>; 94 next-level-cache = <&l2_0>; 95 clocks = <&k3_clks 138 0>; 96 }; 97 }; 98 99 l2_0: l2-cache0 { 100 compatible = "cache"; 101 cache-unified; 102 cache-level = <2>; 103 cache-size = <0x80000>; 104 cache-line-size = <64>; 105 cache-sets = <512>; 106 }; 107}; 108