1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree file for the AM62P main domain peripherals 4 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ 5 */ 6 7&cbass_main { 8 oc_sram: sram@70000000 { 9 compatible = "mmio-sram"; 10 reg = <0x00 0x70000000 0x00 0x10000>; 11 #address-cells = <1>; 12 #size-cells = <1>; 13 ranges = <0x00 0x00 0x70000000 0x10000>; 14 }; 15 16 gic500: interrupt-controller@1800000 { 17 compatible = "arm,gic-v3"; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 ranges; 21 #interrupt-cells = <3>; 22 interrupt-controller; 23 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 24 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 25 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 26 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 27 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 28 /* 29 * vcpumntirq: 30 * virtual CPU interface maintenance interrupt 31 */ 32 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 33 34 gic_its: msi-controller@1820000 { 35 compatible = "arm,gic-v3-its"; 36 reg = <0x00 0x01820000 0x00 0x10000>; 37 socionext,synquacer-pre-its = <0x1000000 0x400000>; 38 msi-controller; 39 #msi-cells = <1>; 40 }; 41 }; 42 43 main_conf: bus@100000 { 44 compatible = "simple-bus"; 45 reg = <0x00 0x00100000 0x00 0x20000>; 46 #address-cells = <1>; 47 #size-cells = <1>; 48 ranges = <0x00 0x00 0x00100000 0x20000>; 49 50 phy_gmii_sel: phy@4044 { 51 compatible = "ti,am654-phy-gmii-sel"; 52 reg = <0x4044 0x8>; 53 #phy-cells = <1>; 54 }; 55 56 epwm_tbclk: clock-controller@4130 { 57 compatible = "ti,am62-epwm-tbclk"; 58 reg = <0x4130 0x4>; 59 #clock-cells = <1>; 60 }; 61 }; 62 63 dmss: bus@48000000 { 64 compatible = "simple-bus"; 65 #address-cells = <2>; 66 #size-cells = <2>; 67 dma-ranges; 68 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; 69 bootph-all; 70 71 ti,sci-dev-id = <25>; 72 73 secure_proxy_main: mailbox@4d000000 { 74 compatible = "ti,am654-secure-proxy"; 75 #mbox-cells = <1>; 76 reg-names = "target_data", "rt", "scfg"; 77 reg = <0x00 0x4d000000 0x00 0x80000>, 78 <0x00 0x4a600000 0x00 0x80000>, 79 <0x00 0x4a400000 0x00 0x80000>; 80 interrupt-names = "rx_012"; 81 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 82 bootph-all; 83 }; 84 85 inta_main_dmss: interrupt-controller@48000000 { 86 compatible = "ti,sci-inta"; 87 reg = <0x00 0x48000000 0x00 0x100000>; 88 #interrupt-cells = <0>; 89 interrupt-controller; 90 interrupt-parent = <&gic500>; 91 msi-controller; 92 ti,sci = <&dmsc>; 93 ti,sci-dev-id = <28>; 94 ti,interrupt-ranges = <5 69 35>; 95 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 96 }; 97 98 main_bcdma: dma-controller@485c0100 { 99 compatible = "ti,am64-dmss-bcdma"; 100 reg = <0x00 0x485c0100 0x00 0x100>, 101 <0x00 0x4c000000 0x00 0x20000>, 102 <0x00 0x4a820000 0x00 0x20000>, 103 <0x00 0x4aa40000 0x00 0x20000>, 104 <0x00 0x4bc00000 0x00 0x100000>, 105 <0x00 0x48600000 0x00 0x8000>, 106 <0x00 0x484a4000 0x00 0x2000>, 107 <0x00 0x484c2000 0x00 0x2000>, 108 <0x00 0x48420000 0x00 0x2000>; 109 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt", 110 "ring", "tchan", "rchan", "bchan"; 111 msi-parent = <&inta_main_dmss>; 112 #dma-cells = <3>; 113 114 ti,sci = <&dmsc>; 115 ti,sci-dev-id = <26>; 116 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 117 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 118 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 119 bootph-all; 120 }; 121 122 main_pktdma: dma-controller@485c0000 { 123 compatible = "ti,am64-dmss-pktdma"; 124 reg = <0x00 0x485c0000 0x00 0x100>, 125 <0x00 0x4a800000 0x00 0x20000>, 126 <0x00 0x4aa00000 0x00 0x40000>, 127 <0x00 0x4b800000 0x00 0x400000>, 128 <0x00 0x485e0000 0x00 0x10000>, 129 <0x00 0x484a0000 0x00 0x2000>, 130 <0x00 0x484c0000 0x00 0x2000>, 131 <0x00 0x48430000 0x00 0x1000>; 132 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", 133 "ring", "tchan", "rchan", "rflow"; 134 msi-parent = <&inta_main_dmss>; 135 #dma-cells = <2>; 136 bootph-all; 137 138 ti,sci = <&dmsc>; 139 ti,sci-dev-id = <30>; 140 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 141 <0x24>, /* CPSW_TX_CHAN */ 142 <0x25>, /* SAUL_TX_0_CHAN */ 143 <0x26>; /* SAUL_TX_1_CHAN */ 144 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 145 <0x11>, /* RING_CPSW_TX_CHAN */ 146 <0x12>, /* RING_SAUL_TX_0_CHAN */ 147 <0x13>; /* RING_SAUL_TX_1_CHAN */ 148 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 149 <0x2b>, /* CPSW_RX_CHAN */ 150 <0x2d>, /* SAUL_RX_0_CHAN */ 151 <0x2f>, /* SAUL_RX_1_CHAN */ 152 <0x31>, /* SAUL_RX_2_CHAN */ 153 <0x33>; /* SAUL_RX_3_CHAN */ 154 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 155 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 156 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 157 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ 158 }; 159 }; 160 161 dmss_csi: bus@4e000000 { 162 compatible = "simple-bus"; 163 ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x408000>; 164 #address-cells = <2>; 165 #size-cells = <2>; 166 dma-ranges; 167 ti,sci-dev-id = <198>; 168 169 inta_main_dmss_csi: interrupt-controller@4e400000 { 170 compatible = "ti,sci-inta"; 171 reg = <0x00 0x4e400000 0x00 0x8000>; 172 #interrupt-cells = <0>; 173 interrupt-controller; 174 interrupt-parent = <&gic500>; 175 msi-controller; 176 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 177 ti,sci = <&dmsc>; 178 ti,sci-dev-id = <200>; 179 ti,interrupt-ranges = <0 237 8>; 180 ti,unmapped-event-sources = <&main_bcdma_csi>; 181 }; 182 183 main_bcdma_csi: dma-controller@4e230000 { 184 compatible = "ti,am62a-dmss-bcdma-csirx"; 185 reg = <0x00 0x4e230000 0x00 0x100>, 186 <0x00 0x4e180000 0x00 0x8000>, 187 <0x00 0x4e100000 0x00 0x10000>; 188 reg-names = "gcfg", "rchanrt", "ringrt"; 189 #dma-cells = <3>; 190 msi-parent = <&inta_main_dmss_csi>; 191 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 192 ti,sci = <&dmsc>; 193 ti,sci-dev-id = <199>; 194 ti,sci-rm-range-rchan = <0x21>; 195 }; 196 }; 197 198 dmsc: system-controller@44043000 { 199 compatible = "ti,k2g-sci"; 200 ti,host-id = <12>; 201 mbox-names = "rx", "tx"; 202 mboxes = <&secure_proxy_main 12>, 203 <&secure_proxy_main 13>; 204 reg-names = "debug_messages"; 205 reg = <0x00 0x44043000 0x00 0xfe0>; 206 bootph-all; 207 208 k3_pds: power-controller { 209 compatible = "ti,sci-pm-domain"; 210 #power-domain-cells = <2>; 211 bootph-all; 212 }; 213 214 k3_clks: clock-controller { 215 compatible = "ti,k2g-sci-clk"; 216 #clock-cells = <2>; 217 bootph-all; 218 }; 219 220 k3_reset: reset-controller { 221 compatible = "ti,sci-reset"; 222 #reset-cells = <2>; 223 bootph-all; 224 }; 225 }; 226 227 crypto: crypto@40900000 { 228 compatible = "ti,am62-sa3ul"; 229 reg = <0x00 0x40900000 0x00 0x1200>; 230 #address-cells = <2>; 231 #size-cells = <2>; 232 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; 233 234 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, 235 <&main_pktdma 0x7507 0>; 236 dma-names = "tx", "rx1", "rx2"; 237 }; 238 239 secure_proxy_sa3: mailbox@43600000 { 240 compatible = "ti,am654-secure-proxy"; 241 #mbox-cells = <1>; 242 reg-names = "target_data", "rt", "scfg"; 243 reg = <0x00 0x43600000 0x00 0x10000>, 244 <0x00 0x44880000 0x00 0x20000>, 245 <0x00 0x44860000 0x00 0x20000>; 246 /* 247 * Marked Disabled: 248 * Node is incomplete as it is meant for bootloaders and 249 * firmware on non-MPU processors 250 */ 251 status = "disabled"; 252 bootph-all; 253 }; 254 255 main_pmx0: pinctrl@f4000 { 256 compatible = "pinctrl-single"; 257 reg = <0x00 0xf4000 0x00 0x2ac>; 258 #pinctrl-cells = <1>; 259 pinctrl-single,register-width = <32>; 260 pinctrl-single,function-mask = <0xffffffff>; 261 bootph-all; 262 }; 263 264 main_esm: esm@420000 { 265 compatible = "ti,j721e-esm"; 266 reg = <0x00 0x420000 0x00 0x1000>; 267 ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>; 268 bootph-pre-ram; 269 }; 270 271 main_timer0: timer@2400000 { 272 compatible = "ti,am654-timer"; 273 reg = <0x00 0x2400000 0x00 0x400>; 274 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&k3_clks 36 2>; 276 clock-names = "fck"; 277 assigned-clocks = <&k3_clks 36 2>; 278 assigned-clock-parents = <&k3_clks 36 3>; 279 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 280 ti,timer-pwm; 281 bootph-all; 282 }; 283 284 main_timer1: timer@2410000 { 285 compatible = "ti,am654-timer"; 286 reg = <0x00 0x2410000 0x00 0x400>; 287 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 288 clocks = <&k3_clks 37 2>; 289 clock-names = "fck"; 290 assigned-clocks = <&k3_clks 37 2>; 291 assigned-clock-parents = <&k3_clks 37 3>; 292 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 293 ti,timer-pwm; 294 }; 295 296 main_timer2: timer@2420000 { 297 compatible = "ti,am654-timer"; 298 reg = <0x00 0x2420000 0x00 0x400>; 299 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 300 clocks = <&k3_clks 38 2>; 301 clock-names = "fck"; 302 assigned-clocks = <&k3_clks 38 2>; 303 assigned-clock-parents = <&k3_clks 38 3>; 304 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 305 ti,timer-pwm; 306 }; 307 308 main_timer3: timer@2430000 { 309 compatible = "ti,am654-timer"; 310 reg = <0x00 0x2430000 0x00 0x400>; 311 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&k3_clks 39 2>; 313 clock-names = "fck"; 314 assigned-clocks = <&k3_clks 39 2>; 315 assigned-clock-parents = <&k3_clks 39 3>; 316 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 317 ti,timer-pwm; 318 }; 319 320 main_timer4: timer@2440000 { 321 compatible = "ti,am654-timer"; 322 reg = <0x00 0x2440000 0x00 0x400>; 323 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&k3_clks 40 2>; 325 clock-names = "fck"; 326 assigned-clocks = <&k3_clks 40 2>; 327 assigned-clock-parents = <&k3_clks 40 3>; 328 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 329 ti,timer-pwm; 330 }; 331 332 main_timer5: timer@2450000 { 333 compatible = "ti,am654-timer"; 334 reg = <0x00 0x2450000 0x00 0x400>; 335 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&k3_clks 41 2>; 337 clock-names = "fck"; 338 assigned-clocks = <&k3_clks 41 2>; 339 assigned-clock-parents = <&k3_clks 41 3>; 340 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 341 ti,timer-pwm; 342 }; 343 344 main_timer6: timer@2460000 { 345 compatible = "ti,am654-timer"; 346 reg = <0x00 0x2460000 0x00 0x400>; 347 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&k3_clks 42 2>; 349 clock-names = "fck"; 350 assigned-clocks = <&k3_clks 42 2>; 351 assigned-clock-parents = <&k3_clks 42 3>; 352 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 353 ti,timer-pwm; 354 }; 355 356 main_timer7: timer@2470000 { 357 compatible = "ti,am654-timer"; 358 reg = <0x00 0x2470000 0x00 0x400>; 359 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&k3_clks 43 2>; 361 clock-names = "fck"; 362 assigned-clocks = <&k3_clks 43 2>; 363 assigned-clock-parents = <&k3_clks 43 3>; 364 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 365 ti,timer-pwm; 366 }; 367 368 main_uart0: serial@2800000 { 369 compatible = "ti,am64-uart", "ti,am654-uart"; 370 reg = <0x00 0x02800000 0x00 0x100>; 371 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 372 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 373 clocks = <&k3_clks 146 0>; 374 clock-names = "fclk"; 375 status = "disabled"; 376 }; 377 378 main_uart1: serial@2810000 { 379 compatible = "ti,am64-uart", "ti,am654-uart"; 380 reg = <0x00 0x02810000 0x00 0x100>; 381 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 382 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 383 clocks = <&k3_clks 152 0>; 384 clock-names = "fclk"; 385 status = "disabled"; 386 }; 387 388 main_uart2: serial@2820000 { 389 compatible = "ti,am64-uart", "ti,am654-uart"; 390 reg = <0x00 0x02820000 0x00 0x100>; 391 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 392 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 393 clocks = <&k3_clks 153 0>; 394 clock-names = "fclk"; 395 status = "disabled"; 396 }; 397 398 main_uart3: serial@2830000 { 399 compatible = "ti,am64-uart", "ti,am654-uart"; 400 reg = <0x00 0x02830000 0x00 0x100>; 401 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 402 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 403 clocks = <&k3_clks 154 0>; 404 clock-names = "fclk"; 405 status = "disabled"; 406 }; 407 408 main_uart4: serial@2840000 { 409 compatible = "ti,am64-uart", "ti,am654-uart"; 410 reg = <0x00 0x02840000 0x00 0x100>; 411 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 412 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 413 clocks = <&k3_clks 155 0>; 414 clock-names = "fclk"; 415 status = "disabled"; 416 }; 417 418 main_uart5: serial@2850000 { 419 compatible = "ti,am64-uart", "ti,am654-uart"; 420 reg = <0x00 0x02850000 0x00 0x100>; 421 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 422 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 423 clocks = <&k3_clks 156 0>; 424 clock-names = "fclk"; 425 status = "disabled"; 426 }; 427 428 main_uart6: serial@2860000 { 429 compatible = "ti,am64-uart", "ti,am654-uart"; 430 reg = <0x00 0x02860000 0x00 0x100>; 431 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 432 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 433 clocks = <&k3_clks 158 0>; 434 clock-names = "fclk"; 435 status = "disabled"; 436 }; 437 438 main_i2c0: i2c@20000000 { 439 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 440 reg = <0x00 0x20000000 0x00 0x100>; 441 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 445 clocks = <&k3_clks 102 2>; 446 clock-names = "fck"; 447 status = "disabled"; 448 }; 449 450 main_i2c1: i2c@20010000 { 451 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 452 reg = <0x00 0x20010000 0x00 0x100>; 453 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 454 #address-cells = <1>; 455 #size-cells = <0>; 456 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 457 clocks = <&k3_clks 103 2>; 458 clock-names = "fck"; 459 status = "disabled"; 460 }; 461 462 main_i2c2: i2c@20020000 { 463 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 464 reg = <0x00 0x20020000 0x00 0x100>; 465 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 469 clocks = <&k3_clks 104 2>; 470 clock-names = "fck"; 471 status = "disabled"; 472 }; 473 474 main_i2c3: i2c@20030000 { 475 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 476 reg = <0x00 0x20030000 0x00 0x100>; 477 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 478 #address-cells = <1>; 479 #size-cells = <0>; 480 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 481 clocks = <&k3_clks 105 2>; 482 clock-names = "fck"; 483 status = "disabled"; 484 }; 485 486 main_spi0: spi@20100000 { 487 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 488 reg = <0x00 0x20100000 0x00 0x400>; 489 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 493 clocks = <&k3_clks 141 0>; 494 status = "disabled"; 495 }; 496 497 main_spi1: spi@20110000 { 498 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 499 reg = <0x00 0x20110000 0x00 0x400>; 500 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 501 #address-cells = <1>; 502 #size-cells = <0>; 503 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 504 clocks = <&k3_clks 142 0>; 505 status = "disabled"; 506 }; 507 508 main_spi2: spi@20120000 { 509 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 510 reg = <0x00 0x20120000 0x00 0x400>; 511 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 512 #address-cells = <1>; 513 #size-cells = <0>; 514 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 515 clocks = <&k3_clks 143 0>; 516 status = "disabled"; 517 }; 518 519 main_gpio_intr: interrupt-controller@a00000 { 520 compatible = "ti,sci-intr"; 521 reg = <0x00 0x00a00000 0x00 0x800>; 522 ti,intr-trigger-type = <1>; 523 interrupt-controller; 524 interrupt-parent = <&gic500>; 525 #interrupt-cells = <1>; 526 ti,sci = <&dmsc>; 527 ti,sci-dev-id = <3>; 528 ti,interrupt-ranges = <0 32 16>; 529 }; 530 531 main_gpio0: gpio@600000 { 532 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 533 reg = <0x00 0x00600000 0x00 0x100>; 534 gpio-controller; 535 #gpio-cells = <2>; 536 interrupt-parent = <&main_gpio_intr>; 537 interrupts = <190>, <191>, <192>, 538 <193>, <194>, <195>; 539 interrupt-controller; 540 #interrupt-cells = <2>; 541 ti,ngpio = <92>; 542 ti,davinci-gpio-unbanked = <0>; 543 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 544 clocks = <&k3_clks 77 0>; 545 clock-names = "gpio"; 546 }; 547 548 main_gpio1: gpio@601000 { 549 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 550 reg = <0x00 0x00601000 0x00 0x100>; 551 gpio-controller; 552 #gpio-cells = <2>; 553 interrupt-parent = <&main_gpio_intr>; 554 interrupts = <180>, <181>, <182>, 555 <183>, <184>, <185>; 556 interrupt-controller; 557 #interrupt-cells = <2>; 558 ti,ngpio = <52>; 559 ti,davinci-gpio-unbanked = <0>; 560 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 561 clocks = <&k3_clks 78 0>; 562 clock-names = "gpio"; 563 }; 564 565 sdhci0: mmc@fa10000 { 566 compatible = "ti,am64-sdhci-8bit"; 567 reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>; 568 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 569 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 570 clocks = <&k3_clks 57 1>, <&k3_clks 57 2>; 571 clock-names = "clk_ahb", "clk_xin"; 572 assigned-clocks = <&k3_clks 57 2>; 573 assigned-clock-parents = <&k3_clks 57 4>; 574 bus-width = <8>; 575 mmc-ddr-1_8v; 576 mmc-hs200-1_8v; 577 mmc-hs400-1_8v; 578 ti,clkbuf-sel = <0x7>; 579 ti,strobe-sel = <0x77>; 580 ti,trm-icp = <0x8>; 581 ti,otap-del-sel-legacy = <0x1>; 582 ti,otap-del-sel-mmc-hs = <0x1>; 583 ti,otap-del-sel-ddr52 = <0x6>; 584 ti,otap-del-sel-hs200 = <0x8>; 585 ti,otap-del-sel-hs400 = <0x5>; 586 ti,itap-del-sel-legacy = <0x10>; 587 ti,itap-del-sel-mmc-hs = <0xa>; 588 ti,itap-del-sel-ddr52 = <0x3>; 589 status = "disabled"; 590 }; 591 592 sdhci1: mmc@fa00000 { 593 compatible = "ti,am62-sdhci"; 594 reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>; 595 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 596 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 597 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; 598 clock-names = "clk_ahb", "clk_xin"; 599 bus-width = <4>; 600 ti,clkbuf-sel = <0x7>; 601 ti,otap-del-sel-legacy = <0x0>; 602 ti,otap-del-sel-sd-hs = <0x0>; 603 ti,otap-del-sel-sdr12 = <0xf>; 604 ti,otap-del-sel-sdr25 = <0xf>; 605 ti,otap-del-sel-sdr50 = <0xc>; 606 ti,otap-del-sel-ddr50 = <0x9>; 607 ti,otap-del-sel-sdr104 = <0x6>; 608 ti,itap-del-sel-legacy = <0x0>; 609 ti,itap-del-sel-sd-hs = <0x0>; 610 ti,itap-del-sel-sdr12 = <0x0>; 611 ti,itap-del-sel-sdr25 = <0x0>; 612 status = "disabled"; 613 }; 614 615 sdhci2: mmc@fa20000 { 616 compatible = "ti,am62-sdhci"; 617 reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>; 618 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 619 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 620 clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; 621 clock-names = "clk_ahb", "clk_xin"; 622 bus-width = <4>; 623 ti,clkbuf-sel = <0x7>; 624 ti,otap-del-sel-legacy = <0x0>; 625 ti,otap-del-sel-sd-hs = <0x0>; 626 ti,otap-del-sel-sdr12 = <0xf>; 627 ti,otap-del-sel-sdr25 = <0xf>; 628 ti,otap-del-sel-sdr50 = <0xc>; 629 ti,otap-del-sel-ddr50 = <0x9>; 630 ti,otap-del-sel-sdr104 = <0x6>; 631 ti,itap-del-sel-legacy = <0x0>; 632 ti,itap-del-sel-sd-hs = <0x0>; 633 ti,itap-del-sel-sdr12 = <0x0>; 634 ti,itap-del-sel-sdr25 = <0x0>; 635 status = "disabled"; 636 }; 637 638 fss: bus@fc00000 { 639 compatible = "simple-bus"; 640 reg = <0x00 0x0fc00000 0x00 0x70000>; 641 #address-cells = <2>; 642 #size-cells = <2>; 643 ranges; 644 645 ospi0: spi@fc40000 { 646 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 647 reg = <0x00 0x0fc40000 0x00 0x100>, 648 <0x05 0x00000000 0x01 0x00000000>; 649 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 650 cdns,fifo-depth = <256>; 651 cdns,fifo-width = <4>; 652 cdns,trigger-address = <0x0>; 653 clocks = <&k3_clks 75 7>; 654 assigned-clocks = <&k3_clks 75 7>; 655 assigned-clock-parents = <&k3_clks 75 8>; 656 assigned-clock-rates = <166666666>; 657 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 658 #address-cells = <1>; 659 #size-cells = <0>; 660 status = "disabled"; 661 }; 662 }; 663 664 cpsw3g: ethernet@8000000 { 665 compatible = "ti,am642-cpsw-nuss"; 666 #address-cells = <2>; 667 #size-cells = <2>; 668 reg = <0x00 0x08000000 0x00 0x200000>; 669 reg-names = "cpsw_nuss"; 670 ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>; 671 clocks = <&k3_clks 13 0>; 672 assigned-clocks = <&k3_clks 13 3>; 673 assigned-clock-parents = <&k3_clks 13 11>; 674 clock-names = "fck"; 675 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 676 677 dmas = <&main_pktdma 0xc600 15>, 678 <&main_pktdma 0xc601 15>, 679 <&main_pktdma 0xc602 15>, 680 <&main_pktdma 0xc603 15>, 681 <&main_pktdma 0xc604 15>, 682 <&main_pktdma 0xc605 15>, 683 <&main_pktdma 0xc606 15>, 684 <&main_pktdma 0xc607 15>, 685 <&main_pktdma 0x4600 15>; 686 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 687 "tx7", "rx"; 688 689 ethernet-ports { 690 #address-cells = <1>; 691 #size-cells = <0>; 692 693 cpsw_port1: port@1 { 694 reg = <1>; 695 ti,mac-only; 696 label = "port1"; 697 phys = <&phy_gmii_sel 1>; 698 mac-address = [00 00 00 00 00 00]; 699 }; 700 701 cpsw_port2: port@2 { 702 reg = <2>; 703 ti,mac-only; 704 label = "port2"; 705 phys = <&phy_gmii_sel 2>; 706 mac-address = [00 00 00 00 00 00]; 707 }; 708 }; 709 710 cpsw3g_mdio: mdio@f00 { 711 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 712 reg = <0x00 0xf00 0x00 0x100>; 713 #address-cells = <1>; 714 #size-cells = <0>; 715 clocks = <&k3_clks 13 0>; 716 clock-names = "fck"; 717 bus_freq = <1000000>; 718 status = "disabled"; 719 }; 720 721 cpts@3d000 { 722 compatible = "ti,j721e-cpts"; 723 reg = <0x00 0x3d000 0x00 0x400>; 724 clocks = <&k3_clks 13 3>; 725 clock-names = "cpts"; 726 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 727 interrupt-names = "cpts"; 728 ti,cpts-ext-ts-inputs = <4>; 729 ti,cpts-periodic-outputs = <2>; 730 }; 731 }; 732 733 hwspinlock: spinlock@2a000000 { 734 compatible = "ti,am64-hwspinlock"; 735 reg = <0x00 0x2a000000 0x00 0x1000>; 736 #hwlock-cells = <1>; 737 }; 738 739 mailbox0_cluster0: mailbox@29000000 { 740 compatible = "ti,am64-mailbox"; 741 reg = <0x00 0x29000000 0x00 0x200>; 742 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 743 #mbox-cells = <1>; 744 ti,mbox-num-users = <4>; 745 ti,mbox-num-fifos = <16>; 746 }; 747 748 mailbox0_cluster1: mailbox@29010000 { 749 compatible = "ti,am64-mailbox"; 750 reg = <0x00 0x29010000 0x00 0x200>; 751 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 752 #mbox-cells = <1>; 753 ti,mbox-num-users = <4>; 754 ti,mbox-num-fifos = <16>; 755 }; 756 757 mailbox0_cluster2: mailbox@29020000 { 758 compatible = "ti,am64-mailbox"; 759 reg = <0x00 0x29020000 0x00 0x200>; 760 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 761 #mbox-cells = <1>; 762 ti,mbox-num-users = <4>; 763 ti,mbox-num-fifos = <16>; 764 }; 765 766 mailbox0_cluster3: mailbox@29030000 { 767 compatible = "ti,am64-mailbox"; 768 reg = <0x00 0x29030000 0x00 0x200>; 769 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 770 #mbox-cells = <1>; 771 ti,mbox-num-users = <4>; 772 ti,mbox-num-fifos = <16>; 773 }; 774 775 ecap0: pwm@23100000 { 776 compatible = "ti,am3352-ecap"; 777 #pwm-cells = <3>; 778 reg = <0x00 0x23100000 0x00 0x100>; 779 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 780 clocks = <&k3_clks 51 0>; 781 clock-names = "fck"; 782 status = "disabled"; 783 }; 784 785 ecap1: pwm@23110000 { 786 compatible = "ti,am3352-ecap"; 787 #pwm-cells = <3>; 788 reg = <0x00 0x23110000 0x00 0x100>; 789 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 790 clocks = <&k3_clks 52 0>; 791 clock-names = "fck"; 792 status = "disabled"; 793 }; 794 795 ecap2: pwm@23120000 { 796 compatible = "ti,am3352-ecap"; 797 #pwm-cells = <3>; 798 reg = <0x00 0x23120000 0x00 0x100>; 799 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 800 clocks = <&k3_clks 53 0>; 801 clock-names = "fck"; 802 status = "disabled"; 803 }; 804 805 main_mcan0: can@20701000 { 806 compatible = "bosch,m_can"; 807 reg = <0x00 0x20701000 0x00 0x200>, 808 <0x00 0x20708000 0x00 0x8000>; 809 reg-names = "m_can", "message_ram"; 810 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 811 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; 812 clock-names = "hclk", "cclk"; 813 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 815 interrupt-names = "int0", "int1"; 816 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 817 status = "disabled"; 818 }; 819 820 main_mcan1: can@20711000 { 821 compatible = "bosch,m_can"; 822 reg = <0x00 0x20711000 0x00 0x200>, 823 <0x00 0x20718000 0x00 0x8000>; 824 reg-names = "m_can", "message_ram"; 825 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 826 clocks = <&k3_clks 99 6>, <&k3_clks 99 1>; 827 clock-names = "hclk", "cclk"; 828 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 830 interrupt-names = "int0", "int1"; 831 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 832 status = "disabled"; 833 }; 834 835 main_rti0: watchdog@e000000 { 836 compatible = "ti,j7-rti-wdt"; 837 reg = <0x00 0x0e000000 0x00 0x100>; 838 clocks = <&k3_clks 125 0>; 839 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 840 assigned-clocks = <&k3_clks 125 0>; 841 assigned-clock-parents = <&k3_clks 125 2>; 842 }; 843 844 main_rti1: watchdog@e010000 { 845 compatible = "ti,j7-rti-wdt"; 846 reg = <0x00 0x0e010000 0x00 0x100>; 847 clocks = <&k3_clks 126 0>; 848 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; 849 assigned-clocks = <&k3_clks 126 0>; 850 assigned-clock-parents = <&k3_clks 126 2>; 851 }; 852 853 main_rti2: watchdog@e020000 { 854 compatible = "ti,j7-rti-wdt"; 855 reg = <0x00 0x0e020000 0x00 0x100>; 856 clocks = <&k3_clks 127 0>; 857 power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; 858 assigned-clocks = <&k3_clks 127 0>; 859 assigned-clock-parents = <&k3_clks 127 2>; 860 }; 861 862 main_rti3: watchdog@e030000 { 863 compatible = "ti,j7-rti-wdt"; 864 reg = <0x00 0x0e030000 0x00 0x100>; 865 clocks = <&k3_clks 128 0>; 866 power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; 867 assigned-clocks = <&k3_clks 128 0>; 868 assigned-clock-parents = <&k3_clks 128 2>; 869 }; 870 871 main_rti15: watchdog@e0f0000 { 872 compatible = "ti,j7-rti-wdt"; 873 reg = <0x00 0x0e0f0000 0x00 0x100>; 874 clocks = <&k3_clks 130 0>; 875 power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>; 876 assigned-clocks = <&k3_clks 130 0>; 877 assigned-clock-parents = <&k3_clks 130 2>; 878 }; 879 880 epwm0: pwm@23000000 { 881 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 882 #pwm-cells = <3>; 883 reg = <0x00 0x23000000 0x00 0x100>; 884 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 885 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 886 clock-names = "tbclk", "fck"; 887 status = "disabled"; 888 }; 889 890 epwm1: pwm@23010000 { 891 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 892 #pwm-cells = <3>; 893 reg = <0x00 0x23010000 0x00 0x100>; 894 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 895 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 896 clock-names = "tbclk", "fck"; 897 status = "disabled"; 898 }; 899 900 epwm2: pwm@23020000 { 901 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 902 #pwm-cells = <3>; 903 reg = <0x00 0x23020000 0x00 0x100>; 904 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 905 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 906 clock-names = "tbclk", "fck"; 907 status = "disabled"; 908 }; 909 910 mcasp0: audio-controller@2b00000 { 911 compatible = "ti,am33xx-mcasp-audio"; 912 reg = <0x00 0x02b00000 0x00 0x2000>, 913 <0x00 0x02b08000 0x00 0x400>; 914 reg-names = "mpu", "dat"; 915 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, 916 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 917 interrupt-names = "tx", "rx"; 918 919 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; 920 dma-names = "tx", "rx"; 921 922 clocks = <&k3_clks 190 0>; 923 clock-names = "fck"; 924 assigned-clocks = <&k3_clks 190 0>; 925 assigned-clock-parents = <&k3_clks 190 2>; 926 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 927 status = "disabled"; 928 }; 929 930 mcasp1: audio-controller@2b10000 { 931 compatible = "ti,am33xx-mcasp-audio"; 932 reg = <0x00 0x02b10000 0x00 0x2000>, 933 <0x00 0x02b18000 0x00 0x400>; 934 reg-names = "mpu", "dat"; 935 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 937 interrupt-names = "tx", "rx"; 938 939 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; 940 dma-names = "tx", "rx"; 941 942 clocks = <&k3_clks 191 0>; 943 clock-names = "fck"; 944 assigned-clocks = <&k3_clks 191 0>; 945 assigned-clock-parents = <&k3_clks 191 2>; 946 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 947 status = "disabled"; 948 }; 949 950 mcasp2: audio-controller@2b20000 { 951 compatible = "ti,am33xx-mcasp-audio"; 952 reg = <0x00 0x02b20000 0x00 0x2000>, 953 <0x00 0x02b28000 0x00 0x400>; 954 reg-names = "mpu", "dat"; 955 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 957 interrupt-names = "tx", "rx"; 958 959 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; 960 dma-names = "tx", "rx"; 961 962 clocks = <&k3_clks 192 0>; 963 clock-names = "fck"; 964 assigned-clocks = <&k3_clks 192 0>; 965 assigned-clock-parents = <&k3_clks 192 2>; 966 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 967 status = "disabled"; 968 }; 969 970 ti_csi2rx0: ticsi2rx@30102000 { 971 compatible = "ti,j721e-csi2rx-shim"; 972 reg = <0x00 0x30102000 0x00 0x1000>; 973 ranges; 974 #address-cells = <2>; 975 #size-cells = <2>; 976 dmas = <&main_bcdma_csi 0 0x5000 0>; 977 dma-names = "rx0"; 978 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 979 status = "disabled"; 980 981 cdns_csi2rx0: csi-bridge@30101000 { 982 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 983 reg = <0x00 0x30101000 0x00 0x1000>; 984 clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, 985 <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; 986 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 987 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 988 phys = <&dphy0>; 989 phy-names = "dphy"; 990 991 ports { 992 #address-cells = <1>; 993 #size-cells = <0>; 994 995 csi0_port0: port@0 { 996 reg = <0>; 997 status = "disabled"; 998 }; 999 1000 csi0_port1: port@1 { 1001 reg = <1>; 1002 status = "disabled"; 1003 }; 1004 1005 csi0_port2: port@2 { 1006 reg = <2>; 1007 status = "disabled"; 1008 }; 1009 1010 csi0_port3: port@3 { 1011 reg = <3>; 1012 status = "disabled"; 1013 }; 1014 1015 csi0_port4: port@4 { 1016 reg = <4>; 1017 status = "disabled"; 1018 }; 1019 }; 1020 }; 1021 }; 1022 1023 dphy0: phy@30110000 { 1024 compatible = "cdns,dphy-rx"; 1025 reg = <0x00 0x30110000 0x00 0x1100>; 1026 #phy-cells = <0>; 1027 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1028 status = "disabled"; 1029 }; 1030 1031 vpu: video-codec@30210000 { 1032 compatible = "ti,j721s2-wave521c", "cnm,wave521c"; 1033 reg = <0x00 0x30210000 0x00 0x10000>; 1034 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1035 clocks = <&k3_clks 204 2>; 1036 power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; 1037 }; 1038}; 1039