1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree file for the MAIN domain peripherals shared by AM62P and J722S 4 * 5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 oc_sram: sram@70000000 { 10 compatible = "mmio-sram"; 11 #address-cells = <1>; 12 #size-cells = <1>; 13 }; 14 15 gic500: interrupt-controller@1800000 { 16 compatible = "arm,gic-v3"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 ranges; 20 #interrupt-cells = <3>; 21 interrupt-controller; 22 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 23 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 24 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 25 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 26 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 27 /* 28 * vcpumntirq: 29 * virtual CPU interface maintenance interrupt 30 */ 31 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 32 33 gic_its: msi-controller@1820000 { 34 compatible = "arm,gic-v3-its"; 35 reg = <0x00 0x01820000 0x00 0x10000>; 36 socionext,synquacer-pre-its = <0x1000000 0x400000>; 37 msi-controller; 38 #msi-cells = <1>; 39 }; 40 }; 41 42 main_conf: bus@100000 { 43 compatible = "simple-bus"; 44 reg = <0x00 0x00100000 0x00 0x20000>; 45 #address-cells = <1>; 46 #size-cells = <1>; 47 ranges = <0x00 0x00 0x00100000 0x20000>; 48 49 phy_gmii_sel: phy@4044 { 50 compatible = "ti,am654-phy-gmii-sel"; 51 reg = <0x4044 0x8>; 52 #phy-cells = <1>; 53 }; 54 55 epwm_tbclk: clock-controller@4130 { 56 compatible = "ti,am62-epwm-tbclk"; 57 reg = <0x4130 0x4>; 58 #clock-cells = <1>; 59 }; 60 }; 61 62 dmss: bus@48000000 { 63 compatible = "simple-bus"; 64 #address-cells = <2>; 65 #size-cells = <2>; 66 dma-ranges; 67 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; 68 bootph-all; 69 70 ti,sci-dev-id = <25>; 71 72 secure_proxy_main: mailbox@4d000000 { 73 compatible = "ti,am654-secure-proxy"; 74 #mbox-cells = <1>; 75 reg-names = "target_data", "rt", "scfg"; 76 reg = <0x00 0x4d000000 0x00 0x80000>, 77 <0x00 0x4a600000 0x00 0x80000>, 78 <0x00 0x4a400000 0x00 0x80000>; 79 interrupt-names = "rx_012"; 80 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 81 bootph-all; 82 }; 83 84 inta_main_dmss: interrupt-controller@48000000 { 85 compatible = "ti,sci-inta"; 86 reg = <0x00 0x48000000 0x00 0x100000>; 87 #interrupt-cells = <0>; 88 interrupt-controller; 89 interrupt-parent = <&gic500>; 90 msi-controller; 91 ti,sci = <&dmsc>; 92 ti,sci-dev-id = <28>; 93 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 94 }; 95 96 main_bcdma: dma-controller@485c0100 { 97 compatible = "ti,am64-dmss-bcdma"; 98 reg = <0x00 0x485c0100 0x00 0x100>, 99 <0x00 0x4c000000 0x00 0x20000>, 100 <0x00 0x4a820000 0x00 0x20000>, 101 <0x00 0x4aa40000 0x00 0x20000>, 102 <0x00 0x4bc00000 0x00 0x100000>, 103 <0x00 0x48600000 0x00 0x8000>, 104 <0x00 0x484a4000 0x00 0x2000>, 105 <0x00 0x484c2000 0x00 0x2000>, 106 <0x00 0x48420000 0x00 0x2000>; 107 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt", 108 "ring", "tchan", "rchan", "bchan"; 109 msi-parent = <&inta_main_dmss>; 110 #dma-cells = <3>; 111 112 ti,sci = <&dmsc>; 113 ti,sci-dev-id = <26>; 114 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 115 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 116 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 117 bootph-all; 118 }; 119 120 main_pktdma: dma-controller@485c0000 { 121 compatible = "ti,am64-dmss-pktdma"; 122 reg = <0x00 0x485c0000 0x00 0x100>, 123 <0x00 0x4a800000 0x00 0x20000>, 124 <0x00 0x4aa00000 0x00 0x20000>, 125 <0x00 0x4b800000 0x00 0x200000>, 126 <0x00 0x485e0000 0x00 0x10000>, 127 <0x00 0x484a0000 0x00 0x2000>, 128 <0x00 0x484c0000 0x00 0x2000>, 129 <0x00 0x48430000 0x00 0x1000>; 130 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", 131 "ring", "tchan", "rchan", "rflow"; 132 msi-parent = <&inta_main_dmss>; 133 #dma-cells = <2>; 134 bootph-all; 135 136 ti,sci = <&dmsc>; 137 ti,sci-dev-id = <30>; 138 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 139 <0x24>, /* CPSW_TX_CHAN */ 140 <0x25>, /* SAUL_TX_0_CHAN */ 141 <0x26>; /* SAUL_TX_1_CHAN */ 142 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 143 <0x11>, /* RING_CPSW_TX_CHAN */ 144 <0x12>, /* RING_SAUL_TX_0_CHAN */ 145 <0x13>; /* RING_SAUL_TX_1_CHAN */ 146 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 147 <0x2b>, /* CPSW_RX_CHAN */ 148 <0x2d>, /* SAUL_RX_0_CHAN */ 149 <0x2f>, /* SAUL_RX_1_CHAN */ 150 <0x31>, /* SAUL_RX_2_CHAN */ 151 <0x33>; /* SAUL_RX_3_CHAN */ 152 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 153 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 154 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 155 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ 156 }; 157 }; 158 159 dmss_csi: bus@4e000000 { 160 compatible = "simple-bus"; 161 ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x408000>; 162 #address-cells = <2>; 163 #size-cells = <2>; 164 dma-ranges; 165 ti,sci-dev-id = <198>; 166 167 inta_main_dmss_csi: interrupt-controller@4e400000 { 168 compatible = "ti,sci-inta"; 169 reg = <0x00 0x4e400000 0x00 0x8000>; 170 #interrupt-cells = <0>; 171 interrupt-controller; 172 interrupt-parent = <&gic500>; 173 msi-controller; 174 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 175 ti,sci = <&dmsc>; 176 ti,sci-dev-id = <200>; 177 ti,interrupt-ranges = <0 237 8>; 178 ti,unmapped-event-sources = <&main_bcdma_csi>; 179 }; 180 181 main_bcdma_csi: dma-controller@4e230000 { 182 compatible = "ti,am62a-dmss-bcdma-csirx"; 183 reg = <0x00 0x4e230000 0x00 0x100>, 184 <0x00 0x4e180000 0x00 0x8000>, 185 <0x00 0x4e100000 0x00 0x10000>; 186 reg-names = "gcfg", "rchanrt", "ringrt"; 187 #dma-cells = <3>; 188 msi-parent = <&inta_main_dmss_csi>; 189 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 190 ti,sci = <&dmsc>; 191 ti,sci-dev-id = <199>; 192 ti,sci-rm-range-rchan = <0x21>; 193 }; 194 }; 195 196 dmsc: system-controller@44043000 { 197 compatible = "ti,k2g-sci"; 198 ti,host-id = <12>; 199 mbox-names = "rx", "tx"; 200 mboxes = <&secure_proxy_main 12>, 201 <&secure_proxy_main 13>; 202 reg-names = "debug_messages"; 203 reg = <0x00 0x44043000 0x00 0xfe0>; 204 bootph-all; 205 206 k3_pds: power-controller { 207 compatible = "ti,sci-pm-domain"; 208 #power-domain-cells = <2>; 209 bootph-all; 210 }; 211 212 k3_clks: clock-controller { 213 compatible = "ti,k2g-sci-clk"; 214 #clock-cells = <2>; 215 bootph-all; 216 }; 217 218 k3_reset: reset-controller { 219 compatible = "ti,sci-reset"; 220 #reset-cells = <2>; 221 bootph-all; 222 }; 223 }; 224 225 crypto: crypto@40900000 { 226 compatible = "ti,am62-sa3ul"; 227 reg = <0x00 0x40900000 0x00 0x1200>; 228 #address-cells = <2>; 229 #size-cells = <2>; 230 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, 231 <&main_pktdma 0x7507 0>; 232 dma-names = "tx", "rx1", "rx2"; 233 }; 234 235 secure_proxy_sa3: mailbox@43600000 { 236 compatible = "ti,am654-secure-proxy"; 237 #mbox-cells = <1>; 238 reg-names = "target_data", "rt", "scfg"; 239 reg = <0x00 0x43600000 0x00 0x10000>, 240 <0x00 0x44880000 0x00 0x20000>, 241 <0x00 0x44860000 0x00 0x20000>; 242 /* 243 * Marked Disabled: 244 * Node is incomplete as it is meant for bootloaders and 245 * firmware on non-MPU processors 246 */ 247 status = "disabled"; 248 bootph-all; 249 }; 250 251 main_pmx0: pinctrl@f4000 { 252 compatible = "pinctrl-single"; 253 reg = <0x00 0xf4000 0x00 0x2ac>; 254 #pinctrl-cells = <1>; 255 pinctrl-single,register-width = <32>; 256 pinctrl-single,function-mask = <0xffffffff>; 257 bootph-all; 258 }; 259 260 main_esm: esm@420000 { 261 compatible = "ti,j721e-esm"; 262 reg = <0x00 0x420000 0x00 0x1000>; 263 bootph-pre-ram; 264 /* Interrupt sources: rti0, rti1, wrti0 rti2, rti3, rti15 */ 265 ti,esm-pins = <224>, <225>, <227>, <241>, <242>, <248>; 266 }; 267 268 main_timer0: timer@2400000 { 269 compatible = "ti,am654-timer"; 270 reg = <0x00 0x2400000 0x00 0x400>; 271 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 272 clocks = <&k3_clks 36 2>; 273 clock-names = "fck"; 274 assigned-clocks = <&k3_clks 36 2>; 275 assigned-clock-parents = <&k3_clks 36 3>; 276 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 277 ti,timer-pwm; 278 bootph-all; 279 }; 280 281 main_timer1: timer@2410000 { 282 compatible = "ti,am654-timer"; 283 reg = <0x00 0x2410000 0x00 0x400>; 284 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&k3_clks 37 2>; 286 clock-names = "fck"; 287 assigned-clocks = <&k3_clks 37 2>; 288 assigned-clock-parents = <&k3_clks 37 3>; 289 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 290 ti,timer-pwm; 291 }; 292 293 main_timer2: timer@2420000 { 294 compatible = "ti,am654-timer"; 295 reg = <0x00 0x2420000 0x00 0x400>; 296 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&k3_clks 38 2>; 298 clock-names = "fck"; 299 assigned-clocks = <&k3_clks 38 2>; 300 assigned-clock-parents = <&k3_clks 38 3>; 301 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 302 ti,timer-pwm; 303 }; 304 305 main_timer3: timer@2430000 { 306 compatible = "ti,am654-timer"; 307 reg = <0x00 0x2430000 0x00 0x400>; 308 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 309 clocks = <&k3_clks 39 2>; 310 clock-names = "fck"; 311 assigned-clocks = <&k3_clks 39 2>; 312 assigned-clock-parents = <&k3_clks 39 3>; 313 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 314 ti,timer-pwm; 315 }; 316 317 main_timer4: timer@2440000 { 318 compatible = "ti,am654-timer"; 319 reg = <0x00 0x2440000 0x00 0x400>; 320 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&k3_clks 40 2>; 322 clock-names = "fck"; 323 assigned-clocks = <&k3_clks 40 2>; 324 assigned-clock-parents = <&k3_clks 40 3>; 325 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 326 ti,timer-pwm; 327 }; 328 329 main_timer5: timer@2450000 { 330 compatible = "ti,am654-timer"; 331 reg = <0x00 0x2450000 0x00 0x400>; 332 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&k3_clks 41 2>; 334 clock-names = "fck"; 335 assigned-clocks = <&k3_clks 41 2>; 336 assigned-clock-parents = <&k3_clks 41 3>; 337 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 338 ti,timer-pwm; 339 }; 340 341 main_timer6: timer@2460000 { 342 compatible = "ti,am654-timer"; 343 reg = <0x00 0x2460000 0x00 0x400>; 344 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&k3_clks 42 2>; 346 clock-names = "fck"; 347 assigned-clocks = <&k3_clks 42 2>; 348 assigned-clock-parents = <&k3_clks 42 3>; 349 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 350 ti,timer-pwm; 351 }; 352 353 main_timer7: timer@2470000 { 354 compatible = "ti,am654-timer"; 355 reg = <0x00 0x2470000 0x00 0x400>; 356 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&k3_clks 43 2>; 358 clock-names = "fck"; 359 assigned-clocks = <&k3_clks 43 2>; 360 assigned-clock-parents = <&k3_clks 43 3>; 361 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 362 ti,timer-pwm; 363 }; 364 365 main_uart0: serial@2800000 { 366 compatible = "ti,am64-uart", "ti,am654-uart"; 367 reg = <0x00 0x02800000 0x00 0x100>; 368 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 369 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 370 clocks = <&k3_clks 146 0>; 371 clock-names = "fclk"; 372 status = "disabled"; 373 }; 374 375 main_uart1: serial@2810000 { 376 compatible = "ti,am64-uart", "ti,am654-uart"; 377 reg = <0x00 0x02810000 0x00 0x100>; 378 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 379 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 380 clocks = <&k3_clks 152 0>; 381 clock-names = "fclk"; 382 status = "disabled"; 383 }; 384 385 main_uart2: serial@2820000 { 386 compatible = "ti,am64-uart", "ti,am654-uart"; 387 reg = <0x00 0x02820000 0x00 0x100>; 388 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 389 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 390 clocks = <&k3_clks 153 0>; 391 clock-names = "fclk"; 392 status = "disabled"; 393 }; 394 395 main_uart3: serial@2830000 { 396 compatible = "ti,am64-uart", "ti,am654-uart"; 397 reg = <0x00 0x02830000 0x00 0x100>; 398 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 399 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 400 clocks = <&k3_clks 154 0>; 401 clock-names = "fclk"; 402 status = "disabled"; 403 }; 404 405 main_uart4: serial@2840000 { 406 compatible = "ti,am64-uart", "ti,am654-uart"; 407 reg = <0x00 0x02840000 0x00 0x100>; 408 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 409 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 410 clocks = <&k3_clks 155 0>; 411 clock-names = "fclk"; 412 status = "disabled"; 413 }; 414 415 main_uart5: serial@2850000 { 416 compatible = "ti,am64-uart", "ti,am654-uart"; 417 reg = <0x00 0x02850000 0x00 0x100>; 418 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 419 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 420 clocks = <&k3_clks 156 0>; 421 clock-names = "fclk"; 422 status = "disabled"; 423 }; 424 425 main_uart6: serial@2860000 { 426 compatible = "ti,am64-uart", "ti,am654-uart"; 427 reg = <0x00 0x02860000 0x00 0x100>; 428 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 429 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 430 clocks = <&k3_clks 158 0>; 431 clock-names = "fclk"; 432 status = "disabled"; 433 }; 434 435 main_i2c0: i2c@20000000 { 436 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 437 reg = <0x00 0x20000000 0x00 0x100>; 438 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 442 clocks = <&k3_clks 102 2>; 443 clock-names = "fck"; 444 status = "disabled"; 445 }; 446 447 main_i2c1: i2c@20010000 { 448 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 449 reg = <0x00 0x20010000 0x00 0x100>; 450 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 451 #address-cells = <1>; 452 #size-cells = <0>; 453 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 454 clocks = <&k3_clks 103 2>; 455 clock-names = "fck"; 456 status = "disabled"; 457 }; 458 459 main_i2c2: i2c@20020000 { 460 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 461 reg = <0x00 0x20020000 0x00 0x100>; 462 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 463 #address-cells = <1>; 464 #size-cells = <0>; 465 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 466 clocks = <&k3_clks 104 2>; 467 clock-names = "fck"; 468 status = "disabled"; 469 }; 470 471 main_i2c3: i2c@20030000 { 472 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 473 reg = <0x00 0x20030000 0x00 0x100>; 474 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 475 #address-cells = <1>; 476 #size-cells = <0>; 477 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 478 clocks = <&k3_clks 105 2>; 479 clock-names = "fck"; 480 status = "disabled"; 481 }; 482 483 main_spi0: spi@20100000 { 484 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 485 reg = <0x00 0x20100000 0x00 0x400>; 486 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 487 #address-cells = <1>; 488 #size-cells = <0>; 489 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 490 clocks = <&k3_clks 141 0>; 491 status = "disabled"; 492 }; 493 494 main_spi1: spi@20110000 { 495 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 496 reg = <0x00 0x20110000 0x00 0x400>; 497 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 498 #address-cells = <1>; 499 #size-cells = <0>; 500 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 501 clocks = <&k3_clks 142 0>; 502 status = "disabled"; 503 }; 504 505 main_spi2: spi@20120000 { 506 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 507 reg = <0x00 0x20120000 0x00 0x400>; 508 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 512 clocks = <&k3_clks 143 0>; 513 status = "disabled"; 514 }; 515 516 main_gpio_intr: interrupt-controller@a00000 { 517 compatible = "ti,sci-intr"; 518 reg = <0x00 0x00a00000 0x00 0x800>; 519 ti,intr-trigger-type = <1>; 520 interrupt-controller; 521 interrupt-parent = <&gic500>; 522 #interrupt-cells = <1>; 523 ti,sci = <&dmsc>; 524 ti,sci-dev-id = <3>; 525 ti,interrupt-ranges = <0 32 16>; 526 }; 527 528 main_gpio0: gpio@600000 { 529 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 530 reg = <0x00 0x00600000 0x00 0x100>; 531 gpio-controller; 532 #gpio-cells = <2>; 533 interrupt-parent = <&main_gpio_intr>; 534 interrupts = <190>, <191>, <192>, 535 <193>, <194>, <195>; 536 interrupt-controller; 537 #interrupt-cells = <2>; 538 ti,davinci-gpio-unbanked = <0>; 539 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 540 clocks = <&k3_clks 77 0>; 541 clock-names = "gpio"; 542 }; 543 544 main_gpio1: gpio@601000 { 545 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 546 reg = <0x00 0x00601000 0x00 0x100>; 547 gpio-controller; 548 #gpio-cells = <2>; 549 interrupt-parent = <&main_gpio_intr>; 550 interrupts = <180>, <181>, <182>, 551 <183>, <184>, <185>; 552 interrupt-controller; 553 #interrupt-cells = <2>; 554 ti,davinci-gpio-unbanked = <0>; 555 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 556 clocks = <&k3_clks 78 0>; 557 clock-names = "gpio"; 558 }; 559 560 sdhci0: mmc@fa10000 { 561 compatible = "ti,am64-sdhci-8bit"; 562 reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>; 563 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 564 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 565 clocks = <&k3_clks 57 1>, <&k3_clks 57 2>; 566 clock-names = "clk_ahb", "clk_xin"; 567 assigned-clocks = <&k3_clks 57 2>; 568 assigned-clock-parents = <&k3_clks 57 4>; 569 bus-width = <8>; 570 mmc-ddr-1_8v; 571 mmc-hs200-1_8v; 572 mmc-hs400-1_8v; 573 ti,clkbuf-sel = <0x7>; 574 ti,strobe-sel = <0x77>; 575 ti,trm-icp = <0x8>; 576 ti,otap-del-sel-legacy = <0x1>; 577 ti,otap-del-sel-mmc-hs = <0x1>; 578 ti,otap-del-sel-ddr52 = <0x6>; 579 ti,otap-del-sel-hs200 = <0x8>; 580 ti,otap-del-sel-hs400 = <0x5>; 581 ti,itap-del-sel-legacy = <0x10>; 582 ti,itap-del-sel-mmc-hs = <0xa>; 583 ti,itap-del-sel-ddr52 = <0x3>; 584 status = "disabled"; 585 }; 586 587 sdhci1: mmc@fa00000 { 588 compatible = "ti,am62-sdhci"; 589 reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>; 590 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 591 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 592 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; 593 clock-names = "clk_ahb", "clk_xin"; 594 bus-width = <4>; 595 ti,clkbuf-sel = <0x7>; 596 ti,otap-del-sel-legacy = <0x0>; 597 ti,otap-del-sel-sd-hs = <0x0>; 598 ti,otap-del-sel-sdr12 = <0xf>; 599 ti,otap-del-sel-sdr25 = <0xf>; 600 ti,otap-del-sel-sdr50 = <0xc>; 601 ti,otap-del-sel-ddr50 = <0x9>; 602 ti,otap-del-sel-sdr104 = <0x6>; 603 ti,itap-del-sel-legacy = <0x0>; 604 ti,itap-del-sel-sd-hs = <0x0>; 605 ti,itap-del-sel-sdr12 = <0x0>; 606 ti,itap-del-sel-sdr25 = <0x0>; 607 status = "disabled"; 608 }; 609 610 sdhci2: mmc@fa20000 { 611 compatible = "ti,am62-sdhci"; 612 reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>; 613 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 614 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 615 clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; 616 clock-names = "clk_ahb", "clk_xin"; 617 bus-width = <4>; 618 ti,clkbuf-sel = <0x7>; 619 ti,otap-del-sel-legacy = <0x0>; 620 ti,otap-del-sel-sd-hs = <0x0>; 621 ti,otap-del-sel-sdr12 = <0xf>; 622 ti,otap-del-sel-sdr25 = <0xf>; 623 ti,otap-del-sel-sdr50 = <0xc>; 624 ti,otap-del-sel-ddr50 = <0x9>; 625 ti,otap-del-sel-sdr104 = <0x6>; 626 ti,itap-del-sel-legacy = <0x0>; 627 ti,itap-del-sel-sd-hs = <0x0>; 628 ti,itap-del-sel-sdr12 = <0x0>; 629 ti,itap-del-sel-sdr25 = <0x0>; 630 status = "disabled"; 631 }; 632 633 usbss0: usb@f900000 { 634 compatible = "ti,am62-usb"; 635 reg = <0x00 0x0f900000 0x00 0x800>, 636 <0x00 0x0f908000 0x00 0x400>; 637 clocks = <&k3_clks 161 3>; 638 clock-names = "ref"; 639 ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>; 640 #address-cells = <2>; 641 #size-cells = <2>; 642 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 643 ranges; 644 status = "disabled"; 645 646 usb0: usb@31000000 { 647 compatible = "snps,dwc3"; 648 reg = <0x00 0x31000000 0x00 0x50000>; 649 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 650 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 651 interrupt-names = "host", "peripheral"; 652 maximum-speed = "high-speed"; 653 dr_mode = "otg"; 654 snps,usb2-gadget-lpm-disable; 655 snps,usb2-lpm-disable; 656 }; 657 }; 658 659 fss: bus@fc00000 { 660 compatible = "simple-bus"; 661 reg = <0x00 0x0fc00000 0x00 0x70000>; 662 #address-cells = <2>; 663 #size-cells = <2>; 664 ranges; 665 666 ospi0: spi@fc40000 { 667 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 668 reg = <0x00 0x0fc40000 0x00 0x100>, 669 <0x05 0x00000000 0x01 0x00000000>; 670 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 671 cdns,fifo-depth = <256>; 672 cdns,fifo-width = <4>; 673 cdns,trigger-address = <0x0>; 674 clocks = <&k3_clks 75 7>; 675 assigned-clocks = <&k3_clks 75 7>; 676 assigned-clock-parents = <&k3_clks 75 8>; 677 assigned-clock-rates = <166666666>; 678 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 679 #address-cells = <1>; 680 #size-cells = <0>; 681 status = "disabled"; 682 }; 683 }; 684 685 cpsw3g: ethernet@8000000 { 686 compatible = "ti,am642-cpsw-nuss"; 687 #address-cells = <2>; 688 #size-cells = <2>; 689 reg = <0x00 0x08000000 0x00 0x200000>; 690 reg-names = "cpsw_nuss"; 691 ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>; 692 clocks = <&k3_clks 13 0>; 693 assigned-clocks = <&k3_clks 13 3>; 694 assigned-clock-parents = <&k3_clks 13 11>; 695 clock-names = "fck"; 696 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 697 status = "disabled"; 698 699 dmas = <&main_pktdma 0xc600 15>, 700 <&main_pktdma 0xc601 15>, 701 <&main_pktdma 0xc602 15>, 702 <&main_pktdma 0xc603 15>, 703 <&main_pktdma 0xc604 15>, 704 <&main_pktdma 0xc605 15>, 705 <&main_pktdma 0xc606 15>, 706 <&main_pktdma 0xc607 15>, 707 <&main_pktdma 0x4600 15>; 708 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 709 "tx7", "rx"; 710 711 ethernet-ports { 712 #address-cells = <1>; 713 #size-cells = <0>; 714 715 cpsw_port1: port@1 { 716 reg = <1>; 717 ti,mac-only; 718 label = "port1"; 719 phys = <&phy_gmii_sel 1>; 720 mac-address = [00 00 00 00 00 00]; 721 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; 722 status = "disabled"; 723 }; 724 725 cpsw_port2: port@2 { 726 reg = <2>; 727 ti,mac-only; 728 label = "port2"; 729 phys = <&phy_gmii_sel 2>; 730 mac-address = [00 00 00 00 00 00]; 731 status = "disabled"; 732 }; 733 }; 734 735 cpsw3g_mdio: mdio@f00 { 736 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 737 reg = <0x00 0xf00 0x00 0x100>; 738 #address-cells = <1>; 739 #size-cells = <0>; 740 clocks = <&k3_clks 13 0>; 741 clock-names = "fck"; 742 bus_freq = <1000000>; 743 status = "disabled"; 744 }; 745 746 cpts@3d000 { 747 compatible = "ti,j721e-cpts"; 748 reg = <0x00 0x3d000 0x00 0x400>; 749 clocks = <&k3_clks 13 3>; 750 clock-names = "cpts"; 751 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 752 interrupt-names = "cpts"; 753 ti,cpts-ext-ts-inputs = <4>; 754 ti,cpts-periodic-outputs = <2>; 755 }; 756 }; 757 758 hwspinlock: spinlock@2a000000 { 759 compatible = "ti,am64-hwspinlock"; 760 reg = <0x00 0x2a000000 0x00 0x1000>; 761 #hwlock-cells = <1>; 762 }; 763 764 mailbox0_cluster0: mailbox@29000000 { 765 compatible = "ti,am64-mailbox"; 766 reg = <0x00 0x29000000 0x00 0x200>; 767 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 768 #mbox-cells = <1>; 769 ti,mbox-num-users = <4>; 770 ti,mbox-num-fifos = <16>; 771 }; 772 773 mailbox0_cluster1: mailbox@29010000 { 774 compatible = "ti,am64-mailbox"; 775 reg = <0x00 0x29010000 0x00 0x200>; 776 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 777 #mbox-cells = <1>; 778 ti,mbox-num-users = <4>; 779 ti,mbox-num-fifos = <16>; 780 }; 781 782 mailbox0_cluster2: mailbox@29020000 { 783 compatible = "ti,am64-mailbox"; 784 reg = <0x00 0x29020000 0x00 0x200>; 785 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 786 #mbox-cells = <1>; 787 ti,mbox-num-users = <4>; 788 ti,mbox-num-fifos = <16>; 789 }; 790 791 mailbox0_cluster3: mailbox@29030000 { 792 compatible = "ti,am64-mailbox"; 793 reg = <0x00 0x29030000 0x00 0x200>; 794 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 795 #mbox-cells = <1>; 796 ti,mbox-num-users = <4>; 797 ti,mbox-num-fifos = <16>; 798 }; 799 800 ecap0: pwm@23100000 { 801 compatible = "ti,am3352-ecap"; 802 #pwm-cells = <3>; 803 reg = <0x00 0x23100000 0x00 0x100>; 804 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 805 clocks = <&k3_clks 51 0>; 806 clock-names = "fck"; 807 status = "disabled"; 808 }; 809 810 ecap1: pwm@23110000 { 811 compatible = "ti,am3352-ecap"; 812 #pwm-cells = <3>; 813 reg = <0x00 0x23110000 0x00 0x100>; 814 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 815 clocks = <&k3_clks 52 0>; 816 clock-names = "fck"; 817 status = "disabled"; 818 }; 819 820 ecap2: pwm@23120000 { 821 compatible = "ti,am3352-ecap"; 822 #pwm-cells = <3>; 823 reg = <0x00 0x23120000 0x00 0x100>; 824 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 825 clocks = <&k3_clks 53 0>; 826 clock-names = "fck"; 827 status = "disabled"; 828 }; 829 830 main_mcan0: can@20701000 { 831 compatible = "bosch,m_can"; 832 reg = <0x00 0x20701000 0x00 0x200>, 833 <0x00 0x20708000 0x00 0x8000>; 834 reg-names = "m_can", "message_ram"; 835 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 836 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; 837 clock-names = "hclk", "cclk"; 838 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 840 interrupt-names = "int0", "int1"; 841 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 842 status = "disabled"; 843 }; 844 845 main_mcan1: can@20711000 { 846 compatible = "bosch,m_can"; 847 reg = <0x00 0x20711000 0x00 0x200>, 848 <0x00 0x20718000 0x00 0x8000>; 849 reg-names = "m_can", "message_ram"; 850 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 851 clocks = <&k3_clks 99 6>, <&k3_clks 99 1>; 852 clock-names = "hclk", "cclk"; 853 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 854 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 855 interrupt-names = "int0", "int1"; 856 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 857 status = "disabled"; 858 }; 859 860 main_rti0: watchdog@e000000 { 861 compatible = "ti,j7-rti-wdt"; 862 reg = <0x00 0x0e000000 0x00 0x100>; 863 clocks = <&k3_clks 125 0>; 864 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 865 assigned-clocks = <&k3_clks 125 0>; 866 assigned-clock-parents = <&k3_clks 125 2>; 867 }; 868 869 main_rti1: watchdog@e010000 { 870 compatible = "ti,j7-rti-wdt"; 871 reg = <0x00 0x0e010000 0x00 0x100>; 872 clocks = <&k3_clks 126 0>; 873 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; 874 assigned-clocks = <&k3_clks 126 0>; 875 assigned-clock-parents = <&k3_clks 126 2>; 876 }; 877 878 main_rti2: watchdog@e020000 { 879 compatible = "ti,j7-rti-wdt"; 880 reg = <0x00 0x0e020000 0x00 0x100>; 881 clocks = <&k3_clks 127 0>; 882 power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; 883 assigned-clocks = <&k3_clks 127 0>; 884 assigned-clock-parents = <&k3_clks 127 2>; 885 }; 886 887 main_rti3: watchdog@e030000 { 888 compatible = "ti,j7-rti-wdt"; 889 reg = <0x00 0x0e030000 0x00 0x100>; 890 clocks = <&k3_clks 128 0>; 891 power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; 892 assigned-clocks = <&k3_clks 128 0>; 893 assigned-clock-parents = <&k3_clks 128 2>; 894 }; 895 896 main_rti15: watchdog@e0f0000 { 897 compatible = "ti,j7-rti-wdt"; 898 reg = <0x00 0x0e0f0000 0x00 0x100>; 899 clocks = <&k3_clks 130 0>; 900 power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>; 901 assigned-clocks = <&k3_clks 130 0>; 902 assigned-clock-parents = <&k3_clks 130 2>; 903 }; 904 905 epwm0: pwm@23000000 { 906 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 907 #pwm-cells = <3>; 908 reg = <0x00 0x23000000 0x00 0x100>; 909 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 910 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 911 clock-names = "tbclk", "fck"; 912 status = "disabled"; 913 }; 914 915 epwm1: pwm@23010000 { 916 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 917 #pwm-cells = <3>; 918 reg = <0x00 0x23010000 0x00 0x100>; 919 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 920 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 921 clock-names = "tbclk", "fck"; 922 status = "disabled"; 923 }; 924 925 epwm2: pwm@23020000 { 926 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 927 #pwm-cells = <3>; 928 reg = <0x00 0x23020000 0x00 0x100>; 929 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 930 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 931 clock-names = "tbclk", "fck"; 932 status = "disabled"; 933 }; 934 935 mcasp0: audio-controller@2b00000 { 936 compatible = "ti,am33xx-mcasp-audio"; 937 reg = <0x00 0x02b00000 0x00 0x2000>, 938 <0x00 0x02b08000 0x00 0x400>; 939 reg-names = "mpu", "dat"; 940 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 942 interrupt-names = "tx", "rx"; 943 944 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; 945 dma-names = "tx", "rx"; 946 947 clocks = <&k3_clks 190 0>; 948 clock-names = "fck"; 949 assigned-clocks = <&k3_clks 190 0>; 950 assigned-clock-parents = <&k3_clks 190 2>; 951 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 952 status = "disabled"; 953 }; 954 955 mcasp1: audio-controller@2b10000 { 956 compatible = "ti,am33xx-mcasp-audio"; 957 reg = <0x00 0x02b10000 0x00 0x2000>, 958 <0x00 0x02b18000 0x00 0x400>; 959 reg-names = "mpu", "dat"; 960 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 962 interrupt-names = "tx", "rx"; 963 964 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; 965 dma-names = "tx", "rx"; 966 967 clocks = <&k3_clks 191 0>; 968 clock-names = "fck"; 969 assigned-clocks = <&k3_clks 191 0>; 970 assigned-clock-parents = <&k3_clks 191 2>; 971 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 972 status = "disabled"; 973 }; 974 975 mcasp2: audio-controller@2b20000 { 976 compatible = "ti,am33xx-mcasp-audio"; 977 reg = <0x00 0x02b20000 0x00 0x2000>, 978 <0x00 0x02b28000 0x00 0x400>; 979 reg-names = "mpu", "dat"; 980 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 981 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 982 interrupt-names = "tx", "rx"; 983 984 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; 985 dma-names = "tx", "rx"; 986 987 clocks = <&k3_clks 192 0>; 988 clock-names = "fck"; 989 assigned-clocks = <&k3_clks 192 0>; 990 assigned-clock-parents = <&k3_clks 192 2>; 991 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 992 status = "disabled"; 993 }; 994 995 ti_csi2rx0: ticsi2rx@30102000 { 996 compatible = "ti,j721e-csi2rx-shim"; 997 reg = <0x00 0x30102000 0x00 0x1000>; 998 ranges; 999 #address-cells = <2>; 1000 #size-cells = <2>; 1001 dmas = <&main_bcdma_csi 0 0x5000 0>; 1002 dma-names = "rx0"; 1003 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1004 status = "disabled"; 1005 1006 cdns_csi2rx0: csi-bridge@30101000 { 1007 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 1008 reg = <0x00 0x30101000 0x00 0x1000>; 1009 clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, 1010 <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; 1011 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 1012 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 1013 phys = <&dphy0>; 1014 phy-names = "dphy"; 1015 1016 ports { 1017 #address-cells = <1>; 1018 #size-cells = <0>; 1019 1020 csi0_port0: port@0 { 1021 reg = <0>; 1022 status = "disabled"; 1023 }; 1024 1025 csi0_port1: port@1 { 1026 reg = <1>; 1027 status = "disabled"; 1028 }; 1029 1030 csi0_port2: port@2 { 1031 reg = <2>; 1032 status = "disabled"; 1033 }; 1034 1035 csi0_port3: port@3 { 1036 reg = <3>; 1037 status = "disabled"; 1038 }; 1039 1040 csi0_port4: port@4 { 1041 reg = <4>; 1042 status = "disabled"; 1043 }; 1044 }; 1045 }; 1046 }; 1047 1048 dphy0: phy@30110000 { 1049 compatible = "cdns,dphy-rx"; 1050 reg = <0x00 0x30110000 0x00 0x1100>; 1051 #phy-cells = <0>; 1052 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1053 status = "disabled"; 1054 }; 1055 1056 vpu: video-codec@30210000 { 1057 compatible = "ti,j721s2-wave521c", "cnm,wave521c"; 1058 reg = <0x00 0x30210000 0x00 0x10000>; 1059 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1060 clocks = <&k3_clks 204 2>; 1061 power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; 1062 }; 1063}; 1064