15fc6b1b6SVignesh Raghavendra// SPDX-License-Identifier: GPL-2.0 25fc6b1b6SVignesh Raghavendra/* 35fc6b1b6SVignesh Raghavendra * Device Tree Source for AM625 SoC Family MCU Domain peripherals 45fc6b1b6SVignesh Raghavendra * 55fc6b1b6SVignesh Raghavendra * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ 65fc6b1b6SVignesh Raghavendra */ 75fc6b1b6SVignesh Raghavendra 85fc6b1b6SVignesh Raghavendra&cbass_mcu { 95fc6b1b6SVignesh Raghavendra mcu_pmx0: pinctrl@4084000 { 105fc6b1b6SVignesh Raghavendra compatible = "pinctrl-single"; 115fc6b1b6SVignesh Raghavendra reg = <0x00 0x04084000 0x00 0x88>; 125fc6b1b6SVignesh Raghavendra #pinctrl-cells = <1>; 135fc6b1b6SVignesh Raghavendra pinctrl-single,register-width = <32>; 145fc6b1b6SVignesh Raghavendra pinctrl-single,function-mask = <0xffffffff>; 155fc6b1b6SVignesh Raghavendra status = "disabled"; 165fc6b1b6SVignesh Raghavendra }; 175fc6b1b6SVignesh Raghavendra 1868dd81a7SNishanth Menon /* 1968dd81a7SNishanth Menon * The MCU domain timer interrupts are routed only to the ESM module, 2068dd81a7SNishanth Menon * and not currently available for Linux. The MCU domain timers are 2168dd81a7SNishanth Menon * of limited use without interrupts, and likely reserved by the ESM. 2268dd81a7SNishanth Menon */ 2368dd81a7SNishanth Menon mcu_timer0: timer@4800000 { 2468dd81a7SNishanth Menon compatible = "ti,am654-timer"; 2568dd81a7SNishanth Menon reg = <0x00 0x4800000 0x00 0x400>; 2668dd81a7SNishanth Menon clocks = <&k3_clks 35 2>; 2768dd81a7SNishanth Menon clock-names = "fck"; 2868dd81a7SNishanth Menon power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 2968dd81a7SNishanth Menon ti,timer-pwm; 3068dd81a7SNishanth Menon status = "reserved"; 3168dd81a7SNishanth Menon }; 3268dd81a7SNishanth Menon 3368dd81a7SNishanth Menon mcu_timer1: timer@4810000 { 3468dd81a7SNishanth Menon compatible = "ti,am654-timer"; 3568dd81a7SNishanth Menon reg = <0x00 0x4810000 0x00 0x400>; 3668dd81a7SNishanth Menon clocks = <&k3_clks 48 2>; 3768dd81a7SNishanth Menon clock-names = "fck"; 3868dd81a7SNishanth Menon power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; 3968dd81a7SNishanth Menon ti,timer-pwm; 4068dd81a7SNishanth Menon status = "reserved"; 4168dd81a7SNishanth Menon }; 4268dd81a7SNishanth Menon 4368dd81a7SNishanth Menon mcu_timer2: timer@4820000 { 4468dd81a7SNishanth Menon compatible = "ti,am654-timer"; 4568dd81a7SNishanth Menon reg = <0x00 0x4820000 0x00 0x400>; 4668dd81a7SNishanth Menon clocks = <&k3_clks 49 2>; 4768dd81a7SNishanth Menon clock-names = "fck"; 4868dd81a7SNishanth Menon power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; 4968dd81a7SNishanth Menon ti,timer-pwm; 5068dd81a7SNishanth Menon status = "reserved"; 5168dd81a7SNishanth Menon }; 5268dd81a7SNishanth Menon 5368dd81a7SNishanth Menon mcu_timer3: timer@4830000 { 5468dd81a7SNishanth Menon compatible = "ti,am654-timer"; 5568dd81a7SNishanth Menon reg = <0x00 0x4830000 0x00 0x400>; 5668dd81a7SNishanth Menon clocks = <&k3_clks 50 2>; 5768dd81a7SNishanth Menon clock-names = "fck"; 5868dd81a7SNishanth Menon power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; 5968dd81a7SNishanth Menon ti,timer-pwm; 6068dd81a7SNishanth Menon status = "reserved"; 6168dd81a7SNishanth Menon }; 6268dd81a7SNishanth Menon 635fc6b1b6SVignesh Raghavendra mcu_uart0: serial@4a00000 { 645fc6b1b6SVignesh Raghavendra compatible = "ti,am64-uart", "ti,am654-uart"; 655fc6b1b6SVignesh Raghavendra reg = <0x00 0x04a00000 0x00 0x100>; 665fc6b1b6SVignesh Raghavendra interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 675fc6b1b6SVignesh Raghavendra power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 685fc6b1b6SVignesh Raghavendra clocks = <&k3_clks 149 0>; 695fc6b1b6SVignesh Raghavendra clock-names = "fclk"; 705fc6b1b6SVignesh Raghavendra status = "disabled"; 715fc6b1b6SVignesh Raghavendra }; 725fc6b1b6SVignesh Raghavendra 735fc6b1b6SVignesh Raghavendra mcu_i2c0: i2c@4900000 { 745fc6b1b6SVignesh Raghavendra compatible = "ti,am64-i2c", "ti,omap4-i2c"; 755fc6b1b6SVignesh Raghavendra reg = <0x00 0x04900000 0x00 0x100>; 765fc6b1b6SVignesh Raghavendra interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 775fc6b1b6SVignesh Raghavendra #address-cells = <1>; 785fc6b1b6SVignesh Raghavendra #size-cells = <0>; 795fc6b1b6SVignesh Raghavendra power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 805fc6b1b6SVignesh Raghavendra clocks = <&k3_clks 106 2>; 815fc6b1b6SVignesh Raghavendra clock-names = "fck"; 825fc6b1b6SVignesh Raghavendra status = "disabled"; 835fc6b1b6SVignesh Raghavendra }; 84eaee246bSVignesh Raghavendra 85eaee246bSVignesh Raghavendra mcu_spi0: spi@4b00000 { 86eaee246bSVignesh Raghavendra compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 87eaee246bSVignesh Raghavendra reg = <0x00 0x04b00000 0x00 0x400>; 88eaee246bSVignesh Raghavendra interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 89eaee246bSVignesh Raghavendra #address-cells = <1>; 90eaee246bSVignesh Raghavendra #size-cells = <0>; 91eaee246bSVignesh Raghavendra power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; 92eaee246bSVignesh Raghavendra clocks = <&k3_clks 147 0>; 93eaee246bSVignesh Raghavendra status = "disabled"; 94eaee246bSVignesh Raghavendra }; 95eaee246bSVignesh Raghavendra 96eaee246bSVignesh Raghavendra mcu_spi1: spi@4b10000 { 97eaee246bSVignesh Raghavendra compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 98eaee246bSVignesh Raghavendra reg = <0x00 0x04b10000 0x00 0x400>; 99eaee246bSVignesh Raghavendra interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 100eaee246bSVignesh Raghavendra #address-cells = <1>; 101eaee246bSVignesh Raghavendra #size-cells = <0>; 102eaee246bSVignesh Raghavendra power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; 103eaee246bSVignesh Raghavendra clocks = <&k3_clks 148 0>; 104eaee246bSVignesh Raghavendra status = "disabled"; 105eaee246bSVignesh Raghavendra }; 106eaee246bSVignesh Raghavendra 107eaee246bSVignesh Raghavendra mcu_gpio_intr: interrupt-controller@4210000 { 108eaee246bSVignesh Raghavendra compatible = "ti,sci-intr"; 109eaee246bSVignesh Raghavendra reg = <0x00 0x04210000 0x00 0x200>; 110eaee246bSVignesh Raghavendra ti,intr-trigger-type = <1>; 111eaee246bSVignesh Raghavendra interrupt-controller; 112eaee246bSVignesh Raghavendra interrupt-parent = <&gic500>; 113eaee246bSVignesh Raghavendra #interrupt-cells = <1>; 114eaee246bSVignesh Raghavendra ti,sci = <&dmsc>; 115eaee246bSVignesh Raghavendra ti,sci-dev-id = <5>; 116eaee246bSVignesh Raghavendra ti,interrupt-ranges = <0 104 4>; 117eaee246bSVignesh Raghavendra }; 118eaee246bSVignesh Raghavendra 119eaee246bSVignesh Raghavendra mcu_gpio0: gpio@4201000 { 120eaee246bSVignesh Raghavendra compatible = "ti,am64-gpio", "ti,keystone-gpio"; 121eaee246bSVignesh Raghavendra reg = <0x00 0x04201000 0x00 0x100>; 122eaee246bSVignesh Raghavendra gpio-controller; 123eaee246bSVignesh Raghavendra #gpio-cells = <2>; 124eaee246bSVignesh Raghavendra interrupt-parent = <&mcu_gpio_intr>; 125eaee246bSVignesh Raghavendra interrupts = <30>, <31>; 126eaee246bSVignesh Raghavendra interrupt-controller; 127eaee246bSVignesh Raghavendra #interrupt-cells = <2>; 128eaee246bSVignesh Raghavendra ti,ngpio = <24>; 129eaee246bSVignesh Raghavendra ti,davinci-gpio-unbanked = <0>; 130eaee246bSVignesh Raghavendra power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; 131eaee246bSVignesh Raghavendra clocks = <&k3_clks 79 0>; 132eaee246bSVignesh Raghavendra clock-names = "gpio"; 133eaee246bSVignesh Raghavendra status = "disabled"; 134eaee246bSVignesh Raghavendra }; 135*804702e4SNishanth Menon 136*804702e4SNishanth Menon mcu_rti0: watchdog@4880000 { 137*804702e4SNishanth Menon compatible = "ti,j7-rti-wdt"; 138*804702e4SNishanth Menon reg = <0x00 0x04880000 0x00 0x100>; 139*804702e4SNishanth Menon clocks = <&k3_clks 131 0>; 140*804702e4SNishanth Menon power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>; 141*804702e4SNishanth Menon assigned-clocks = <&k3_clks 131 0>; 142*804702e4SNishanth Menon assigned-clock-parents = <&k3_clks 131 2>; 143*804702e4SNishanth Menon /* Tightly coupled to M4F */ 144*804702e4SNishanth Menon status = "reserved"; 145*804702e4SNishanth Menon }; 1465fc6b1b6SVignesh Raghavendra}; 147