1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for AM62A SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 oc_sram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x00 0x70000000 0x00 0x10000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x0 0x00 0x70000000 0x10000>; 15 }; 16 17 gic500: interrupt-controller@1800000 { 18 compatible = "arm,gic-v3"; 19 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 20 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 21 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 22 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 23 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 24 #address-cells = <2>; 25 #size-cells = <2>; 26 ranges; 27 #interrupt-cells = <3>; 28 interrupt-controller; 29 /* 30 * vcpumntirq: 31 * virtual CPU interface maintenance interrupt 32 */ 33 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 34 35 gic_its: msi-controller@1820000 { 36 compatible = "arm,gic-v3-its"; 37 reg = <0x00 0x01820000 0x00 0x10000>; 38 socionext,synquacer-pre-its = <0x1000000 0x400000>; 39 msi-controller; 40 #msi-cells = <1>; 41 }; 42 }; 43 44 main_conf: bus@100000 { 45 compatible = "simple-bus"; 46 #address-cells = <1>; 47 #size-cells = <1>; 48 ranges = <0x00 0x00 0x00100000 0x20000>; 49 50 phy_gmii_sel: phy@4044 { 51 compatible = "ti,am654-phy-gmii-sel"; 52 reg = <0x4044 0x8>; 53 #phy-cells = <1>; 54 bootph-all; 55 }; 56 57 epwm_tbclk: clock-controller@4130 { 58 compatible = "ti,am62-epwm-tbclk"; 59 reg = <0x4130 0x4>; 60 #clock-cells = <1>; 61 }; 62 63 audio_refclk0: clock-controller@82e0 { 64 compatible = "ti,am62-audio-refclk"; 65 reg = <0x82e0 0x4>; 66 clocks = <&k3_clks 157 0>; 67 assigned-clocks = <&k3_clks 157 0>; 68 assigned-clock-parents = <&k3_clks 157 8>; 69 #clock-cells = <0>; 70 }; 71 72 audio_refclk1: clock-controller@82e4 { 73 compatible = "ti,am62-audio-refclk"; 74 reg = <0x82e4 0x4>; 75 clocks = <&k3_clks 157 10>; 76 assigned-clocks = <&k3_clks 157 10>; 77 assigned-clock-parents = <&k3_clks 157 18>; 78 #clock-cells = <0>; 79 }; 80 }; 81 82 dmss: bus@48000000 { 83 compatible = "simple-bus"; 84 #address-cells = <2>; 85 #size-cells = <2>; 86 dma-ranges; 87 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>; 88 89 ti,sci-dev-id = <25>; 90 91 secure_proxy_main: mailbox@4d000000 { 92 compatible = "ti,am654-secure-proxy"; 93 reg = <0x00 0x4d000000 0x00 0x80000>, 94 <0x00 0x4a600000 0x00 0x80000>, 95 <0x00 0x4a400000 0x00 0x80000>; 96 reg-names = "target_data", "rt", "scfg"; 97 #mbox-cells = <1>; 98 interrupt-names = "rx_012"; 99 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 100 bootph-all; 101 }; 102 103 inta_main_dmss: interrupt-controller@48000000 { 104 compatible = "ti,sci-inta"; 105 reg = <0x00 0x48000000 0x00 0x100000>; 106 #interrupt-cells = <0>; 107 interrupt-controller; 108 interrupt-parent = <&gic500>; 109 msi-controller; 110 ti,sci = <&dmsc>; 111 ti,sci-dev-id = <28>; 112 ti,interrupt-ranges = <6 70 34>; 113 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 114 }; 115 116 main_bcdma: dma-controller@485c0100 { 117 compatible = "ti,am64-dmss-bcdma"; 118 reg = <0x00 0x485c0100 0x00 0x100>, 119 <0x00 0x4c000000 0x00 0x20000>, 120 <0x00 0x4a820000 0x00 0x20000>, 121 <0x00 0x4aa40000 0x00 0x20000>, 122 <0x00 0x4bc00000 0x00 0x100000>, 123 <0x00 0x48600000 0x00 0x8000>, 124 <0x00 0x484a4000 0x00 0x2000>, 125 <0x00 0x484c2000 0x00 0x2000>, 126 <0x00 0x48420000 0x00 0x2000>; 127 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt", 128 "ring", "tchan", "rchan", "bchan"; 129 msi-parent = <&inta_main_dmss>; 130 #dma-cells = <3>; 131 ti,sci = <&dmsc>; 132 ti,sci-dev-id = <26>; 133 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 134 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 135 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 136 bootph-all; 137 }; 138 139 main_pktdma: dma-controller@485c0000 { 140 compatible = "ti,am64-dmss-pktdma"; 141 reg = <0x00 0x485c0000 0x00 0x100>, 142 <0x00 0x4a800000 0x00 0x20000>, 143 <0x00 0x4aa00000 0x00 0x20000>, 144 <0x00 0x4b800000 0x00 0x200000>, 145 <0x00 0x485e0000 0x00 0x10000>, 146 <0x00 0x484a0000 0x00 0x2000>, 147 <0x00 0x484c0000 0x00 0x2000>, 148 <0x00 0x48430000 0x00 0x1000>; 149 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", 150 "ring", "tchan", "rchan", "rflow"; 151 msi-parent = <&inta_main_dmss>; 152 #dma-cells = <2>; 153 bootph-all; 154 155 ti,sci = <&dmsc>; 156 ti,sci-dev-id = <30>; 157 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 158 <0x24>, /* CPSW_TX_CHAN */ 159 <0x25>, /* SAUL_TX_0_CHAN */ 160 <0x26>; /* SAUL_TX_1_CHAN */ 161 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 162 <0x11>, /* RING_CPSW_TX_CHAN */ 163 <0x12>, /* RING_SAUL_TX_0_CHAN */ 164 <0x13>; /* RING_SAUL_TX_1_CHAN */ 165 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 166 <0x2b>, /* CPSW_RX_CHAN */ 167 <0x2d>, /* SAUL_RX_0_CHAN */ 168 <0x2f>, /* SAUL_RX_1_CHAN */ 169 <0x31>, /* SAUL_RX_2_CHAN */ 170 <0x33>; /* SAUL_RX_3_CHAN */ 171 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 172 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 173 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 174 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ 175 }; 176 }; 177 178 dmss_csi: bus@4e000000 { 179 compatible = "simple-bus"; 180 #address-cells = <2>; 181 #size-cells = <2>; 182 dma-ranges; 183 ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x300000>; 184 185 ti,sci-dev-id = <198>; 186 187 inta_main_dmss_csi: interrupt-controller@4e0a0000 { 188 compatible = "ti,sci-inta"; 189 reg = <0x00 0x4e0a0000 0x00 0x8000>; 190 #interrupt-cells = <0>; 191 interrupt-controller; 192 interrupt-parent = <&gic500>; 193 msi-controller; 194 ti,sci = <&dmsc>; 195 ti,sci-dev-id = <200>; 196 ti,interrupt-ranges = <0 237 8>; 197 ti,unmapped-event-sources = <&main_bcdma_csi>; 198 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 199 }; 200 201 main_bcdma_csi: dma-controller@4e230000 { 202 compatible = "ti,am62a-dmss-bcdma-csirx"; 203 reg = <0x00 0x4e230000 0x00 0x100>, 204 <0x00 0x4e180000 0x00 0x8000>, 205 <0x00 0x4e100000 0x00 0x10000>; 206 reg-names = "gcfg", "rchanrt", "ringrt"; 207 msi-parent = <&inta_main_dmss_csi>; 208 #dma-cells = <3>; 209 ti,sci = <&dmsc>; 210 ti,sci-dev-id = <199>; 211 ti,sci-rm-range-rchan = <0x21>; 212 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 213 }; 214 }; 215 216 dmsc: system-controller@44043000 { 217 compatible = "ti,k2g-sci"; 218 reg = <0x00 0x44043000 0x00 0xfe0>; 219 reg-names = "debug_messages"; 220 ti,host-id = <12>; 221 mbox-names = "rx", "tx"; 222 mboxes = <&secure_proxy_main 12>, 223 <&secure_proxy_main 13>; 224 225 k3_pds: power-controller { 226 compatible = "ti,sci-pm-domain"; 227 #power-domain-cells = <2>; 228 bootph-all; 229 }; 230 231 k3_clks: clock-controller { 232 compatible = "ti,k2g-sci-clk"; 233 #clock-cells = <2>; 234 bootph-all; 235 }; 236 237 k3_reset: reset-controller { 238 compatible = "ti,sci-reset"; 239 #reset-cells = <2>; 240 bootph-all; 241 }; 242 }; 243 244 crypto: crypto@40900000 { 245 compatible = "ti,am62-sa3ul"; 246 reg = <0x00 0x40900000 0x00 0x1200>; 247 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, 248 <&main_pktdma 0x7507 0>; 249 dma-names = "tx", "rx1", "rx2"; 250 }; 251 252 secure_proxy_sa3: mailbox@43600000 { 253 compatible = "ti,am654-secure-proxy"; 254 #mbox-cells = <1>; 255 reg-names = "target_data", "rt", "scfg"; 256 reg = <0x00 0x43600000 0x00 0x10000>, 257 <0x00 0x44880000 0x00 0x20000>, 258 <0x00 0x44860000 0x00 0x20000>; 259 /* 260 * Marked Disabled: 261 * Node is incomplete as it is meant for bootloaders and 262 * firmware on non-MPU processors 263 */ 264 status = "disabled"; 265 bootph-all; 266 }; 267 268 main_pmx0: pinctrl@f4000 { 269 compatible = "pinctrl-single"; 270 reg = <0x00 0xf4000 0x00 0x25c>; 271 #pinctrl-cells = <1>; 272 pinctrl-single,register-width = <32>; 273 pinctrl-single,function-mask = <0xffffffff>; 274 }; 275 276 main_esm: esm@420000 { 277 compatible = "ti,j721e-esm"; 278 reg = <0x0 0x420000 0x0 0x1000>; 279 bootph-pre-ram; 280 /* Interrupt sources: rti0, rti1, wrti0, rti4, rti2, rti3 */ 281 ti,esm-pins = <192>, <193>, <195>, <204>, <209>, <210>; 282 }; 283 284 main_timer0: timer@2400000 { 285 compatible = "ti,am654-timer"; 286 reg = <0x00 0x2400000 0x00 0x400>; 287 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 288 clocks = <&k3_clks 36 2>; 289 clock-names = "fck"; 290 assigned-clocks = <&k3_clks 36 2>; 291 assigned-clock-parents = <&k3_clks 36 3>; 292 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 293 ti,timer-pwm; 294 bootph-all; 295 }; 296 297 main_timer1: timer@2410000 { 298 compatible = "ti,am654-timer"; 299 reg = <0x00 0x2410000 0x00 0x400>; 300 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&k3_clks 37 2>; 302 clock-names = "fck"; 303 assigned-clocks = <&k3_clks 37 2>; 304 assigned-clock-parents = <&k3_clks 37 3>; 305 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 306 ti,timer-pwm; 307 }; 308 309 main_timer2: timer@2420000 { 310 compatible = "ti,am654-timer"; 311 reg = <0x00 0x2420000 0x00 0x400>; 312 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&k3_clks 38 2>; 314 clock-names = "fck"; 315 assigned-clocks = <&k3_clks 38 2>; 316 assigned-clock-parents = <&k3_clks 38 3>; 317 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 318 ti,timer-pwm; 319 }; 320 321 main_timer3: timer@2430000 { 322 compatible = "ti,am654-timer"; 323 reg = <0x00 0x2430000 0x00 0x400>; 324 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 325 clocks = <&k3_clks 39 2>; 326 clock-names = "fck"; 327 assigned-clocks = <&k3_clks 39 2>; 328 assigned-clock-parents = <&k3_clks 39 3>; 329 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 330 ti,timer-pwm; 331 }; 332 333 main_timer4: timer@2440000 { 334 compatible = "ti,am654-timer"; 335 reg = <0x00 0x2440000 0x00 0x400>; 336 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 337 clocks = <&k3_clks 40 2>; 338 clock-names = "fck"; 339 assigned-clocks = <&k3_clks 40 2>; 340 assigned-clock-parents = <&k3_clks 40 3>; 341 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 342 ti,timer-pwm; 343 }; 344 345 main_timer5: timer@2450000 { 346 compatible = "ti,am654-timer"; 347 reg = <0x00 0x2450000 0x00 0x400>; 348 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&k3_clks 41 2>; 350 clock-names = "fck"; 351 assigned-clocks = <&k3_clks 41 2>; 352 assigned-clock-parents = <&k3_clks 41 3>; 353 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 354 ti,timer-pwm; 355 }; 356 357 main_timer6: timer@2460000 { 358 compatible = "ti,am654-timer"; 359 reg = <0x00 0x2460000 0x00 0x400>; 360 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 361 clocks = <&k3_clks 42 2>; 362 clock-names = "fck"; 363 assigned-clocks = <&k3_clks 42 2>; 364 assigned-clock-parents = <&k3_clks 42 3>; 365 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 366 ti,timer-pwm; 367 }; 368 369 main_timer7: timer@2470000 { 370 compatible = "ti,am654-timer"; 371 reg = <0x00 0x2470000 0x00 0x400>; 372 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&k3_clks 43 2>; 374 clock-names = "fck"; 375 assigned-clocks = <&k3_clks 43 2>; 376 assigned-clock-parents = <&k3_clks 43 3>; 377 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 378 ti,timer-pwm; 379 }; 380 381 main_uart0: serial@2800000 { 382 compatible = "ti,am64-uart", "ti,am654-uart"; 383 reg = <0x00 0x02800000 0x00 0x100>; 384 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 385 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 386 clocks = <&k3_clks 146 0>; 387 clock-names = "fclk"; 388 status = "disabled"; 389 }; 390 391 main_uart1: serial@2810000 { 392 compatible = "ti,am64-uart", "ti,am654-uart"; 393 reg = <0x00 0x02810000 0x00 0x100>; 394 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 395 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 396 clocks = <&k3_clks 152 0>; 397 clock-names = "fclk"; 398 status = "disabled"; 399 }; 400 401 main_uart2: serial@2820000 { 402 compatible = "ti,am64-uart", "ti,am654-uart"; 403 reg = <0x00 0x02820000 0x00 0x100>; 404 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 405 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 406 clocks = <&k3_clks 153 0>; 407 clock-names = "fclk"; 408 status = "disabled"; 409 }; 410 411 main_uart3: serial@2830000 { 412 compatible = "ti,am64-uart", "ti,am654-uart"; 413 reg = <0x00 0x02830000 0x00 0x100>; 414 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 415 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 416 clocks = <&k3_clks 154 0>; 417 clock-names = "fclk"; 418 status = "disabled"; 419 }; 420 421 main_uart4: serial@2840000 { 422 compatible = "ti,am64-uart", "ti,am654-uart"; 423 reg = <0x00 0x02840000 0x00 0x100>; 424 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 425 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 426 clocks = <&k3_clks 155 0>; 427 clock-names = "fclk"; 428 status = "disabled"; 429 }; 430 431 main_uart5: serial@2850000 { 432 compatible = "ti,am64-uart", "ti,am654-uart"; 433 reg = <0x00 0x02850000 0x00 0x100>; 434 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 435 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 436 clocks = <&k3_clks 156 0>; 437 clock-names = "fclk"; 438 status = "disabled"; 439 }; 440 441 main_uart6: serial@2860000 { 442 compatible = "ti,am64-uart", "ti,am654-uart"; 443 reg = <0x00 0x02860000 0x00 0x100>; 444 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 445 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 446 clocks = <&k3_clks 158 0>; 447 clock-names = "fclk"; 448 status = "disabled"; 449 }; 450 451 main_i2c0: i2c@20000000 { 452 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 453 reg = <0x00 0x20000000 0x00 0x100>; 454 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 458 clocks = <&k3_clks 102 2>; 459 clock-names = "fck"; 460 status = "disabled"; 461 }; 462 463 main_i2c1: i2c@20010000 { 464 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 465 reg = <0x00 0x20010000 0x00 0x100>; 466 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 470 clocks = <&k3_clks 103 2>; 471 clock-names = "fck"; 472 status = "disabled"; 473 }; 474 475 main_i2c2: i2c@20020000 { 476 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 477 reg = <0x00 0x20020000 0x00 0x100>; 478 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 482 clocks = <&k3_clks 104 2>; 483 clock-names = "fck"; 484 status = "disabled"; 485 }; 486 487 main_i2c3: i2c@20030000 { 488 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 489 reg = <0x00 0x20030000 0x00 0x100>; 490 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 494 clocks = <&k3_clks 105 2>; 495 clock-names = "fck"; 496 status = "disabled"; 497 }; 498 499 main_spi0: spi@20100000 { 500 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 501 reg = <0x00 0x20100000 0x00 0x400>; 502 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 506 clocks = <&k3_clks 141 0>; 507 status = "disabled"; 508 }; 509 510 main_spi1: spi@20110000 { 511 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 512 reg = <0x00 0x20110000 0x00 0x400>; 513 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 517 clocks = <&k3_clks 142 0>; 518 status = "disabled"; 519 }; 520 521 main_spi2: spi@20120000 { 522 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 523 reg = <0x00 0x20120000 0x00 0x400>; 524 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 525 #address-cells = <1>; 526 #size-cells = <0>; 527 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 528 clocks = <&k3_clks 143 0>; 529 status = "disabled"; 530 }; 531 532 main_gpio_intr: interrupt-controller@a00000 { 533 compatible = "ti,sci-intr"; 534 reg = <0x00 0x00a00000 0x00 0x800>; 535 ti,intr-trigger-type = <1>; 536 interrupt-controller; 537 interrupt-parent = <&gic500>; 538 #interrupt-cells = <1>; 539 ti,sci = <&dmsc>; 540 ti,sci-dev-id = <3>; 541 ti,interrupt-ranges = <0 32 16>; 542 status = "disabled"; 543 }; 544 545 main_gpio0: gpio@600000 { 546 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 547 reg = <0x00 0x00600000 0x0 0x100>; 548 gpio-controller; 549 #gpio-cells = <2>; 550 interrupt-parent = <&main_gpio_intr>; 551 interrupts = <190>, <191>, <192>, 552 <193>, <194>, <195>; 553 interrupt-controller; 554 #interrupt-cells = <2>; 555 ti,ngpio = <92>; 556 ti,davinci-gpio-unbanked = <0>; 557 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 558 clocks = <&k3_clks 77 0>; 559 clock-names = "gpio"; 560 status = "disabled"; 561 }; 562 563 main_gpio1: gpio@601000 { 564 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 565 reg = <0x00 0x00601000 0x0 0x100>; 566 gpio-controller; 567 #gpio-cells = <2>; 568 interrupt-parent = <&main_gpio_intr>; 569 interrupts = <180>, <181>, <182>, 570 <183>, <184>, <185>; 571 interrupt-controller; 572 #interrupt-cells = <2>; 573 ti,ngpio = <52>; 574 ti,davinci-gpio-unbanked = <0>; 575 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 576 clocks = <&k3_clks 78 0>; 577 clock-names = "gpio"; 578 status = "disabled"; 579 }; 580 581 sdhci0: mmc@fa10000 { 582 compatible = "ti,am62-sdhci"; 583 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; 584 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 585 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 586 clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; 587 clock-names = "clk_ahb", "clk_xin"; 588 bus-width = <8>; 589 mmc-hs200-1_8v; 590 ti,clkbuf-sel = <0x7>; 591 ti,otap-del-sel-legacy = <0x0>; 592 ti,otap-del-sel-mmc-hs = <0x0>; 593 ti,otap-del-sel-hs200 = <0x6>; 594 status = "disabled"; 595 }; 596 597 sdhci1: mmc@fa00000 { 598 compatible = "ti,am62-sdhci"; 599 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; 600 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 601 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 602 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; 603 clock-names = "clk_ahb", "clk_xin"; 604 bus-width = <4>; 605 ti,clkbuf-sel = <0x7>; 606 ti,otap-del-sel-legacy = <0x0>; 607 ti,otap-del-sel-sd-hs = <0x0>; 608 ti,otap-del-sel-sdr12 = <0xf>; 609 ti,otap-del-sel-sdr25 = <0xf>; 610 ti,otap-del-sel-sdr50 = <0xc>; 611 ti,otap-del-sel-sdr104 = <0x6>; 612 ti,otap-del-sel-ddr50 = <0x9>; 613 ti,itap-del-sel-legacy = <0x0>; 614 ti,itap-del-sel-sd-hs = <0x0>; 615 ti,itap-del-sel-sdr12 = <0x0>; 616 ti,itap-del-sel-sdr25 = <0x0>; 617 status = "disabled"; 618 }; 619 620 sdhci2: mmc@fa20000 { 621 compatible = "ti,am62-sdhci"; 622 reg = <0x00 0xfa20000 0x00 0x260>, <0x00 0xfa28000 0x00 0x134>; 623 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 624 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 625 clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; 626 clock-names = "clk_ahb", "clk_xin"; 627 bus-width = <4>; 628 ti,clkbuf-sel = <0x7>; 629 ti,otap-del-sel-legacy = <0x0>; 630 ti,otap-del-sel-sd-hs = <0x0>; 631 ti,otap-del-sel-sdr12 = <0xf>; 632 ti,otap-del-sel-sdr25 = <0xf>; 633 ti,otap-del-sel-sdr50 = <0xc>; 634 ti,otap-del-sel-sdr104 = <0x6>; 635 ti,otap-del-sel-ddr50 = <0x9>; 636 ti,itap-del-sel-legacy = <0x0>; 637 ti,itap-del-sel-sd-hs = <0x0>; 638 ti,itap-del-sel-sdr12 = <0x0>; 639 ti,itap-del-sel-sdr25 = <0x0>; 640 status = "disabled"; 641 }; 642 643 usbss0: dwc3-usb@f900000 { 644 compatible = "ti,am62-usb"; 645 reg = <0x00 0x0f900000 0x00 0x800>, 646 <0x00 0x0f908000 0x00 0x400>; 647 clocks = <&k3_clks 161 3>; 648 clock-names = "ref"; 649 ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>; 650 #address-cells = <2>; 651 #size-cells = <2>; 652 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 653 ranges; 654 status = "disabled"; 655 656 usb0: usb@31000000 { 657 compatible = "snps,dwc3"; 658 reg = <0x00 0x31000000 0x00 0x50000>; 659 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 660 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 661 interrupt-names = "host", "peripheral"; 662 maximum-speed = "high-speed"; 663 dr_mode = "otg"; 664 bootph-all; 665 snps,usb2-gadget-lpm-disable; 666 snps,usb2-lpm-disable; 667 }; 668 }; 669 670 usbss1: dwc3-usb@f910000 { 671 compatible = "ti,am62-usb"; 672 reg = <0x00 0x0f910000 0x00 0x800>, 673 <0x00 0x0f918000 0x00 0x400>; 674 clocks = <&k3_clks 162 3>; 675 clock-names = "ref"; 676 ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>; 677 #address-cells = <2>; 678 #size-cells = <2>; 679 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 680 ranges; 681 status = "disabled"; 682 683 usb1: usb@31100000 { 684 compatible = "snps,dwc3"; 685 reg = <0x00 0x31100000 0x00 0x50000>; 686 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 687 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 688 interrupt-names = "host", "peripheral"; 689 maximum-speed = "high-speed"; 690 dr_mode = "otg"; 691 snps,usb2-gadget-lpm-disable; 692 snps,usb2-lpm-disable; 693 }; 694 }; 695 696 fss: bus@fc00000 { 697 compatible = "simple-bus"; 698 reg = <0x00 0x0fc00000 0x00 0x70000>; 699 #address-cells = <2>; 700 #size-cells = <2>; 701 ranges; 702 status = "disabled"; 703 704 ospi0: spi@fc40000 { 705 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 706 reg = <0x00 0x0fc40000 0x00 0x100>, 707 <0x05 0x00000000 0x01 0x00000000>; 708 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 709 cdns,fifo-depth = <256>; 710 cdns,fifo-width = <4>; 711 cdns,trigger-address = <0x0>; 712 clocks = <&k3_clks 75 7>; 713 assigned-clocks = <&k3_clks 75 7>; 714 assigned-clock-parents = <&k3_clks 75 8>; 715 assigned-clock-rates = <166666666>; 716 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 717 #address-cells = <1>; 718 #size-cells = <0>; 719 }; 720 }; 721 722 cpsw3g: ethernet@8000000 { 723 compatible = "ti,am642-cpsw-nuss"; 724 #address-cells = <2>; 725 #size-cells = <2>; 726 reg = <0x0 0x8000000 0x0 0x200000>; 727 reg-names = "cpsw_nuss"; 728 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>; 729 clocks = <&k3_clks 13 0>; 730 assigned-clocks = <&k3_clks 13 3>; 731 assigned-clock-parents = <&k3_clks 13 11>; 732 clock-names = "fck"; 733 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 734 status = "disabled"; 735 736 dmas = <&main_pktdma 0xc600 15>, 737 <&main_pktdma 0xc601 15>, 738 <&main_pktdma 0xc602 15>, 739 <&main_pktdma 0xc603 15>, 740 <&main_pktdma 0xc604 15>, 741 <&main_pktdma 0xc605 15>, 742 <&main_pktdma 0xc606 15>, 743 <&main_pktdma 0xc607 15>, 744 <&main_pktdma 0x4600 15>; 745 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 746 "tx7", "rx"; 747 748 ethernet-ports { 749 #address-cells = <1>; 750 #size-cells = <0>; 751 752 cpsw_port1: port@1 { 753 reg = <1>; 754 ti,mac-only; 755 label = "port1"; 756 phys = <&phy_gmii_sel 1>; 757 mac-address = [00 00 00 00 00 00]; 758 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; 759 bootph-all; 760 }; 761 762 cpsw_port2: port@2 { 763 reg = <2>; 764 ti,mac-only; 765 label = "port2"; 766 phys = <&phy_gmii_sel 2>; 767 mac-address = [00 00 00 00 00 00]; 768 }; 769 }; 770 771 cpsw3g_mdio: mdio@f00 { 772 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 773 reg = <0x0 0xf00 0x0 0x100>; 774 #address-cells = <1>; 775 #size-cells = <0>; 776 clocks = <&k3_clks 13 0>; 777 clock-names = "fck"; 778 bus_freq = <1000000>; 779 bootph-all; 780 }; 781 782 cpts@3d000 { 783 compatible = "ti,j721e-cpts"; 784 reg = <0x0 0x3d000 0x0 0x400>; 785 clocks = <&k3_clks 13 3>; 786 clock-names = "cpts"; 787 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 788 interrupt-names = "cpts"; 789 ti,cpts-ext-ts-inputs = <4>; 790 ti,cpts-periodic-outputs = <2>; 791 }; 792 }; 793 794 hwspinlock: spinlock@2a000000 { 795 compatible = "ti,am64-hwspinlock"; 796 reg = <0x00 0x2a000000 0x00 0x1000>; 797 #hwlock-cells = <1>; 798 }; 799 800 mailbox0_cluster0: mailbox@29000000 { 801 compatible = "ti,am64-mailbox"; 802 reg = <0x00 0x29000000 0x00 0x200>; 803 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 804 #mbox-cells = <1>; 805 ti,mbox-num-users = <4>; 806 ti,mbox-num-fifos = <16>; 807 status = "disabled"; 808 }; 809 810 mailbox0_cluster1: mailbox@29010000 { 811 compatible = "ti,am64-mailbox"; 812 reg = <0x00 0x29010000 0x00 0x200>; 813 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 814 #mbox-cells = <1>; 815 ti,mbox-num-users = <4>; 816 ti,mbox-num-fifos = <16>; 817 status = "disabled"; 818 }; 819 820 mailbox0_cluster2: mailbox@29020000 { 821 compatible = "ti,am64-mailbox"; 822 reg = <0x00 0x29020000 0x00 0x200>; 823 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 824 #mbox-cells = <1>; 825 ti,mbox-num-users = <4>; 826 ti,mbox-num-fifos = <16>; 827 status = "disabled"; 828 }; 829 830 mailbox0_cluster3: mailbox@29030000 { 831 compatible = "ti,am64-mailbox"; 832 reg = <0x00 0x29030000 0x00 0x200>; 833 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 834 #mbox-cells = <1>; 835 ti,mbox-num-users = <4>; 836 ti,mbox-num-fifos = <16>; 837 status = "disabled"; 838 }; 839 840 main_mcan0: can@20701000 { 841 compatible = "bosch,m_can"; 842 reg = <0x00 0x20701000 0x00 0x200>, 843 <0x00 0x20708000 0x00 0x8000>; 844 reg-names = "m_can", "message_ram"; 845 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 846 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; 847 clock-names = "hclk", "cclk"; 848 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 849 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 850 interrupt-names = "int0", "int1"; 851 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 852 status = "disabled"; 853 }; 854 855 main_rti0: watchdog@e000000 { 856 compatible = "ti,j7-rti-wdt"; 857 reg = <0x00 0x0e000000 0x00 0x100>; 858 clocks = <&k3_clks 125 0>; 859 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 860 assigned-clocks = <&k3_clks 125 0>; 861 assigned-clock-parents = <&k3_clks 125 2>; 862 }; 863 864 main_rti1: watchdog@e010000 { 865 compatible = "ti,j7-rti-wdt"; 866 reg = <0x00 0x0e010000 0x00 0x100>; 867 clocks = <&k3_clks 126 0>; 868 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; 869 assigned-clocks = <&k3_clks 126 0>; 870 assigned-clock-parents = <&k3_clks 126 2>; 871 }; 872 873 main_rti2: watchdog@e020000 { 874 compatible = "ti,j7-rti-wdt"; 875 reg = <0x00 0x0e020000 0x00 0x100>; 876 clocks = <&k3_clks 127 0>; 877 power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; 878 assigned-clocks = <&k3_clks 127 0>; 879 assigned-clock-parents = <&k3_clks 127 2>; 880 }; 881 882 main_rti3: watchdog@e030000 { 883 compatible = "ti,j7-rti-wdt"; 884 reg = <0x00 0x0e030000 0x00 0x100>; 885 clocks = <&k3_clks 128 0>; 886 power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; 887 assigned-clocks = <&k3_clks 128 0>; 888 assigned-clock-parents = <&k3_clks 128 2>; 889 }; 890 891 main_rti4: watchdog@e040000 { 892 compatible = "ti,j7-rti-wdt"; 893 reg = <0x00 0x0e040000 0x00 0x100>; 894 clocks = <&k3_clks 205 0>; 895 power-domains = <&k3_pds 205 TI_SCI_PD_EXCLUSIVE>; 896 assigned-clocks = <&k3_clks 205 0>; 897 assigned-clock-parents = <&k3_clks 205 2>; 898 }; 899 900 epwm0: pwm@23000000 { 901 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 902 #pwm-cells = <3>; 903 reg = <0x00 0x23000000 0x00 0x100>; 904 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 905 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 906 clock-names = "tbclk", "fck"; 907 status = "disabled"; 908 }; 909 910 epwm1: pwm@23010000 { 911 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 912 #pwm-cells = <3>; 913 reg = <0x00 0x23010000 0x00 0x100>; 914 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 915 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 916 clock-names = "tbclk", "fck"; 917 status = "disabled"; 918 }; 919 920 epwm2: pwm@23020000 { 921 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 922 #pwm-cells = <3>; 923 reg = <0x00 0x23020000 0x00 0x100>; 924 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 925 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 926 clock-names = "tbclk", "fck"; 927 status = "disabled"; 928 }; 929 930 ecap0: pwm@23100000 { 931 compatible = "ti,am3352-ecap"; 932 #pwm-cells = <3>; 933 reg = <0x00 0x23100000 0x00 0x100>; 934 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 935 clocks = <&k3_clks 51 0>; 936 clock-names = "fck"; 937 status = "disabled"; 938 }; 939 940 ecap1: pwm@23110000 { 941 compatible = "ti,am3352-ecap"; 942 #pwm-cells = <3>; 943 reg = <0x00 0x23110000 0x00 0x100>; 944 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 945 clocks = <&k3_clks 52 0>; 946 clock-names = "fck"; 947 status = "disabled"; 948 }; 949 950 ecap2: pwm@23120000 { 951 compatible = "ti,am3352-ecap"; 952 #pwm-cells = <3>; 953 reg = <0x00 0x23120000 0x00 0x100>; 954 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 955 clocks = <&k3_clks 53 0>; 956 clock-names = "fck"; 957 status = "disabled"; 958 }; 959 960 eqep0: counter@23200000 { 961 compatible = "ti,am62-eqep"; 962 reg = <0x00 0x23200000 0x00 0x100>; 963 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; 964 clocks = <&k3_clks 59 0>; 965 interrupts = <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>; 966 status = "disabled"; 967 }; 968 969 eqep1: counter@23210000 { 970 compatible = "ti,am62-eqep"; 971 reg = <0x00 0x23210000 0x00 0x100>; 972 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; 973 clocks = <&k3_clks 60 0>; 974 interrupts = <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>; 975 status = "disabled"; 976 }; 977 978 eqep2: counter@23220000 { 979 compatible = "ti,am62-eqep"; 980 reg = <0x00 0x23220000 0x00 0x100>; 981 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 982 clocks = <&k3_clks 62 0>; 983 interrupts = <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>; 984 status = "disabled"; 985 }; 986 987 mcasp0: audio-controller@2b00000 { 988 compatible = "ti,am33xx-mcasp-audio"; 989 reg = <0x00 0x02b00000 0x00 0x2000>, 990 <0x00 0x02b08000 0x00 0x400>; 991 reg-names = "mpu", "dat"; 992 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 994 interrupt-names = "tx", "rx"; 995 996 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; 997 dma-names = "tx", "rx"; 998 999 clocks = <&k3_clks 190 0>; 1000 clock-names = "fck"; 1001 assigned-clocks = <&k3_clks 190 0>; 1002 assigned-clock-parents = <&k3_clks 190 2>; 1003 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 1004 status = "disabled"; 1005 }; 1006 1007 mcasp1: audio-controller@2b10000 { 1008 compatible = "ti,am33xx-mcasp-audio"; 1009 reg = <0x00 0x02b10000 0x00 0x2000>, 1010 <0x00 0x02b18000 0x00 0x400>; 1011 reg-names = "mpu", "dat"; 1012 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1013 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 1014 interrupt-names = "tx", "rx"; 1015 1016 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; 1017 dma-names = "tx", "rx"; 1018 1019 clocks = <&k3_clks 191 0>; 1020 clock-names = "fck"; 1021 assigned-clocks = <&k3_clks 191 0>; 1022 assigned-clock-parents = <&k3_clks 191 2>; 1023 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1024 status = "disabled"; 1025 }; 1026 1027 mcasp2: audio-controller@2b20000 { 1028 compatible = "ti,am33xx-mcasp-audio"; 1029 reg = <0x00 0x02b20000 0x00 0x2000>, 1030 <0x00 0x02b28000 0x00 0x400>; 1031 reg-names = "mpu", "dat"; 1032 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1033 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1034 interrupt-names = "tx", "rx"; 1035 1036 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; 1037 dma-names = "tx", "rx"; 1038 1039 clocks = <&k3_clks 192 0>; 1040 clock-names = "fck"; 1041 assigned-clocks = <&k3_clks 192 0>; 1042 assigned-clock-parents = <&k3_clks 192 2>; 1043 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1044 status = "disabled"; 1045 }; 1046 1047 ti_csi2rx0: ticsi2rx@30102000 { 1048 compatible = "ti,j721e-csi2rx-shim"; 1049 dmas = <&main_bcdma_csi 0 0x5000 0>; 1050 dma-names = "rx0"; 1051 reg = <0x00 0x30102000 0x00 0x1000>; 1052 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1053 #address-cells = <2>; 1054 #size-cells = <2>; 1055 ranges; 1056 status = "disabled"; 1057 1058 cdns_csi2rx0: csi-bridge@30101000 { 1059 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 1060 reg = <0x00 0x30101000 0x00 0x1000>; 1061 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1062 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1063 interrupt-names = "error_irq", "irq"; 1064 clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, 1065 <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; 1066 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 1067 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 1068 phys = <&dphy0>; 1069 phy-names = "dphy"; 1070 1071 ports { 1072 #address-cells = <1>; 1073 #size-cells = <0>; 1074 1075 csi0_port0: port@0 { 1076 reg = <0>; 1077 status = "disabled"; 1078 }; 1079 1080 csi0_port1: port@1 { 1081 reg = <1>; 1082 status = "disabled"; 1083 }; 1084 1085 csi0_port2: port@2 { 1086 reg = <2>; 1087 status = "disabled"; 1088 }; 1089 1090 csi0_port3: port@3 { 1091 reg = <3>; 1092 status = "disabled"; 1093 }; 1094 1095 csi0_port4: port@4 { 1096 reg = <4>; 1097 status = "disabled"; 1098 }; 1099 }; 1100 }; 1101 }; 1102 1103 dphy0: phy@30110000 { 1104 compatible = "cdns,dphy-rx"; 1105 reg = <0x00 0x30110000 0x00 0x1100>; 1106 #phy-cells = <0>; 1107 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1108 status = "disabled"; 1109 }; 1110 1111 dss: dss@30200000 { 1112 compatible = "ti,am62a7-dss"; 1113 reg = <0x00 0x30200000 0x00 0x1000>, /* common */ 1114 <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ 1115 <0x00 0x30206000 0x00 0x1000>, /* vid */ 1116 <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ 1117 <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ 1118 <0x00 0x3020a000 0x00 0x1000>, /* vp1: Tied OFF in the SoC */ 1119 <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ 1120 <0x00 0x30201000 0x00 0x1000>; /* common1 */ 1121 reg-names = "common", "vidl1", "vid", 1122 "ovr1", "ovr2", "vp1", "vp2", "common1"; 1123 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; 1124 clocks = <&k3_clks 186 6>, 1125 <&k3_clks 186 0>, 1126 <&k3_clks 186 2>; 1127 clock-names = "fck", "vp1", "vp2"; 1128 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1129 status = "disabled"; 1130 1131 dss_ports: ports { 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 }; 1135 }; 1136 1137 vpu: video-codec@30210000 { 1138 compatible = "ti,j721s2-wave521c", "cnm,wave521c"; 1139 reg = <0x00 0x30210000 0x00 0x10000>; 1140 clocks = <&k3_clks 204 2>; 1141 power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; 1142 }; 1143 1144 c7x_0: dsp@7e000000 { 1145 compatible = "ti,am62a-c7xv-dsp"; 1146 reg = <0x00 0x7e000000 0x00 0x00100000>; 1147 reg-names = "l2sram"; 1148 resets = <&k3_reset 208 1>; 1149 firmware-name = "am62a-c71_0-fw"; 1150 ti,sci = <&dmsc>; 1151 ti,sci-dev-id = <208>; 1152 ti,sci-proc-ids = <0x04 0xff>; 1153 status = "disabled"; 1154 }; 1155 1156 e5010: jpeg-encoder@fd20000 { 1157 compatible = "ti,am62a-jpeg-enc", "img,e5010-jpeg-enc"; 1158 reg = <0x00 0xfd20000 0x00 0x100>, 1159 <0x00 0xfd20200 0x00 0x200>; 1160 reg-names = "core", "mmu"; 1161 clocks = <&k3_clks 201 0>; 1162 power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>; 1163 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1164 }; 1165}; 1166