1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for AM62A SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 oc_sram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x00 0x70000000 0x00 0x10000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x0 0x00 0x70000000 0x10000>; 15 }; 16 17 gic500: interrupt-controller@1800000 { 18 compatible = "arm,gic-v3"; 19 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 20 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 21 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 22 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 23 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 24 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 25 #address-cells = <2>; 26 #size-cells = <2>; 27 ranges; 28 #interrupt-cells = <3>; 29 interrupt-controller; 30 /* 31 * vcpumntirq: 32 * virtual CPU interface maintenance interrupt 33 */ 34 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 35 36 gic_its: msi-controller@1820000 { 37 compatible = "arm,gic-v3-its"; 38 reg = <0x00 0x01820000 0x00 0x10000>; 39 socionext,synquacer-pre-its = <0x1000000 0x400000>; 40 msi-controller; 41 #msi-cells = <1>; 42 }; 43 }; 44 45 main_conf: bus@100000 { 46 compatible = "simple-bus"; 47 #address-cells = <1>; 48 #size-cells = <1>; 49 ranges = <0x00 0x00 0x00100000 0x20000>; 50 51 phy_gmii_sel: phy@4044 { 52 compatible = "ti,am654-phy-gmii-sel"; 53 reg = <0x4044 0x8>; 54 #phy-cells = <1>; 55 }; 56 57 epwm_tbclk: clock-controller@4130 { 58 compatible = "ti,am62-epwm-tbclk"; 59 reg = <0x4130 0x4>; 60 #clock-cells = <1>; 61 }; 62 }; 63 64 dmss: bus@48000000 { 65 compatible = "simple-bus"; 66 #address-cells = <2>; 67 #size-cells = <2>; 68 dma-ranges; 69 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>; 70 71 ti,sci-dev-id = <25>; 72 73 secure_proxy_main: mailbox@4d000000 { 74 compatible = "ti,am654-secure-proxy"; 75 reg = <0x00 0x4d000000 0x00 0x80000>, 76 <0x00 0x4a600000 0x00 0x80000>, 77 <0x00 0x4a400000 0x00 0x80000>; 78 reg-names = "target_data", "rt", "scfg"; 79 #mbox-cells = <1>; 80 interrupt-names = "rx_012"; 81 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 82 }; 83 84 inta_main_dmss: interrupt-controller@48000000 { 85 compatible = "ti,sci-inta"; 86 reg = <0x00 0x48000000 0x00 0x100000>; 87 #interrupt-cells = <0>; 88 interrupt-controller; 89 interrupt-parent = <&gic500>; 90 msi-controller; 91 ti,sci = <&dmsc>; 92 ti,sci-dev-id = <28>; 93 ti,interrupt-ranges = <6 70 34>; 94 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 95 }; 96 97 main_bcdma: dma-controller@485c0100 { 98 compatible = "ti,am64-dmss-bcdma"; 99 reg = <0x00 0x485c0100 0x00 0x100>, 100 <0x00 0x4c000000 0x00 0x20000>, 101 <0x00 0x4a820000 0x00 0x20000>, 102 <0x00 0x4aa40000 0x00 0x20000>, 103 <0x00 0x4bc00000 0x00 0x100000>, 104 <0x00 0x48600000 0x00 0x8000>, 105 <0x00 0x484a4000 0x00 0x2000>, 106 <0x00 0x484c2000 0x00 0x2000>, 107 <0x00 0x48420000 0x00 0x2000>; 108 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt", 109 "ring", "tchan", "rchan", "bchan"; 110 msi-parent = <&inta_main_dmss>; 111 #dma-cells = <3>; 112 ti,sci = <&dmsc>; 113 ti,sci-dev-id = <26>; 114 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 115 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 116 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 117 }; 118 119 main_pktdma: dma-controller@485c0000 { 120 compatible = "ti,am64-dmss-pktdma"; 121 reg = <0x00 0x485c0000 0x00 0x100>, 122 <0x00 0x4a800000 0x00 0x20000>, 123 <0x00 0x4aa00000 0x00 0x40000>, 124 <0x00 0x4b800000 0x00 0x400000>, 125 <0x00 0x485e0000 0x00 0x10000>, 126 <0x00 0x484a0000 0x00 0x2000>, 127 <0x00 0x484c0000 0x00 0x2000>, 128 <0x00 0x48430000 0x00 0x1000>; 129 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", 130 "ring", "tchan", "rchan", "rflow"; 131 msi-parent = <&inta_main_dmss>; 132 #dma-cells = <2>; 133 ti,sci = <&dmsc>; 134 ti,sci-dev-id = <30>; 135 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 136 <0x24>, /* CPSW_TX_CHAN */ 137 <0x25>, /* SAUL_TX_0_CHAN */ 138 <0x26>; /* SAUL_TX_1_CHAN */ 139 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 140 <0x11>, /* RING_CPSW_TX_CHAN */ 141 <0x12>, /* RING_SAUL_TX_0_CHAN */ 142 <0x13>; /* RING_SAUL_TX_1_CHAN */ 143 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 144 <0x2b>, /* CPSW_RX_CHAN */ 145 <0x2d>, /* SAUL_RX_0_CHAN */ 146 <0x2f>, /* SAUL_RX_1_CHAN */ 147 <0x31>, /* SAUL_RX_2_CHAN */ 148 <0x33>; /* SAUL_RX_3_CHAN */ 149 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 150 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 151 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 152 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ 153 }; 154 }; 155 156 dmss_csi: bus@4e000000 { 157 compatible = "simple-bus"; 158 #address-cells = <2>; 159 #size-cells = <2>; 160 dma-ranges; 161 ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x300000>; 162 163 ti,sci-dev-id = <198>; 164 165 inta_main_dmss_csi: interrupt-controller@4e0a0000 { 166 compatible = "ti,sci-inta"; 167 reg = <0x00 0x4e0a0000 0x00 0x8000>; 168 #interrupt-cells = <0>; 169 interrupt-controller; 170 interrupt-parent = <&gic500>; 171 msi-controller; 172 ti,sci = <&dmsc>; 173 ti,sci-dev-id = <200>; 174 ti,interrupt-ranges = <0 237 8>; 175 ti,unmapped-event-sources = <&main_bcdma_csi>; 176 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 177 }; 178 179 main_bcdma_csi: dma-controller@4e230000 { 180 compatible = "ti,am62a-dmss-bcdma-csirx"; 181 reg = <0x00 0x4e230000 0x00 0x100>, 182 <0x00 0x4e180000 0x00 0x8000>, 183 <0x00 0x4e100000 0x00 0x10000>; 184 reg-names = "gcfg", "rchanrt", "ringrt"; 185 msi-parent = <&inta_main_dmss_csi>; 186 #dma-cells = <3>; 187 ti,sci = <&dmsc>; 188 ti,sci-dev-id = <199>; 189 ti,sci-rm-range-rchan = <0x21>; 190 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 191 }; 192 }; 193 194 dmsc: system-controller@44043000 { 195 compatible = "ti,k2g-sci"; 196 reg = <0x00 0x44043000 0x00 0xfe0>; 197 reg-names = "debug_messages"; 198 ti,host-id = <12>; 199 mbox-names = "rx", "tx"; 200 mboxes = <&secure_proxy_main 12>, 201 <&secure_proxy_main 13>; 202 203 k3_pds: power-controller { 204 compatible = "ti,sci-pm-domain"; 205 #power-domain-cells = <2>; 206 }; 207 208 k3_clks: clock-controller { 209 compatible = "ti,k2g-sci-clk"; 210 #clock-cells = <2>; 211 }; 212 213 k3_reset: reset-controller { 214 compatible = "ti,sci-reset"; 215 #reset-cells = <2>; 216 }; 217 }; 218 219 secure_proxy_sa3: mailbox@43600000 { 220 compatible = "ti,am654-secure-proxy"; 221 #mbox-cells = <1>; 222 reg-names = "target_data", "rt", "scfg"; 223 reg = <0x00 0x43600000 0x00 0x10000>, 224 <0x00 0x44880000 0x00 0x20000>, 225 <0x00 0x44860000 0x00 0x20000>; 226 /* 227 * Marked Disabled: 228 * Node is incomplete as it is meant for bootloaders and 229 * firmware on non-MPU processors 230 */ 231 status = "disabled"; 232 }; 233 234 main_pmx0: pinctrl@f4000 { 235 compatible = "pinctrl-single"; 236 reg = <0x00 0xf4000 0x00 0x2ac>; 237 #pinctrl-cells = <1>; 238 pinctrl-single,register-width = <32>; 239 pinctrl-single,function-mask = <0xffffffff>; 240 }; 241 242 main_timer0: timer@2400000 { 243 compatible = "ti,am654-timer"; 244 reg = <0x00 0x2400000 0x00 0x400>; 245 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&k3_clks 36 2>; 247 clock-names = "fck"; 248 assigned-clocks = <&k3_clks 36 2>; 249 assigned-clock-parents = <&k3_clks 36 3>; 250 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 251 ti,timer-pwm; 252 }; 253 254 main_timer1: timer@2410000 { 255 compatible = "ti,am654-timer"; 256 reg = <0x00 0x2410000 0x00 0x400>; 257 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&k3_clks 37 2>; 259 clock-names = "fck"; 260 assigned-clocks = <&k3_clks 37 2>; 261 assigned-clock-parents = <&k3_clks 37 3>; 262 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 263 ti,timer-pwm; 264 }; 265 266 main_timer2: timer@2420000 { 267 compatible = "ti,am654-timer"; 268 reg = <0x00 0x2420000 0x00 0x400>; 269 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&k3_clks 38 2>; 271 clock-names = "fck"; 272 assigned-clocks = <&k3_clks 38 2>; 273 assigned-clock-parents = <&k3_clks 38 3>; 274 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 275 ti,timer-pwm; 276 }; 277 278 main_timer3: timer@2430000 { 279 compatible = "ti,am654-timer"; 280 reg = <0x00 0x2430000 0x00 0x400>; 281 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 282 clocks = <&k3_clks 39 2>; 283 clock-names = "fck"; 284 assigned-clocks = <&k3_clks 39 2>; 285 assigned-clock-parents = <&k3_clks 39 3>; 286 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 287 ti,timer-pwm; 288 }; 289 290 main_timer4: timer@2440000 { 291 compatible = "ti,am654-timer"; 292 reg = <0x00 0x2440000 0x00 0x400>; 293 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&k3_clks 40 2>; 295 clock-names = "fck"; 296 assigned-clocks = <&k3_clks 40 2>; 297 assigned-clock-parents = <&k3_clks 40 3>; 298 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 299 ti,timer-pwm; 300 }; 301 302 main_timer5: timer@2450000 { 303 compatible = "ti,am654-timer"; 304 reg = <0x00 0x2450000 0x00 0x400>; 305 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&k3_clks 41 2>; 307 clock-names = "fck"; 308 assigned-clocks = <&k3_clks 41 2>; 309 assigned-clock-parents = <&k3_clks 41 3>; 310 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 311 ti,timer-pwm; 312 }; 313 314 main_timer6: timer@2460000 { 315 compatible = "ti,am654-timer"; 316 reg = <0x00 0x2460000 0x00 0x400>; 317 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&k3_clks 42 2>; 319 clock-names = "fck"; 320 assigned-clocks = <&k3_clks 42 2>; 321 assigned-clock-parents = <&k3_clks 42 3>; 322 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 323 ti,timer-pwm; 324 }; 325 326 main_timer7: timer@2470000 { 327 compatible = "ti,am654-timer"; 328 reg = <0x00 0x2470000 0x00 0x400>; 329 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 330 clocks = <&k3_clks 43 2>; 331 clock-names = "fck"; 332 assigned-clocks = <&k3_clks 43 2>; 333 assigned-clock-parents = <&k3_clks 43 3>; 334 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 335 ti,timer-pwm; 336 }; 337 338 main_uart0: serial@2800000 { 339 compatible = "ti,am64-uart", "ti,am654-uart"; 340 reg = <0x00 0x02800000 0x00 0x100>; 341 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 342 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 343 clocks = <&k3_clks 146 0>; 344 clock-names = "fclk"; 345 status = "disabled"; 346 }; 347 348 main_uart1: serial@2810000 { 349 compatible = "ti,am64-uart", "ti,am654-uart"; 350 reg = <0x00 0x02810000 0x00 0x100>; 351 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 352 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 353 clocks = <&k3_clks 152 0>; 354 clock-names = "fclk"; 355 status = "disabled"; 356 }; 357 358 main_uart2: serial@2820000 { 359 compatible = "ti,am64-uart", "ti,am654-uart"; 360 reg = <0x00 0x02820000 0x00 0x100>; 361 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 362 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 363 clocks = <&k3_clks 153 0>; 364 clock-names = "fclk"; 365 status = "disabled"; 366 }; 367 368 main_uart3: serial@2830000 { 369 compatible = "ti,am64-uart", "ti,am654-uart"; 370 reg = <0x00 0x02830000 0x00 0x100>; 371 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 372 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 373 clocks = <&k3_clks 154 0>; 374 clock-names = "fclk"; 375 status = "disabled"; 376 }; 377 378 main_uart4: serial@2840000 { 379 compatible = "ti,am64-uart", "ti,am654-uart"; 380 reg = <0x00 0x02840000 0x00 0x100>; 381 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 382 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 383 clocks = <&k3_clks 155 0>; 384 clock-names = "fclk"; 385 status = "disabled"; 386 }; 387 388 main_uart5: serial@2850000 { 389 compatible = "ti,am64-uart", "ti,am654-uart"; 390 reg = <0x00 0x02850000 0x00 0x100>; 391 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 392 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 393 clocks = <&k3_clks 156 0>; 394 clock-names = "fclk"; 395 status = "disabled"; 396 }; 397 398 main_uart6: serial@2860000 { 399 compatible = "ti,am64-uart", "ti,am654-uart"; 400 reg = <0x00 0x02860000 0x00 0x100>; 401 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 402 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 403 clocks = <&k3_clks 158 0>; 404 clock-names = "fclk"; 405 status = "disabled"; 406 }; 407 408 main_i2c0: i2c@20000000 { 409 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 410 reg = <0x00 0x20000000 0x00 0x100>; 411 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 415 clocks = <&k3_clks 102 2>; 416 clock-names = "fck"; 417 status = "disabled"; 418 }; 419 420 main_i2c1: i2c@20010000 { 421 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 422 reg = <0x00 0x20010000 0x00 0x100>; 423 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 424 #address-cells = <1>; 425 #size-cells = <0>; 426 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 427 clocks = <&k3_clks 103 2>; 428 clock-names = "fck"; 429 status = "disabled"; 430 }; 431 432 main_i2c2: i2c@20020000 { 433 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 434 reg = <0x00 0x20020000 0x00 0x100>; 435 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 436 #address-cells = <1>; 437 #size-cells = <0>; 438 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 439 clocks = <&k3_clks 104 2>; 440 clock-names = "fck"; 441 status = "disabled"; 442 }; 443 444 main_i2c3: i2c@20030000 { 445 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 446 reg = <0x00 0x20030000 0x00 0x100>; 447 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 448 #address-cells = <1>; 449 #size-cells = <0>; 450 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 451 clocks = <&k3_clks 105 2>; 452 clock-names = "fck"; 453 status = "disabled"; 454 }; 455 456 main_spi0: spi@20100000 { 457 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 458 reg = <0x00 0x20100000 0x00 0x400>; 459 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 463 clocks = <&k3_clks 141 0>; 464 status = "disabled"; 465 }; 466 467 main_spi1: spi@20110000 { 468 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 469 reg = <0x00 0x20110000 0x00 0x400>; 470 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 471 #address-cells = <1>; 472 #size-cells = <0>; 473 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 474 clocks = <&k3_clks 142 0>; 475 status = "disabled"; 476 }; 477 478 main_spi2: spi@20120000 { 479 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 480 reg = <0x00 0x20120000 0x00 0x400>; 481 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 482 #address-cells = <1>; 483 #size-cells = <0>; 484 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 485 clocks = <&k3_clks 143 0>; 486 status = "disabled"; 487 }; 488 489 main_gpio_intr: interrupt-controller@a00000 { 490 compatible = "ti,sci-intr"; 491 reg = <0x00 0x00a00000 0x00 0x800>; 492 ti,intr-trigger-type = <1>; 493 interrupt-controller; 494 interrupt-parent = <&gic500>; 495 #interrupt-cells = <1>; 496 ti,sci = <&dmsc>; 497 ti,sci-dev-id = <3>; 498 ti,interrupt-ranges = <0 32 16>; 499 status = "disabled"; 500 }; 501 502 main_gpio0: gpio@600000 { 503 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 504 reg = <0x00 0x00600000 0x0 0x100>; 505 gpio-controller; 506 #gpio-cells = <2>; 507 interrupt-parent = <&main_gpio_intr>; 508 interrupts = <190>, <191>, <192>, 509 <193>, <194>, <195>; 510 interrupt-controller; 511 #interrupt-cells = <2>; 512 ti,ngpio = <92>; 513 ti,davinci-gpio-unbanked = <0>; 514 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 515 clocks = <&k3_clks 77 0>; 516 clock-names = "gpio"; 517 status = "disabled"; 518 }; 519 520 main_gpio1: gpio@601000 { 521 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 522 reg = <0x00 0x00601000 0x0 0x100>; 523 gpio-controller; 524 #gpio-cells = <2>; 525 interrupt-parent = <&main_gpio_intr>; 526 interrupts = <180>, <181>, <182>, 527 <183>, <184>, <185>; 528 interrupt-controller; 529 #interrupt-cells = <2>; 530 ti,ngpio = <52>; 531 ti,davinci-gpio-unbanked = <0>; 532 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 533 clocks = <&k3_clks 78 0>; 534 clock-names = "gpio"; 535 status = "disabled"; 536 }; 537 538 sdhci0: mmc@fa10000 { 539 compatible = "ti,am62-sdhci"; 540 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; 541 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 542 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 543 clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; 544 clock-names = "clk_ahb", "clk_xin"; 545 assigned-clocks = <&k3_clks 57 6>; 546 assigned-clock-parents = <&k3_clks 57 8>; 547 bus-width = <8>; 548 mmc-hs200-1_8v; 549 ti,clkbuf-sel = <0x7>; 550 ti,otap-del-sel-legacy = <0x0>; 551 ti,otap-del-sel-mmc-hs = <0x0>; 552 ti,otap-del-sel-hs200 = <0x6>; 553 status = "disabled"; 554 }; 555 556 sdhci1: mmc@fa00000 { 557 compatible = "ti,am62-sdhci"; 558 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; 559 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 560 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 561 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; 562 clock-names = "clk_ahb", "clk_xin"; 563 bus-width = <4>; 564 ti,clkbuf-sel = <0x7>; 565 ti,otap-del-sel-legacy = <0x0>; 566 ti,otap-del-sel-sd-hs = <0x0>; 567 ti,otap-del-sel-sdr12 = <0xf>; 568 ti,otap-del-sel-sdr25 = <0xf>; 569 ti,otap-del-sel-sdr50 = <0xc>; 570 ti,otap-del-sel-sdr104 = <0x6>; 571 ti,otap-del-sel-ddr50 = <0x9>; 572 ti,itap-del-sel-legacy = <0x0>; 573 ti,itap-del-sel-sd-hs = <0x0>; 574 ti,itap-del-sel-sdr12 = <0x0>; 575 ti,itap-del-sel-sdr25 = <0x0>; 576 status = "disabled"; 577 }; 578 579 sdhci2: mmc@fa20000 { 580 compatible = "ti,am62-sdhci"; 581 reg = <0x00 0xfa20000 0x00 0x260>, <0x00 0xfa28000 0x00 0x134>; 582 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 583 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 584 clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; 585 clock-names = "clk_ahb", "clk_xin"; 586 bus-width = <4>; 587 ti,clkbuf-sel = <0x7>; 588 ti,otap-del-sel-legacy = <0x0>; 589 ti,otap-del-sel-sd-hs = <0x0>; 590 ti,otap-del-sel-sdr12 = <0xf>; 591 ti,otap-del-sel-sdr25 = <0xf>; 592 ti,otap-del-sel-sdr50 = <0xc>; 593 ti,otap-del-sel-sdr104 = <0x6>; 594 ti,otap-del-sel-ddr50 = <0x9>; 595 ti,itap-del-sel-legacy = <0x0>; 596 ti,itap-del-sel-sd-hs = <0x0>; 597 ti,itap-del-sel-sdr12 = <0x0>; 598 ti,itap-del-sel-sdr25 = <0x0>; 599 status = "disabled"; 600 }; 601 602 usbss0: dwc3-usb@f900000 { 603 compatible = "ti,am62-usb"; 604 reg = <0x00 0x0f900000 0x00 0x800>, 605 <0x00 0x0f908000 0x00 0x400>; 606 clocks = <&k3_clks 161 3>; 607 clock-names = "ref"; 608 ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>; 609 #address-cells = <2>; 610 #size-cells = <2>; 611 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 612 ranges; 613 status = "disabled"; 614 615 usb0: usb@31000000 { 616 compatible = "snps,dwc3"; 617 reg = <0x00 0x31000000 0x00 0x50000>; 618 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 619 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 620 interrupt-names = "host", "peripheral"; 621 maximum-speed = "high-speed"; 622 dr_mode = "otg"; 623 snps,usb2-gadget-lpm-disable; 624 snps,usb2-lpm-disable; 625 }; 626 }; 627 628 usbss1: dwc3-usb@f910000 { 629 compatible = "ti,am62-usb"; 630 reg = <0x00 0x0f910000 0x00 0x800>, 631 <0x00 0x0f918000 0x00 0x400>; 632 clocks = <&k3_clks 162 3>; 633 clock-names = "ref"; 634 ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>; 635 #address-cells = <2>; 636 #size-cells = <2>; 637 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 638 ranges; 639 status = "disabled"; 640 641 usb1: usb@31100000 { 642 compatible = "snps,dwc3"; 643 reg = <0x00 0x31100000 0x00 0x50000>; 644 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 645 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 646 interrupt-names = "host", "peripheral"; 647 maximum-speed = "high-speed"; 648 dr_mode = "otg"; 649 snps,usb2-gadget-lpm-disable; 650 snps,usb2-lpm-disable; 651 }; 652 }; 653 654 fss: bus@fc00000 { 655 compatible = "simple-bus"; 656 reg = <0x00 0x0fc00000 0x00 0x70000>; 657 #address-cells = <2>; 658 #size-cells = <2>; 659 ranges; 660 status = "disabled"; 661 662 ospi0: spi@fc40000 { 663 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 664 reg = <0x00 0x0fc40000 0x00 0x100>, 665 <0x05 0x00000000 0x01 0x00000000>; 666 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 667 cdns,fifo-depth = <256>; 668 cdns,fifo-width = <4>; 669 cdns,trigger-address = <0x0>; 670 clocks = <&k3_clks 75 7>; 671 assigned-clocks = <&k3_clks 75 7>; 672 assigned-clock-parents = <&k3_clks 75 8>; 673 assigned-clock-rates = <166666666>; 674 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 675 #address-cells = <1>; 676 #size-cells = <0>; 677 }; 678 }; 679 680 cpsw3g: ethernet@8000000 { 681 compatible = "ti,am642-cpsw-nuss"; 682 #address-cells = <2>; 683 #size-cells = <2>; 684 reg = <0x0 0x8000000 0x0 0x200000>; 685 reg-names = "cpsw_nuss"; 686 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>; 687 clocks = <&k3_clks 13 0>; 688 assigned-clocks = <&k3_clks 13 3>; 689 assigned-clock-parents = <&k3_clks 13 11>; 690 clock-names = "fck"; 691 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 692 status = "disabled"; 693 694 dmas = <&main_pktdma 0xc600 15>, 695 <&main_pktdma 0xc601 15>, 696 <&main_pktdma 0xc602 15>, 697 <&main_pktdma 0xc603 15>, 698 <&main_pktdma 0xc604 15>, 699 <&main_pktdma 0xc605 15>, 700 <&main_pktdma 0xc606 15>, 701 <&main_pktdma 0xc607 15>, 702 <&main_pktdma 0x4600 15>; 703 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 704 "tx7", "rx"; 705 706 ethernet-ports { 707 #address-cells = <1>; 708 #size-cells = <0>; 709 710 cpsw_port1: port@1 { 711 reg = <1>; 712 ti,mac-only; 713 label = "port1"; 714 phys = <&phy_gmii_sel 1>; 715 mac-address = [00 00 00 00 00 00]; 716 ti,syscon-efuse = <&wkup_conf 0x200>; 717 }; 718 719 cpsw_port2: port@2 { 720 reg = <2>; 721 ti,mac-only; 722 label = "port2"; 723 phys = <&phy_gmii_sel 2>; 724 mac-address = [00 00 00 00 00 00]; 725 }; 726 }; 727 728 cpsw3g_mdio: mdio@f00 { 729 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 730 reg = <0x0 0xf00 0x0 0x100>; 731 #address-cells = <1>; 732 #size-cells = <0>; 733 clocks = <&k3_clks 13 0>; 734 clock-names = "fck"; 735 bus_freq = <1000000>; 736 }; 737 738 cpts@3d000 { 739 compatible = "ti,j721e-cpts"; 740 reg = <0x0 0x3d000 0x0 0x400>; 741 clocks = <&k3_clks 13 3>; 742 clock-names = "cpts"; 743 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 744 interrupt-names = "cpts"; 745 ti,cpts-ext-ts-inputs = <4>; 746 ti,cpts-periodic-outputs = <2>; 747 }; 748 }; 749 750 hwspinlock: spinlock@2a000000 { 751 compatible = "ti,am64-hwspinlock"; 752 reg = <0x00 0x2a000000 0x00 0x1000>; 753 #hwlock-cells = <1>; 754 }; 755 756 mailbox0_cluster0: mailbox@29000000 { 757 compatible = "ti,am64-mailbox"; 758 reg = <0x00 0x29000000 0x00 0x200>; 759 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 760 #mbox-cells = <1>; 761 ti,mbox-num-users = <4>; 762 ti,mbox-num-fifos = <16>; 763 }; 764 765 mailbox0_cluster1: mailbox@29010000 { 766 compatible = "ti,am64-mailbox"; 767 reg = <0x00 0x29010000 0x00 0x200>; 768 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 769 #mbox-cells = <1>; 770 ti,mbox-num-users = <4>; 771 ti,mbox-num-fifos = <16>; 772 }; 773 774 mailbox0_cluster2: mailbox@29020000 { 775 compatible = "ti,am64-mailbox"; 776 reg = <0x00 0x29020000 0x00 0x200>; 777 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 778 #mbox-cells = <1>; 779 ti,mbox-num-users = <4>; 780 ti,mbox-num-fifos = <16>; 781 }; 782 783 mailbox0_cluster3: mailbox@29030000 { 784 compatible = "ti,am64-mailbox"; 785 reg = <0x00 0x29030000 0x00 0x200>; 786 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 787 #mbox-cells = <1>; 788 ti,mbox-num-users = <4>; 789 ti,mbox-num-fifos = <16>; 790 }; 791 792 main_mcan0: can@20701000 { 793 compatible = "bosch,m_can"; 794 reg = <0x00 0x20701000 0x00 0x200>, 795 <0x00 0x20708000 0x00 0x8000>; 796 reg-names = "m_can", "message_ram"; 797 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 798 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; 799 clock-names = "hclk", "cclk"; 800 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 801 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 802 interrupt-names = "int0", "int1"; 803 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 804 status = "disabled"; 805 }; 806 807 main_rti0: watchdog@e000000 { 808 compatible = "ti,j7-rti-wdt"; 809 reg = <0x00 0x0e000000 0x00 0x100>; 810 clocks = <&k3_clks 125 0>; 811 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 812 assigned-clocks = <&k3_clks 125 0>; 813 assigned-clock-parents = <&k3_clks 125 2>; 814 }; 815 816 main_rti1: watchdog@e010000 { 817 compatible = "ti,j7-rti-wdt"; 818 reg = <0x00 0x0e010000 0x00 0x100>; 819 clocks = <&k3_clks 126 0>; 820 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; 821 assigned-clocks = <&k3_clks 126 0>; 822 assigned-clock-parents = <&k3_clks 126 2>; 823 }; 824 825 main_rti2: watchdog@e020000 { 826 compatible = "ti,j7-rti-wdt"; 827 reg = <0x00 0x0e020000 0x00 0x100>; 828 clocks = <&k3_clks 127 0>; 829 power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; 830 assigned-clocks = <&k3_clks 127 0>; 831 assigned-clock-parents = <&k3_clks 127 2>; 832 }; 833 834 main_rti3: watchdog@e030000 { 835 compatible = "ti,j7-rti-wdt"; 836 reg = <0x00 0x0e030000 0x00 0x100>; 837 clocks = <&k3_clks 128 0>; 838 power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; 839 assigned-clocks = <&k3_clks 128 0>; 840 assigned-clock-parents = <&k3_clks 128 2>; 841 }; 842 843 main_rti4: watchdog@e040000 { 844 compatible = "ti,j7-rti-wdt"; 845 reg = <0x00 0x0e040000 0x00 0x100>; 846 clocks = <&k3_clks 205 0>; 847 power-domains = <&k3_pds 205 TI_SCI_PD_EXCLUSIVE>; 848 assigned-clocks = <&k3_clks 205 0>; 849 assigned-clock-parents = <&k3_clks 205 2>; 850 }; 851 852 epwm0: pwm@23000000 { 853 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 854 #pwm-cells = <3>; 855 reg = <0x00 0x23000000 0x00 0x100>; 856 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 857 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 858 clock-names = "tbclk", "fck"; 859 status = "disabled"; 860 }; 861 862 epwm1: pwm@23010000 { 863 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 864 #pwm-cells = <3>; 865 reg = <0x00 0x23010000 0x00 0x100>; 866 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 867 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 868 clock-names = "tbclk", "fck"; 869 status = "disabled"; 870 }; 871 872 epwm2: pwm@23020000 { 873 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 874 #pwm-cells = <3>; 875 reg = <0x00 0x23020000 0x00 0x100>; 876 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 877 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 878 clock-names = "tbclk", "fck"; 879 status = "disabled"; 880 }; 881 882 ecap0: pwm@23100000 { 883 compatible = "ti,am3352-ecap"; 884 #pwm-cells = <3>; 885 reg = <0x00 0x23100000 0x00 0x100>; 886 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 887 clocks = <&k3_clks 51 0>; 888 clock-names = "fck"; 889 status = "disabled"; 890 }; 891 892 ecap1: pwm@23110000 { 893 compatible = "ti,am3352-ecap"; 894 #pwm-cells = <3>; 895 reg = <0x00 0x23110000 0x00 0x100>; 896 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 897 clocks = <&k3_clks 52 0>; 898 clock-names = "fck"; 899 status = "disabled"; 900 }; 901 902 ecap2: pwm@23120000 { 903 compatible = "ti,am3352-ecap"; 904 #pwm-cells = <3>; 905 reg = <0x00 0x23120000 0x00 0x100>; 906 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 907 clocks = <&k3_clks 53 0>; 908 clock-names = "fck"; 909 status = "disabled"; 910 }; 911 912 mcasp0: audio-controller@2b00000 { 913 compatible = "ti,am33xx-mcasp-audio"; 914 reg = <0x00 0x02b00000 0x00 0x2000>, 915 <0x00 0x02b08000 0x00 0x400>; 916 reg-names = "mpu", "dat"; 917 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, 918 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 919 interrupt-names = "tx", "rx"; 920 921 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; 922 dma-names = "tx", "rx"; 923 924 clocks = <&k3_clks 190 0>; 925 clock-names = "fck"; 926 assigned-clocks = <&k3_clks 190 0>; 927 assigned-clock-parents = <&k3_clks 190 2>; 928 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 929 status = "disabled"; 930 }; 931 932 mcasp1: audio-controller@2b10000 { 933 compatible = "ti,am33xx-mcasp-audio"; 934 reg = <0x00 0x02b10000 0x00 0x2000>, 935 <0x00 0x02b18000 0x00 0x400>; 936 reg-names = "mpu", "dat"; 937 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 939 interrupt-names = "tx", "rx"; 940 941 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; 942 dma-names = "tx", "rx"; 943 944 clocks = <&k3_clks 191 0>; 945 clock-names = "fck"; 946 assigned-clocks = <&k3_clks 191 0>; 947 assigned-clock-parents = <&k3_clks 191 2>; 948 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 949 status = "disabled"; 950 }; 951 952 mcasp2: audio-controller@2b20000 { 953 compatible = "ti,am33xx-mcasp-audio"; 954 reg = <0x00 0x02b20000 0x00 0x2000>, 955 <0x00 0x02b28000 0x00 0x400>; 956 reg-names = "mpu", "dat"; 957 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 959 interrupt-names = "tx", "rx"; 960 961 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; 962 dma-names = "tx", "rx"; 963 964 clocks = <&k3_clks 192 0>; 965 clock-names = "fck"; 966 assigned-clocks = <&k3_clks 192 0>; 967 assigned-clock-parents = <&k3_clks 192 2>; 968 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 969 status = "disabled"; 970 }; 971 972 ti_csi2rx0: ticsi2rx@30102000 { 973 compatible = "ti,j721e-csi2rx-shim"; 974 dmas = <&main_bcdma_csi 0 0x5000 0>; 975 dma-names = "rx0"; 976 reg = <0x00 0x30102000 0x00 0x1000>; 977 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 978 #address-cells = <2>; 979 #size-cells = <2>; 980 ranges; 981 status = "disabled"; 982 983 cdns_csi2rx0: csi-bridge@30101000 { 984 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 985 reg = <0x00 0x30101000 0x00 0x1000>; 986 clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, 987 <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; 988 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 989 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 990 phys = <&dphy0>; 991 phy-names = "dphy"; 992 993 ports { 994 #address-cells = <1>; 995 #size-cells = <0>; 996 997 csi0_port0: port@0 { 998 reg = <0>; 999 status = "disabled"; 1000 }; 1001 1002 csi0_port1: port@1 { 1003 reg = <1>; 1004 status = "disabled"; 1005 }; 1006 1007 csi0_port2: port@2 { 1008 reg = <2>; 1009 status = "disabled"; 1010 }; 1011 1012 csi0_port3: port@3 { 1013 reg = <3>; 1014 status = "disabled"; 1015 }; 1016 1017 csi0_port4: port@4 { 1018 reg = <4>; 1019 status = "disabled"; 1020 }; 1021 }; 1022 }; 1023 }; 1024 1025 dphy0: phy@30110000 { 1026 compatible = "cdns,dphy-rx"; 1027 reg = <0x00 0x30110000 0x00 0x1100>; 1028 #phy-cells = <0>; 1029 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1030 status = "disabled"; 1031 }; 1032 1033 dss: dss@30200000 { 1034 compatible = "ti,am62a7-dss"; 1035 reg = <0x00 0x30200000 0x00 0x1000>, /* common */ 1036 <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ 1037 <0x00 0x30206000 0x00 0x1000>, /* vid */ 1038 <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ 1039 <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ 1040 <0x00 0x3020a000 0x00 0x1000>, /* vp1: Tied OFF in the SoC */ 1041 <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ 1042 <0x00 0x30201000 0x00 0x1000>; /* common1 */ 1043 reg-names = "common", "vidl1", "vid", 1044 "ovr1", "ovr2", "vp1", "vp2", "common1"; 1045 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; 1046 clocks = <&k3_clks 186 6>, 1047 <&k3_clks 186 0>, 1048 <&k3_clks 186 2>; 1049 clock-names = "fck", "vp1", "vp2"; 1050 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1051 status = "disabled"; 1052 1053 dss_ports: ports { 1054 #address-cells = <1>; 1055 #size-cells = <0>; 1056 }; 1057 }; 1058 1059 vpu: video-codec@30210000 { 1060 compatible = "ti,j721s2-wave521c", "cnm,wave521c"; 1061 reg = <0x00 0x30210000 0x00 0x10000>; 1062 clocks = <&k3_clks 204 2>; 1063 power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; 1064 }; 1065}; 1066