1*1d616161SBeleswar Padhi// SPDX-License-Identifier: GPL-2.0-only OR MIT 2*1d616161SBeleswar Padhi/** 3*1d616161SBeleswar Padhi * Device Tree Source for enabling IPC using TI SDK firmware on AM62 SoCs 4*1d616161SBeleswar Padhi * 5*1d616161SBeleswar Padhi * Copyright (C) 2021-2025 Texas Instruments Incorporated - https://www.ti.com/ 6*1d616161SBeleswar Padhi */ 7*1d616161SBeleswar Padhi 8*1d616161SBeleswar Padhi&reserved_memory { 9*1d616161SBeleswar Padhi mcu_m4fss_dma_memory_region: memory@9cb00000 { 10*1d616161SBeleswar Padhi compatible = "shared-dma-pool"; 11*1d616161SBeleswar Padhi reg = <0x00 0x9cb00000 0x00 0x100000>; 12*1d616161SBeleswar Padhi no-map; 13*1d616161SBeleswar Padhi }; 14*1d616161SBeleswar Padhi 15*1d616161SBeleswar Padhi mcu_m4fss_memory_region: memory@9cc00000 { 16*1d616161SBeleswar Padhi compatible = "shared-dma-pool"; 17*1d616161SBeleswar Padhi reg = <0x00 0x9cc00000 0x00 0xe00000>; 18*1d616161SBeleswar Padhi no-map; 19*1d616161SBeleswar Padhi }; 20*1d616161SBeleswar Padhi}; 21*1d616161SBeleswar Padhi 22*1d616161SBeleswar Padhi&mailbox0_cluster0 { 23*1d616161SBeleswar Padhi status = "okay"; 24*1d616161SBeleswar Padhi 25*1d616161SBeleswar Padhi mbox_m4_0: mbox-m4-0 { 26*1d616161SBeleswar Padhi ti,mbox-rx = <0 0 0>; 27*1d616161SBeleswar Padhi ti,mbox-tx = <1 0 0>; 28*1d616161SBeleswar Padhi }; 29*1d616161SBeleswar Padhi 30*1d616161SBeleswar Padhi mbox_r5_0: mbox-r5-0 { 31*1d616161SBeleswar Padhi ti,mbox-rx = <2 0 0>; 32*1d616161SBeleswar Padhi ti,mbox-tx = <3 0 0>; 33*1d616161SBeleswar Padhi }; 34*1d616161SBeleswar Padhi}; 35*1d616161SBeleswar Padhi 36*1d616161SBeleswar Padhi&mcu_m4fss { 37*1d616161SBeleswar Padhi mboxes = <&mailbox0_cluster0 &mbox_m4_0>; 38*1d616161SBeleswar Padhi memory-region = <&mcu_m4fss_dma_memory_region>, 39*1d616161SBeleswar Padhi <&mcu_m4fss_memory_region>; 40*1d616161SBeleswar Padhi status = "okay"; 41*1d616161SBeleswar Padhi}; 42*1d616161SBeleswar Padhi 43*1d616161SBeleswar Padhi&wkup_r5fss0 { 44*1d616161SBeleswar Padhi status = "okay"; 45*1d616161SBeleswar Padhi}; 46*1d616161SBeleswar Padhi 47*1d616161SBeleswar Padhi&wkup_r5fss0_core0 { 48*1d616161SBeleswar Padhi mboxes = <&mailbox0_cluster0 &mbox_r5_0>; 49*1d616161SBeleswar Padhi memory-region = <&wkup_r5fss0_core0_dma_memory_region>, 50*1d616161SBeleswar Padhi <&wkup_r5fss0_core0_memory_region>; 51*1d616161SBeleswar Padhi status = "okay"; 52*1d616161SBeleswar Padhi}; 53