1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for AM625 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 oc_sram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x00 0x70000000 0x00 0x10000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x0 0x00 0x70000000 0x10000>; 15 }; 16 17 gic500: interrupt-controller@1800000 { 18 compatible = "arm,gic-v3"; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 ranges; 22 #interrupt-cells = <3>; 23 interrupt-controller; 24 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 25 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 26 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 27 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 28 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 29 /* 30 * vcpumntirq: 31 * virtual CPU interface maintenance interrupt 32 */ 33 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 34 35 gic_its: msi-controller@1820000 { 36 compatible = "arm,gic-v3-its"; 37 reg = <0x00 0x01820000 0x00 0x10000>; 38 socionext,synquacer-pre-its = <0x1000000 0x400000>; 39 msi-controller; 40 #msi-cells = <1>; 41 }; 42 }; 43 44 main_conf: bus@100000 { 45 compatible = "simple-bus"; 46 #address-cells = <1>; 47 #size-cells = <1>; 48 ranges = <0x0 0x00 0x00100000 0x20000>; 49 50 phy_gmii_sel: phy@4044 { 51 compatible = "ti,am654-phy-gmii-sel"; 52 reg = <0x4044 0x8>; 53 #phy-cells = <1>; 54 }; 55 56 epwm_tbclk: clock-controller@4130 { 57 compatible = "ti,am62-epwm-tbclk"; 58 reg = <0x4130 0x4>; 59 #clock-cells = <1>; 60 }; 61 62 audio_refclk0: clock-controller@82e0 { 63 compatible = "ti,am62-audio-refclk"; 64 reg = <0x82e0 0x4>; 65 clocks = <&k3_clks 157 0>; 66 assigned-clocks = <&k3_clks 157 0>; 67 assigned-clock-parents = <&k3_clks 157 8>; 68 #clock-cells = <0>; 69 }; 70 71 audio_refclk1: clock-controller@82e4 { 72 compatible = "ti,am62-audio-refclk"; 73 reg = <0x82e4 0x4>; 74 clocks = <&k3_clks 157 10>; 75 assigned-clocks = <&k3_clks 157 10>; 76 assigned-clock-parents = <&k3_clks 157 18>; 77 #clock-cells = <0>; 78 }; 79 }; 80 81 dmss: bus@48000000 { 82 bootph-all; 83 compatible = "simple-bus"; 84 #address-cells = <2>; 85 #size-cells = <2>; 86 dma-ranges; 87 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; 88 89 ti,sci-dev-id = <25>; 90 91 secure_proxy_main: mailbox@4d000000 { 92 bootph-all; 93 compatible = "ti,am654-secure-proxy"; 94 #mbox-cells = <1>; 95 reg-names = "target_data", "rt", "scfg"; 96 reg = <0x00 0x4d000000 0x00 0x80000>, 97 <0x00 0x4a600000 0x00 0x80000>, 98 <0x00 0x4a400000 0x00 0x80000>; 99 interrupt-names = "rx_012"; 100 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 101 }; 102 103 inta_main_dmss: interrupt-controller@48000000 { 104 compatible = "ti,sci-inta"; 105 reg = <0x00 0x48000000 0x00 0x100000>; 106 #interrupt-cells = <0>; 107 interrupt-controller; 108 interrupt-parent = <&gic500>; 109 msi-controller; 110 ti,sci = <&dmsc>; 111 ti,sci-dev-id = <28>; 112 ti,interrupt-ranges = <4 68 36>; 113 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 114 }; 115 116 main_bcdma: dma-controller@485c0100 { 117 compatible = "ti,am64-dmss-bcdma"; 118 reg = <0x00 0x485c0100 0x00 0x100>, 119 <0x00 0x4c000000 0x00 0x20000>, 120 <0x00 0x4a820000 0x00 0x20000>, 121 <0x00 0x4aa40000 0x00 0x20000>, 122 <0x00 0x4bc00000 0x00 0x100000>, 123 <0x00 0x48600000 0x00 0x8000>, 124 <0x00 0x484a4000 0x00 0x2000>, 125 <0x00 0x484c2000 0x00 0x2000>, 126 <0x00 0x48420000 0x00 0x2000>; 127 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt", 128 "ring", "tchan", "rchan", "bchan"; 129 msi-parent = <&inta_main_dmss>; 130 #dma-cells = <3>; 131 132 ti,sci = <&dmsc>; 133 ti,sci-dev-id = <26>; 134 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 135 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 136 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 137 }; 138 139 main_pktdma: dma-controller@485c0000 { 140 compatible = "ti,am64-dmss-pktdma"; 141 reg = <0x00 0x485c0000 0x00 0x100>, 142 <0x00 0x4a800000 0x00 0x20000>, 143 <0x00 0x4aa00000 0x00 0x20000>, 144 <0x00 0x4b800000 0x00 0x200000>, 145 <0x00 0x485e0000 0x00 0x10000>, 146 <0x00 0x484a0000 0x00 0x2000>, 147 <0x00 0x484c0000 0x00 0x2000>, 148 <0x00 0x48430000 0x00 0x1000>; 149 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", 150 "ring", "tchan", "rchan", "rflow"; 151 msi-parent = <&inta_main_dmss>; 152 #dma-cells = <2>; 153 154 ti,sci = <&dmsc>; 155 ti,sci-dev-id = <30>; 156 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 157 <0x24>, /* CPSW_TX_CHAN */ 158 <0x25>, /* SAUL_TX_0_CHAN */ 159 <0x26>; /* SAUL_TX_1_CHAN */ 160 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 161 <0x11>, /* RING_CPSW_TX_CHAN */ 162 <0x12>, /* RING_SAUL_TX_0_CHAN */ 163 <0x13>; /* RING_SAUL_TX_1_CHAN */ 164 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 165 <0x2b>, /* CPSW_RX_CHAN */ 166 <0x2d>, /* SAUL_RX_0_CHAN */ 167 <0x2f>, /* SAUL_RX_1_CHAN */ 168 <0x31>, /* SAUL_RX_2_CHAN */ 169 <0x33>; /* SAUL_RX_3_CHAN */ 170 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 171 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 172 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 173 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ 174 }; 175 }; 176 177 dmsc: system-controller@44043000 { 178 bootph-all; 179 compatible = "ti,k2g-sci"; 180 ti,host-id = <12>; 181 mbox-names = "rx", "tx"; 182 mboxes = <&secure_proxy_main 12>, 183 <&secure_proxy_main 13>; 184 reg-names = "debug_messages"; 185 reg = <0x00 0x44043000 0x00 0xfe0>; 186 187 k3_pds: power-controller { 188 bootph-all; 189 compatible = "ti,sci-pm-domain"; 190 #power-domain-cells = <2>; 191 }; 192 193 k3_clks: clock-controller { 194 bootph-all; 195 compatible = "ti,k2g-sci-clk"; 196 #clock-cells = <2>; 197 }; 198 199 k3_reset: reset-controller { 200 bootph-all; 201 compatible = "ti,sci-reset"; 202 #reset-cells = <2>; 203 }; 204 }; 205 206 crypto: crypto@40900000 { 207 compatible = "ti,am62-sa3ul"; 208 reg = <0x00 0x40900000 0x00 0x1200>; 209 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, 210 <&main_pktdma 0x7507 0>; 211 dma-names = "tx", "rx1", "rx2"; 212 }; 213 214 secure_proxy_sa3: mailbox@43600000 { 215 bootph-pre-ram; 216 compatible = "ti,am654-secure-proxy"; 217 #mbox-cells = <1>; 218 reg-names = "target_data", "rt", "scfg"; 219 reg = <0x00 0x43600000 0x00 0x10000>, 220 <0x00 0x44880000 0x00 0x20000>, 221 <0x00 0x44860000 0x00 0x20000>; 222 /* 223 * Marked Disabled: 224 * Node is incomplete as it is meant for bootloaders and 225 * firmware on non-MPU processors 226 */ 227 status = "disabled"; 228 }; 229 230 main_pmx0: pinctrl@f4000 { 231 bootph-all; 232 compatible = "pinctrl-single"; 233 reg = <0x00 0xf4000 0x00 0x2ac>; 234 #pinctrl-cells = <1>; 235 pinctrl-single,register-width = <32>; 236 pinctrl-single,function-mask = <0xffffffff>; 237 }; 238 239 main_esm: esm@420000 { 240 bootph-pre-ram; 241 compatible = "ti,j721e-esm"; 242 reg = <0x00 0x420000 0x00 0x1000>; 243 /* Interrupt sources: rti0, rti1, rti15, wrti0, rti2, rti3 */ 244 ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>; 245 }; 246 247 main_timer0: timer@2400000 { 248 bootph-all; 249 compatible = "ti,am654-timer"; 250 reg = <0x00 0x2400000 0x00 0x400>; 251 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&k3_clks 36 2>; 253 clock-names = "fck"; 254 assigned-clocks = <&k3_clks 36 2>; 255 assigned-clock-parents = <&k3_clks 36 3>; 256 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 257 ti,timer-pwm; 258 }; 259 260 main_timer1: timer@2410000 { 261 compatible = "ti,am654-timer"; 262 reg = <0x00 0x2410000 0x00 0x400>; 263 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 264 clocks = <&k3_clks 37 2>; 265 clock-names = "fck"; 266 assigned-clocks = <&k3_clks 37 2>; 267 assigned-clock-parents = <&k3_clks 37 3>; 268 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 269 ti,timer-pwm; 270 }; 271 272 main_timer2: timer@2420000 { 273 compatible = "ti,am654-timer"; 274 reg = <0x00 0x2420000 0x00 0x400>; 275 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 276 clocks = <&k3_clks 38 2>; 277 clock-names = "fck"; 278 assigned-clocks = <&k3_clks 38 2>; 279 assigned-clock-parents = <&k3_clks 38 3>; 280 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 281 ti,timer-pwm; 282 }; 283 284 main_timer3: timer@2430000 { 285 compatible = "ti,am654-timer"; 286 reg = <0x00 0x2430000 0x00 0x400>; 287 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 288 clocks = <&k3_clks 39 2>; 289 clock-names = "fck"; 290 assigned-clocks = <&k3_clks 39 2>; 291 assigned-clock-parents = <&k3_clks 39 3>; 292 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 293 ti,timer-pwm; 294 }; 295 296 main_timer4: timer@2440000 { 297 compatible = "ti,am654-timer"; 298 reg = <0x00 0x2440000 0x00 0x400>; 299 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 300 clocks = <&k3_clks 40 2>; 301 clock-names = "fck"; 302 assigned-clocks = <&k3_clks 40 2>; 303 assigned-clock-parents = <&k3_clks 40 3>; 304 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 305 ti,timer-pwm; 306 }; 307 308 main_timer5: timer@2450000 { 309 compatible = "ti,am654-timer"; 310 reg = <0x00 0x2450000 0x00 0x400>; 311 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&k3_clks 41 2>; 313 clock-names = "fck"; 314 assigned-clocks = <&k3_clks 41 2>; 315 assigned-clock-parents = <&k3_clks 41 3>; 316 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 317 ti,timer-pwm; 318 }; 319 320 main_timer6: timer@2460000 { 321 compatible = "ti,am654-timer"; 322 reg = <0x00 0x2460000 0x00 0x400>; 323 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&k3_clks 42 2>; 325 clock-names = "fck"; 326 assigned-clocks = <&k3_clks 42 2>; 327 assigned-clock-parents = <&k3_clks 42 3>; 328 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 329 ti,timer-pwm; 330 }; 331 332 main_timer7: timer@2470000 { 333 compatible = "ti,am654-timer"; 334 reg = <0x00 0x2470000 0x00 0x400>; 335 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&k3_clks 43 2>; 337 clock-names = "fck"; 338 assigned-clocks = <&k3_clks 43 2>; 339 assigned-clock-parents = <&k3_clks 43 3>; 340 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 341 ti,timer-pwm; 342 }; 343 344 main_uart0: serial@2800000 { 345 compatible = "ti,am64-uart", "ti,am654-uart"; 346 reg = <0x00 0x02800000 0x00 0x100>; 347 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 348 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 349 clocks = <&k3_clks 146 0>; 350 clock-names = "fclk"; 351 status = "disabled"; 352 }; 353 354 main_uart1: serial@2810000 { 355 compatible = "ti,am64-uart", "ti,am654-uart"; 356 reg = <0x00 0x02810000 0x00 0x100>; 357 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 358 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 359 clocks = <&k3_clks 152 0>; 360 clock-names = "fclk"; 361 status = "disabled"; 362 }; 363 364 main_uart2: serial@2820000 { 365 compatible = "ti,am64-uart", "ti,am654-uart"; 366 reg = <0x00 0x02820000 0x00 0x100>; 367 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 368 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 369 clocks = <&k3_clks 153 0>; 370 clock-names = "fclk"; 371 status = "disabled"; 372 }; 373 374 main_uart3: serial@2830000 { 375 compatible = "ti,am64-uart", "ti,am654-uart"; 376 reg = <0x00 0x02830000 0x00 0x100>; 377 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 378 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 379 clocks = <&k3_clks 154 0>; 380 clock-names = "fclk"; 381 status = "disabled"; 382 }; 383 384 main_uart4: serial@2840000 { 385 compatible = "ti,am64-uart", "ti,am654-uart"; 386 reg = <0x00 0x02840000 0x00 0x100>; 387 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 388 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 389 clocks = <&k3_clks 155 0>; 390 clock-names = "fclk"; 391 status = "disabled"; 392 }; 393 394 main_uart5: serial@2850000 { 395 compatible = "ti,am64-uart", "ti,am654-uart"; 396 reg = <0x00 0x02850000 0x00 0x100>; 397 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 398 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 399 clocks = <&k3_clks 156 0>; 400 clock-names = "fclk"; 401 status = "disabled"; 402 }; 403 404 main_uart6: serial@2860000 { 405 compatible = "ti,am64-uart", "ti,am654-uart"; 406 reg = <0x00 0x02860000 0x00 0x100>; 407 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 408 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 409 clocks = <&k3_clks 158 0>; 410 clock-names = "fclk"; 411 status = "disabled"; 412 }; 413 414 main_i2c0: i2c@20000000 { 415 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 416 reg = <0x00 0x20000000 0x00 0x100>; 417 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 418 #address-cells = <1>; 419 #size-cells = <0>; 420 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 421 clocks = <&k3_clks 102 2>; 422 clock-names = "fck"; 423 status = "disabled"; 424 }; 425 426 main_i2c1: i2c@20010000 { 427 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 428 reg = <0x00 0x20010000 0x00 0x100>; 429 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 430 #address-cells = <1>; 431 #size-cells = <0>; 432 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 433 clocks = <&k3_clks 103 2>; 434 clock-names = "fck"; 435 status = "disabled"; 436 }; 437 438 main_i2c2: i2c@20020000 { 439 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 440 reg = <0x00 0x20020000 0x00 0x100>; 441 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 445 clocks = <&k3_clks 104 2>; 446 clock-names = "fck"; 447 status = "disabled"; 448 }; 449 450 main_i2c3: i2c@20030000 { 451 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 452 reg = <0x00 0x20030000 0x00 0x100>; 453 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 454 #address-cells = <1>; 455 #size-cells = <0>; 456 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 457 clocks = <&k3_clks 105 2>; 458 clock-names = "fck"; 459 status = "disabled"; 460 }; 461 462 main_spi0: spi@20100000 { 463 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 464 reg = <0x00 0x20100000 0x00 0x400>; 465 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 469 clocks = <&k3_clks 141 0>; 470 status = "disabled"; 471 }; 472 473 main_spi1: spi@20110000 { 474 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 475 reg = <0x00 0x20110000 0x00 0x400>; 476 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 480 clocks = <&k3_clks 142 0>; 481 status = "disabled"; 482 }; 483 484 main_spi2: spi@20120000 { 485 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 486 reg = <0x00 0x20120000 0x00 0x400>; 487 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 488 #address-cells = <1>; 489 #size-cells = <0>; 490 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 491 clocks = <&k3_clks 143 0>; 492 status = "disabled"; 493 }; 494 495 main_gpio_intr: interrupt-controller@a00000 { 496 compatible = "ti,sci-intr"; 497 reg = <0x00 0x00a00000 0x00 0x800>; 498 ti,intr-trigger-type = <1>; 499 interrupt-controller; 500 interrupt-parent = <&gic500>; 501 #interrupt-cells = <1>; 502 ti,sci = <&dmsc>; 503 ti,sci-dev-id = <3>; 504 ti,interrupt-ranges = <0 32 16>; 505 }; 506 507 main_gpio0: gpio@600000 { 508 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 509 reg = <0x0 0x00600000 0x0 0x100>; 510 gpio-ranges = <&main_pmx0 0 0 32>, 511 <&main_pmx0 32 33 38>, 512 <&main_pmx0 70 72 22>; 513 gpio-controller; 514 #gpio-cells = <2>; 515 interrupt-parent = <&main_gpio_intr>; 516 interrupts = <190>, <191>, <192>, 517 <193>, <194>, <195>; 518 interrupt-controller; 519 #interrupt-cells = <2>; 520 ti,ngpio = <92>; 521 ti,davinci-gpio-unbanked = <0>; 522 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 523 clocks = <&k3_clks 77 0>; 524 clock-names = "gpio"; 525 }; 526 527 main_gpio1: gpio@601000 { 528 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 529 reg = <0x0 0x00601000 0x0 0x100>; 530 gpio-controller; 531 gpio-ranges = <&main_pmx0 0 94 41>, 532 <&main_pmx0 41 136 6>, 533 <&main_pmx0 47 143 3>, 534 <&main_pmx0 50 149 2>; 535 #gpio-cells = <2>; 536 interrupt-parent = <&main_gpio_intr>; 537 interrupts = <180>, <181>, <182>, 538 <183>, <184>, <185>; 539 interrupt-controller; 540 #interrupt-cells = <2>; 541 ti,ngpio = <52>; 542 ti,davinci-gpio-unbanked = <0>; 543 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 544 clocks = <&k3_clks 78 0>; 545 clock-names = "gpio"; 546 }; 547 548 sdhci0: mmc@fa10000 { 549 compatible = "ti,am62-sdhci"; 550 reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>; 551 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 552 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 553 clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; 554 clock-names = "clk_ahb", "clk_xin"; 555 bus-width = <8>; 556 mmc-hs200-1_8v; 557 ti,clkbuf-sel = <0x7>; 558 ti,otap-del-sel-legacy = <0x0>; 559 ti,otap-del-sel-mmc-hs = <0x0>; 560 ti,otap-del-sel-hs200 = <0x6>; 561 ti,itap-del-sel-legacy = <0x0>; 562 ti,itap-del-sel-mmc-hs = <0x0>; 563 status = "disabled"; 564 }; 565 566 sdhci1: mmc@fa00000 { 567 compatible = "ti,am62-sdhci"; 568 reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>; 569 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 570 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 571 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; 572 clock-names = "clk_ahb", "clk_xin"; 573 bus-width = <4>; 574 ti,clkbuf-sel = <0x7>; 575 ti,otap-del-sel-legacy = <0x0>; 576 ti,otap-del-sel-sd-hs = <0x0>; 577 ti,otap-del-sel-sdr12 = <0xf>; 578 ti,otap-del-sel-sdr25 = <0xf>; 579 ti,otap-del-sel-sdr50 = <0xc>; 580 ti,otap-del-sel-sdr104 = <0x6>; 581 ti,otap-del-sel-ddr50 = <0x9>; 582 ti,itap-del-sel-legacy = <0x0>; 583 ti,itap-del-sel-sd-hs = <0x0>; 584 ti,itap-del-sel-sdr12 = <0x0>; 585 ti,itap-del-sel-sdr25 = <0x0>; 586 status = "disabled"; 587 }; 588 589 sdhci2: mmc@fa20000 { 590 compatible = "ti,am62-sdhci"; 591 reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>; 592 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 593 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 594 clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; 595 clock-names = "clk_ahb", "clk_xin"; 596 bus-width = <4>; 597 ti,clkbuf-sel = <0x7>; 598 ti,otap-del-sel-legacy = <0x0>; 599 ti,otap-del-sel-sd-hs = <0x0>; 600 ti,otap-del-sel-sdr12 = <0xf>; 601 ti,otap-del-sel-sdr25 = <0xf>; 602 ti,otap-del-sel-sdr50 = <0xc>; 603 ti,otap-del-sel-sdr104 = <0x6>; 604 ti,otap-del-sel-ddr50 = <0x9>; 605 ti,itap-del-sel-legacy = <0x0>; 606 ti,itap-del-sel-sd-hs = <0x0>; 607 ti,itap-del-sel-sdr12 = <0x0>; 608 ti,itap-del-sel-sdr25 = <0x0>; 609 status = "disabled"; 610 }; 611 612 usbss0: dwc3-usb@f900000 { 613 compatible = "ti,am62-usb"; 614 reg = <0x00 0x0f900000 0x00 0x800>, 615 <0x00 0x0f908000 0x00 0x400>; 616 clocks = <&k3_clks 161 3>; 617 clock-names = "ref"; 618 ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>; 619 #address-cells = <2>; 620 #size-cells = <2>; 621 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 622 ranges; 623 status = "disabled"; 624 625 usb0: usb@31000000 { 626 compatible = "snps,dwc3"; 627 reg = <0x00 0x31000000 0x00 0x50000>; 628 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 629 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 630 interrupt-names = "host", "peripheral"; 631 maximum-speed = "high-speed"; 632 dr_mode = "otg"; 633 snps,usb2-gadget-lpm-disable; 634 snps,usb2-lpm-disable; 635 }; 636 }; 637 638 usbss1: dwc3-usb@f910000 { 639 compatible = "ti,am62-usb"; 640 reg = <0x00 0x0f910000 0x00 0x800>, 641 <0x00 0x0f918000 0x00 0x400>; 642 clocks = <&k3_clks 162 3>; 643 clock-names = "ref"; 644 ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>; 645 #address-cells = <2>; 646 #size-cells = <2>; 647 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 648 ranges; 649 status = "disabled"; 650 651 usb1: usb@31100000 { 652 compatible = "snps,dwc3"; 653 reg = <0x00 0x31100000 0x00 0x50000>; 654 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 655 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 656 interrupt-names = "host", "peripheral"; 657 maximum-speed = "high-speed"; 658 dr_mode = "otg"; 659 snps,usb2-gadget-lpm-disable; 660 snps,usb2-lpm-disable; 661 }; 662 }; 663 664 fss: bus@fc00000 { 665 compatible = "simple-bus"; 666 reg = <0x00 0x0fc00000 0x00 0x70000>; 667 #address-cells = <2>; 668 #size-cells = <2>; 669 ranges; 670 671 ospi0: spi@fc40000 { 672 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 673 reg = <0x00 0x0fc40000 0x00 0x100>, 674 <0x05 0x00000000 0x01 0x00000000>; 675 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 676 cdns,fifo-depth = <256>; 677 cdns,fifo-width = <4>; 678 cdns,trigger-address = <0x0>; 679 clocks = <&k3_clks 75 7>; 680 assigned-clocks = <&k3_clks 75 7>; 681 assigned-clock-parents = <&k3_clks 75 8>; 682 assigned-clock-rates = <166666666>; 683 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 684 #address-cells = <1>; 685 #size-cells = <0>; 686 status = "disabled"; 687 }; 688 }; 689 690 gpu: gpu@fd00000 { 691 compatible = "ti,am62-gpu", "img,img-axe-1-16m", "img,img-axe", 692 "img,img-rogue"; 693 reg = <0x00 0x0fd00000 0x00 0x20000>; 694 clocks = <&k3_clks 187 0>; 695 clock-names = "core"; 696 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 697 power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; 698 power-domain-names = "a"; 699 }; 700 701 cpsw3g: ethernet@8000000 { 702 compatible = "ti,am642-cpsw-nuss"; 703 #address-cells = <2>; 704 #size-cells = <2>; 705 reg = <0x00 0x08000000 0x00 0x200000>; 706 reg-names = "cpsw_nuss"; 707 ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>; 708 clocks = <&k3_clks 13 0>; 709 assigned-clocks = <&k3_clks 13 3>; 710 assigned-clock-parents = <&k3_clks 13 11>; 711 clock-names = "fck"; 712 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 713 714 dmas = <&main_pktdma 0xc600 15>, 715 <&main_pktdma 0xc601 15>, 716 <&main_pktdma 0xc602 15>, 717 <&main_pktdma 0xc603 15>, 718 <&main_pktdma 0xc604 15>, 719 <&main_pktdma 0xc605 15>, 720 <&main_pktdma 0xc606 15>, 721 <&main_pktdma 0xc607 15>, 722 <&main_pktdma 0x4600 15>; 723 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 724 "tx7", "rx"; 725 726 ethernet-ports { 727 #address-cells = <1>; 728 #size-cells = <0>; 729 730 cpsw_port1: port@1 { 731 reg = <1>; 732 ti,mac-only; 733 label = "port1"; 734 phys = <&phy_gmii_sel 1>; 735 mac-address = [00 00 00 00 00 00]; 736 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; 737 }; 738 739 cpsw_port2: port@2 { 740 reg = <2>; 741 ti,mac-only; 742 label = "port2"; 743 phys = <&phy_gmii_sel 2>; 744 mac-address = [00 00 00 00 00 00]; 745 }; 746 }; 747 748 cpsw3g_mdio: mdio@f00 { 749 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 750 reg = <0x00 0xf00 0x00 0x100>; 751 #address-cells = <1>; 752 #size-cells = <0>; 753 clocks = <&k3_clks 13 0>; 754 clock-names = "fck"; 755 bus_freq = <1000000>; 756 status = "disabled"; 757 }; 758 759 cpts@3d000 { 760 compatible = "ti,j721e-cpts"; 761 reg = <0x00 0x3d000 0x00 0x400>; 762 clocks = <&k3_clks 13 3>; 763 clock-names = "cpts"; 764 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 765 interrupt-names = "cpts"; 766 ti,cpts-ext-ts-inputs = <4>; 767 ti,cpts-periodic-outputs = <2>; 768 }; 769 }; 770 771 dss: dss@30200000 { 772 compatible = "ti,am625-dss"; 773 reg = <0x00 0x30200000 0x00 0x1000>, /* common */ 774 <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ 775 <0x00 0x30206000 0x00 0x1000>, /* vid */ 776 <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ 777 <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ 778 <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ 779 <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ 780 <0x00 0x30201000 0x00 0x1000>; /* common1 */ 781 reg-names = "common", "vidl1", "vid", 782 "ovr1", "ovr2", "vp1", "vp2", "common1"; 783 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; 784 clocks = <&k3_clks 186 6>, 785 <&dss_vp1_clk>, 786 <&k3_clks 186 2>; 787 clock-names = "fck", "vp1", "vp2"; 788 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 789 status = "disabled"; 790 791 dss_ports: ports { 792 #address-cells = <1>; 793 #size-cells = <0>; 794 }; 795 }; 796 797 hwspinlock: spinlock@2a000000 { 798 compatible = "ti,am64-hwspinlock"; 799 reg = <0x00 0x2a000000 0x00 0x1000>; 800 #hwlock-cells = <1>; 801 }; 802 803 mailbox0_cluster0: mailbox@29000000 { 804 compatible = "ti,am64-mailbox"; 805 reg = <0x00 0x29000000 0x00 0x200>; 806 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 808 #mbox-cells = <1>; 809 ti,mbox-num-users = <4>; 810 ti,mbox-num-fifos = <16>; 811 status = "disabled"; 812 }; 813 814 ecap0: pwm@23100000 { 815 compatible = "ti,am3352-ecap"; 816 #pwm-cells = <3>; 817 reg = <0x00 0x23100000 0x00 0x100>; 818 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 819 clocks = <&k3_clks 51 0>; 820 clock-names = "fck"; 821 status = "disabled"; 822 }; 823 824 ecap1: pwm@23110000 { 825 compatible = "ti,am3352-ecap"; 826 #pwm-cells = <3>; 827 reg = <0x00 0x23110000 0x00 0x100>; 828 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 829 clocks = <&k3_clks 52 0>; 830 clock-names = "fck"; 831 status = "disabled"; 832 }; 833 834 ecap2: pwm@23120000 { 835 compatible = "ti,am3352-ecap"; 836 #pwm-cells = <3>; 837 reg = <0x00 0x23120000 0x00 0x100>; 838 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 839 clocks = <&k3_clks 53 0>; 840 clock-names = "fck"; 841 status = "disabled"; 842 }; 843 844 eqep0: counter@23200000 { 845 compatible = "ti,am62-eqep"; 846 reg = <0x00 0x23200000 0x00 0x100>; 847 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; 848 clocks = <&k3_clks 59 0>; 849 interrupts = <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>; 850 status = "disabled"; 851 }; 852 853 eqep1: counter@23210000 { 854 compatible = "ti,am62-eqep"; 855 reg = <0x00 0x23210000 0x00 0x100>; 856 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; 857 clocks = <&k3_clks 60 0>; 858 interrupts = <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>; 859 status = "disabled"; 860 }; 861 862 eqep2: counter@23220000 { 863 compatible = "ti,am62-eqep"; 864 reg = <0x00 0x23220000 0x00 0x100>; 865 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 866 clocks = <&k3_clks 62 0>; 867 interrupts = <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>; 868 status = "disabled"; 869 }; 870 871 main_mcan0: can@20701000 { 872 compatible = "bosch,m_can"; 873 reg = <0x00 0x20701000 0x00 0x200>, 874 <0x00 0x20708000 0x00 0x8000>; 875 reg-names = "m_can", "message_ram"; 876 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 877 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; 878 clock-names = "hclk", "cclk"; 879 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 881 interrupt-names = "int0", "int1"; 882 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 883 status = "disabled"; 884 }; 885 886 main_rti0: watchdog@e000000 { 887 compatible = "ti,j7-rti-wdt"; 888 reg = <0x00 0x0e000000 0x00 0x100>; 889 clocks = <&k3_clks 125 0>; 890 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 891 assigned-clocks = <&k3_clks 125 0>; 892 assigned-clock-parents = <&k3_clks 125 2>; 893 }; 894 895 main_rti1: watchdog@e010000 { 896 compatible = "ti,j7-rti-wdt"; 897 reg = <0x00 0x0e010000 0x00 0x100>; 898 clocks = <&k3_clks 126 0>; 899 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; 900 assigned-clocks = <&k3_clks 126 0>; 901 assigned-clock-parents = <&k3_clks 126 2>; 902 }; 903 904 main_rti2: watchdog@e020000 { 905 compatible = "ti,j7-rti-wdt"; 906 reg = <0x00 0x0e020000 0x00 0x100>; 907 clocks = <&k3_clks 127 0>; 908 power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; 909 assigned-clocks = <&k3_clks 127 0>; 910 assigned-clock-parents = <&k3_clks 127 2>; 911 }; 912 913 main_rti3: watchdog@e030000 { 914 compatible = "ti,j7-rti-wdt"; 915 reg = <0x00 0x0e030000 0x00 0x100>; 916 clocks = <&k3_clks 128 0>; 917 power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; 918 assigned-clocks = <&k3_clks 128 0>; 919 assigned-clock-parents = <&k3_clks 128 2>; 920 }; 921 922 main_rti15: watchdog@e0f0000 { 923 compatible = "ti,j7-rti-wdt"; 924 reg = <0x00 0x0e0f0000 0x00 0x100>; 925 clocks = <&k3_clks 130 0>; 926 power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>; 927 assigned-clocks = <&k3_clks 130 0>; 928 assigned-clock-parents = <&k3_clks 130 2>; 929 }; 930 931 epwm0: pwm@23000000 { 932 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 933 #pwm-cells = <3>; 934 reg = <0x00 0x23000000 0x00 0x100>; 935 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 936 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 937 clock-names = "tbclk", "fck"; 938 status = "disabled"; 939 }; 940 941 epwm1: pwm@23010000 { 942 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 943 #pwm-cells = <3>; 944 reg = <0x00 0x23010000 0x00 0x100>; 945 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 946 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 947 clock-names = "tbclk", "fck"; 948 status = "disabled"; 949 }; 950 951 epwm2: pwm@23020000 { 952 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 953 #pwm-cells = <3>; 954 reg = <0x00 0x23020000 0x00 0x100>; 955 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 956 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 957 clock-names = "tbclk", "fck"; 958 status = "disabled"; 959 }; 960 961 mcasp0: audio-controller@2b00000 { 962 compatible = "ti,am33xx-mcasp-audio"; 963 reg = <0x00 0x02b00000 0x00 0x2000>, 964 <0x00 0x02b08000 0x00 0x400>; 965 reg-names = "mpu", "dat"; 966 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 968 interrupt-names = "tx", "rx"; 969 970 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; 971 dma-names = "tx", "rx"; 972 973 clocks = <&k3_clks 190 0>; 974 clock-names = "fck"; 975 assigned-clocks = <&k3_clks 190 0>; 976 assigned-clock-parents = <&k3_clks 190 2>; 977 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 978 status = "disabled"; 979 }; 980 981 mcasp1: audio-controller@2b10000 { 982 compatible = "ti,am33xx-mcasp-audio"; 983 reg = <0x00 0x02b10000 0x00 0x2000>, 984 <0x00 0x02b18000 0x00 0x400>; 985 reg-names = "mpu", "dat"; 986 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 988 interrupt-names = "tx", "rx"; 989 990 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; 991 dma-names = "tx", "rx"; 992 993 clocks = <&k3_clks 191 0>; 994 clock-names = "fck"; 995 assigned-clocks = <&k3_clks 191 0>; 996 assigned-clock-parents = <&k3_clks 191 2>; 997 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 998 status = "disabled"; 999 }; 1000 1001 mcasp2: audio-controller@2b20000 { 1002 compatible = "ti,am33xx-mcasp-audio"; 1003 reg = <0x00 0x02b20000 0x00 0x2000>, 1004 <0x00 0x02b28000 0x00 0x400>; 1005 reg-names = "mpu", "dat"; 1006 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1007 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1008 interrupt-names = "tx", "rx"; 1009 1010 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; 1011 dma-names = "tx", "rx"; 1012 1013 clocks = <&k3_clks 192 0>; 1014 clock-names = "fck"; 1015 assigned-clocks = <&k3_clks 192 0>; 1016 assigned-clock-parents = <&k3_clks 192 2>; 1017 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1018 status = "disabled"; 1019 }; 1020 1021 ti_csi2rx0: ticsi2rx@30102000 { 1022 compatible = "ti,j721e-csi2rx-shim"; 1023 dmas = <&main_bcdma 0 0x4700 0>; 1024 dma-names = "rx0"; 1025 reg = <0x00 0x30102000 0x00 0x1000>; 1026 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1027 #address-cells = <2>; 1028 #size-cells = <2>; 1029 ranges; 1030 status = "disabled"; 1031 1032 cdns_csi2rx0: csi-bridge@30101000 { 1033 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 1034 reg = <0x00 0x30101000 0x00 0x1000>; 1035 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1036 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1037 interrupt-names = "error_irq", "irq"; 1038 clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, 1039 <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; 1040 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 1041 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 1042 phys = <&dphy0>; 1043 phy-names = "dphy"; 1044 1045 ports { 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 1049 csi0_port0: port@0 { 1050 reg = <0>; 1051 status = "disabled"; 1052 }; 1053 1054 csi0_port1: port@1 { 1055 reg = <1>; 1056 status = "disabled"; 1057 }; 1058 1059 csi0_port2: port@2 { 1060 reg = <2>; 1061 status = "disabled"; 1062 }; 1063 1064 csi0_port3: port@3 { 1065 reg = <3>; 1066 status = "disabled"; 1067 }; 1068 1069 csi0_port4: port@4 { 1070 reg = <4>; 1071 status = "disabled"; 1072 }; 1073 }; 1074 }; 1075 }; 1076 1077 dphy0: phy@30110000 { 1078 compatible = "cdns,dphy-rx"; 1079 reg = <0x00 0x30110000 0x00 0x1100>; 1080 #phy-cells = <0>; 1081 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1082 status = "disabled"; 1083 }; 1084 1085 pruss: pruss@30040000 { 1086 compatible = "ti,am625-pruss"; 1087 reg = <0x00 0x30040000 0x00 0x80000>; 1088 power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; 1089 #address-cells = <1>; 1090 #size-cells = <1>; 1091 ranges = <0x0 0x00 0x30040000 0x80000>; 1092 1093 pruss_mem: memories@0 { 1094 reg = <0x0 0x2000>, 1095 <0x2000 0x2000>, 1096 <0x10000 0x10000>; 1097 reg-names = "dram0", "dram1", "shrdram2"; 1098 }; 1099 1100 pruss_cfg: cfg@26000 { 1101 compatible = "ti,pruss-cfg", "syscon"; 1102 reg = <0x26000 0x200>; 1103 #address-cells = <1>; 1104 #size-cells = <1>; 1105 ranges = <0x0 0x26000 0x2000>; 1106 1107 clocks { 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 1111 pruss_coreclk_mux: coreclk-mux@3c { 1112 reg = <0x3c>; 1113 #clock-cells = <0>; 1114 clocks = <&k3_clks 81 0>, /* pruss_core_clk */ 1115 <&k3_clks 81 14>; /* pruss_iclk */ 1116 assigned-clocks = <&pruss_coreclk_mux>; 1117 assigned-clock-parents = <&k3_clks 81 14>; 1118 }; 1119 1120 pruss_iepclk_mux: iepclk-mux@30 { 1121 reg = <0x30>; 1122 #clock-cells = <0>; 1123 clocks = <&k3_clks 81 3>, /* pruss_iep_clk */ 1124 <&pruss_coreclk_mux>; /* pruss_coreclk_mux */ 1125 assigned-clocks = <&pruss_iepclk_mux>; 1126 assigned-clock-parents = <&pruss_coreclk_mux>; 1127 }; 1128 }; 1129 }; 1130 1131 pruss_intc: interrupt-controller@20000 { 1132 compatible = "ti,pruss-intc"; 1133 reg = <0x20000 0x2000>; 1134 interrupt-controller; 1135 #interrupt-cells = <3>; 1136 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1137 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1138 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1139 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1140 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1141 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1143 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1144 interrupt-names = "host_intr0", "host_intr1", 1145 "host_intr2", "host_intr3", 1146 "host_intr4", "host_intr5", 1147 "host_intr6", "host_intr7"; 1148 }; 1149 1150 pru0: pru@34000 { 1151 compatible = "ti,am625-pru"; 1152 reg = <0x34000 0x3000>, 1153 <0x22000 0x100>, 1154 <0x22400 0x100>; 1155 reg-names = "iram", "control", "debug"; 1156 firmware-name = "am62x-pru0-fw"; 1157 interrupt-parent = <&pruss_intc>; 1158 interrupts = <16 2 2>; 1159 interrupt-names = "vring"; 1160 }; 1161 1162 pru1: pru@38000 { 1163 compatible = "ti,am625-pru"; 1164 reg = <0x38000 0x3000>, 1165 <0x24000 0x100>, 1166 <0x24400 0x100>; 1167 reg-names = "iram", "control", "debug"; 1168 firmware-name = "am62x-pru1-fw"; 1169 interrupt-parent = <&pruss_intc>; 1170 interrupts = <18 3 3>; 1171 interrupt-names = "vring"; 1172 }; 1173 }; 1174 1175 gpmc0: memory-controller@3b000000 { 1176 compatible = "ti,am64-gpmc"; 1177 power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; 1178 clocks = <&k3_clks 80 0>; 1179 clock-names = "fck"; 1180 reg = <0x00 0x03b000000 0x00 0x400>, 1181 <0x00 0x050000000 0x00 0x8000000>; 1182 reg-names = "cfg", "data"; 1183 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1184 gpmc,num-cs = <3>; 1185 gpmc,num-waitpins = <2>; 1186 #address-cells = <2>; 1187 #size-cells = <1>; 1188 interrupt-controller; 1189 #interrupt-cells = <2>; 1190 gpio-controller; 1191 #gpio-cells = <2>; 1192 status = "disabled"; 1193 }; 1194 1195 elm0: ecc@25010000 { 1196 compatible = "ti,am64-elm"; 1197 reg = <0x00 0x25010000 0x00 0x2000>; 1198 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 1199 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; 1200 clocks = <&k3_clks 54 0>; 1201 clock-names = "fck"; 1202 status = "disabled"; 1203 }; 1204}; 1205