1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Tesla Full Self-Driving SoC device tree source 4 * 5 * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd. 6 * https://www.samsung.com 7 * Copyright (c) 2017-2022 Tesla, Inc. 8 * https://www.tesla.com 9 */ 10 11#include <dt-bindings/clock/fsd-clk.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13 14/ { 15 compatible = "tesla,fsd"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 i2c0 = &hsi2c_0; 22 i2c1 = &hsi2c_1; 23 i2c2 = &hsi2c_2; 24 i2c3 = &hsi2c_3; 25 i2c4 = &hsi2c_4; 26 i2c5 = &hsi2c_5; 27 i2c6 = &hsi2c_6; 28 i2c7 = &hsi2c_7; 29 pinctrl0 = &pinctrl_fsys0; 30 pinctrl1 = &pinctrl_peric; 31 pinctrl2 = &pinctrl_pmu; 32 spi0 = &spi_0; 33 spi1 = &spi_1; 34 spi2 = &spi_2; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 cpu-map { 42 cluster0 { 43 core0 { 44 cpu = <&cpucl0_0>; 45 }; 46 core1 { 47 cpu = <&cpucl0_1>; 48 }; 49 core2 { 50 cpu = <&cpucl0_2>; 51 }; 52 core3 { 53 cpu = <&cpucl0_3>; 54 }; 55 }; 56 57 cluster1 { 58 core0 { 59 cpu = <&cpucl1_0>; 60 }; 61 core1 { 62 cpu = <&cpucl1_1>; 63 }; 64 core2 { 65 cpu = <&cpucl1_2>; 66 }; 67 core3 { 68 cpu = <&cpucl1_3>; 69 }; 70 }; 71 72 cluster2 { 73 core0 { 74 cpu = <&cpucl2_0>; 75 }; 76 core1 { 77 cpu = <&cpucl2_1>; 78 }; 79 core2 { 80 cpu = <&cpucl2_2>; 81 }; 82 core3 { 83 cpu = <&cpucl2_3>; 84 }; 85 }; 86 }; 87 88 /* Cluster 0 */ 89 cpucl0_0: cpu@0 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a72"; 92 reg = <0x0 0x000>; 93 enable-method = "psci"; 94 clock-frequency = <2400000000>; 95 cpu-idle-states = <&CPU_SLEEP>; 96 i-cache-size = <0xc000>; 97 i-cache-line-size = <64>; 98 i-cache-sets = <256>; 99 d-cache-size = <0x8000>; 100 d-cache-line-size = <64>; 101 d-cache-sets = <256>; 102 next-level-cache = <&cpucl_l2>; 103 }; 104 105 cpucl0_1: cpu@1 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a72"; 108 reg = <0x0 0x001>; 109 enable-method = "psci"; 110 clock-frequency = <2400000000>; 111 cpu-idle-states = <&CPU_SLEEP>; 112 i-cache-size = <0xc000>; 113 i-cache-line-size = <64>; 114 i-cache-sets = <256>; 115 d-cache-size = <0x8000>; 116 d-cache-line-size = <64>; 117 d-cache-sets = <256>; 118 next-level-cache = <&cpucl_l2>; 119 }; 120 121 cpucl0_2: cpu@2 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a72"; 124 reg = <0x0 0x002>; 125 enable-method = "psci"; 126 clock-frequency = <2400000000>; 127 cpu-idle-states = <&CPU_SLEEP>; 128 i-cache-size = <0xc000>; 129 i-cache-line-size = <64>; 130 i-cache-sets = <256>; 131 d-cache-size = <0x8000>; 132 d-cache-line-size = <64>; 133 d-cache-sets = <256>; 134 next-level-cache = <&cpucl_l2>; 135 }; 136 137 cpucl0_3: cpu@3 { 138 device_type = "cpu"; 139 compatible = "arm,cortex-a72"; 140 reg = <0x0 0x003>; 141 enable-method = "psci"; 142 cpu-idle-states = <&CPU_SLEEP>; 143 i-cache-size = <0xc000>; 144 i-cache-line-size = <64>; 145 i-cache-sets = <256>; 146 d-cache-size = <0x8000>; 147 d-cache-line-size = <64>; 148 d-cache-sets = <256>; 149 next-level-cache = <&cpucl_l2>; 150 }; 151 152 /* Cluster 1 */ 153 cpucl1_0: cpu@100 { 154 device_type = "cpu"; 155 compatible = "arm,cortex-a72"; 156 reg = <0x0 0x100>; 157 enable-method = "psci"; 158 clock-frequency = <2400000000>; 159 cpu-idle-states = <&CPU_SLEEP>; 160 i-cache-size = <0xc000>; 161 i-cache-line-size = <64>; 162 i-cache-sets = <256>; 163 d-cache-size = <0x8000>; 164 d-cache-line-size = <64>; 165 d-cache-sets = <256>; 166 next-level-cache = <&cpucl_l2>; 167 }; 168 169 cpucl1_1: cpu@101 { 170 device_type = "cpu"; 171 compatible = "arm,cortex-a72"; 172 reg = <0x0 0x101>; 173 enable-method = "psci"; 174 clock-frequency = <2400000000>; 175 cpu-idle-states = <&CPU_SLEEP>; 176 i-cache-size = <0xc000>; 177 i-cache-line-size = <64>; 178 i-cache-sets = <256>; 179 d-cache-size = <0x8000>; 180 d-cache-line-size = <64>; 181 d-cache-sets = <256>; 182 next-level-cache = <&cpucl_l2>; 183 }; 184 185 cpucl1_2: cpu@102 { 186 device_type = "cpu"; 187 compatible = "arm,cortex-a72"; 188 reg = <0x0 0x102>; 189 enable-method = "psci"; 190 clock-frequency = <2400000000>; 191 cpu-idle-states = <&CPU_SLEEP>; 192 i-cache-size = <0xc000>; 193 i-cache-line-size = <64>; 194 i-cache-sets = <256>; 195 d-cache-size = <0x8000>; 196 d-cache-line-size = <64>; 197 d-cache-sets = <256>; 198 next-level-cache = <&cpucl_l2>; 199 }; 200 201 cpucl1_3: cpu@103 { 202 device_type = "cpu"; 203 compatible = "arm,cortex-a72"; 204 reg = <0x0 0x103>; 205 enable-method = "psci"; 206 clock-frequency = <2400000000>; 207 cpu-idle-states = <&CPU_SLEEP>; 208 i-cache-size = <0xc000>; 209 i-cache-line-size = <64>; 210 i-cache-sets = <256>; 211 d-cache-size = <0x8000>; 212 d-cache-line-size = <64>; 213 d-cache-sets = <256>; 214 next-level-cache = <&cpucl_l2>; 215 }; 216 217 /* Cluster 2 */ 218 cpucl2_0: cpu@200 { 219 device_type = "cpu"; 220 compatible = "arm,cortex-a72"; 221 reg = <0x0 0x200>; 222 enable-method = "psci"; 223 clock-frequency = <2400000000>; 224 cpu-idle-states = <&CPU_SLEEP>; 225 i-cache-size = <0xc000>; 226 i-cache-line-size = <64>; 227 i-cache-sets = <256>; 228 d-cache-size = <0x8000>; 229 d-cache-line-size = <64>; 230 d-cache-sets = <256>; 231 next-level-cache = <&cpucl_l2>; 232 }; 233 234 cpucl2_1: cpu@201 { 235 device_type = "cpu"; 236 compatible = "arm,cortex-a72"; 237 reg = <0x0 0x201>; 238 enable-method = "psci"; 239 clock-frequency = <2400000000>; 240 cpu-idle-states = <&CPU_SLEEP>; 241 i-cache-size = <0xc000>; 242 i-cache-line-size = <64>; 243 i-cache-sets = <256>; 244 d-cache-size = <0x8000>; 245 d-cache-line-size = <64>; 246 d-cache-sets = <256>; 247 next-level-cache = <&cpucl_l2>; 248 }; 249 250 cpucl2_2: cpu@202 { 251 device_type = "cpu"; 252 compatible = "arm,cortex-a72"; 253 reg = <0x0 0x202>; 254 enable-method = "psci"; 255 clock-frequency = <2400000000>; 256 cpu-idle-states = <&CPU_SLEEP>; 257 i-cache-size = <0xc000>; 258 i-cache-line-size = <64>; 259 i-cache-sets = <256>; 260 d-cache-size = <0x8000>; 261 d-cache-line-size = <64>; 262 d-cache-sets = <256>; 263 next-level-cache = <&cpucl_l2>; 264 }; 265 266 cpucl2_3: cpu@203 { 267 device_type = "cpu"; 268 compatible = "arm,cortex-a72"; 269 reg = <0x0 0x203>; 270 enable-method = "psci"; 271 clock-frequency = <2400000000>; 272 cpu-idle-states = <&CPU_SLEEP>; 273 i-cache-size = <0xc000>; 274 i-cache-line-size = <64>; 275 i-cache-sets = <256>; 276 d-cache-size = <0x8000>; 277 d-cache-line-size = <64>; 278 d-cache-sets = <256>; 279 next-level-cache = <&cpucl_l2>; 280 }; 281 282 cpucl_l2: l2-cache0 { 283 compatible = "cache"; 284 cache-level = <2>; 285 cache-unified; 286 cache-size = <0x400000>; 287 cache-line-size = <64>; 288 cache-sets = <4096>; 289 }; 290 291 idle-states { 292 entry-method = "psci"; 293 294 CPU_SLEEP: cpu-sleep { 295 idle-state-name = "c2"; 296 compatible = "arm,idle-state"; 297 local-timer-stop; 298 arm,psci-suspend-param = <0x0010000>; 299 entry-latency-us = <30>; 300 exit-latency-us = <75>; 301 min-residency-us = <300>; 302 }; 303 }; 304 }; 305 306 arm-pmu { 307 compatible = "arm,armv8-pmuv3"; 308 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 314 <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, 315 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, 316 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>; 320 interrupt-affinity = <&cpucl0_0>, <&cpucl0_1>, <&cpucl0_2>, 321 <&cpucl0_3>, <&cpucl1_0>, <&cpucl1_1>, 322 <&cpucl1_2>, <&cpucl1_3>, <&cpucl2_0>, 323 <&cpucl2_1>, <&cpucl2_2>, <&cpucl2_3>; 324 }; 325 326 psci { 327 compatible = "arm,psci-1.0"; 328 method = "smc"; 329 }; 330 331 timer { 332 compatible = "arm,armv8-timer"; 333 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 334 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 335 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 336 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 337 }; 338 339 fin_pll: clock { 340 compatible = "fixed-clock"; 341 clock-output-names = "fin_pll"; 342 #clock-cells = <0>; 343 }; 344 345 reserved-memory { 346 #address-cells = <2>; 347 #size-cells = <2>; 348 ranges; 349 350 mfc_left: region@84000000 { 351 compatible = "shared-dma-pool"; 352 no-map; 353 reg = <0 0x84000000 0 0x8000000>; 354 }; 355 }; 356 357 soc: soc@0 { 358 compatible = "simple-bus"; 359 #address-cells = <2>; 360 #size-cells = <2>; 361 ranges = <0x0 0x0 0x0 0x0 0x0 0x18000000>; 362 dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; 363 364 gic: interrupt-controller@10400000 { 365 compatible = "arm,gic-v3"; 366 #interrupt-cells = <3>; 367 interrupt-controller; 368 reg = <0x0 0x10400000 0x0 0x10000>, /* GICD */ 369 <0x0 0x10600000 0x0 0x200000>; /* GICR_RD+GICR_SGI */ 370 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 371 }; 372 373 smmu_imem: iommu@10200000 { 374 compatible = "arm,mmu-500"; 375 reg = <0x0 0x10200000 0x0 0x10000>; 376 #iommu-cells = <2>; 377 #global-interrupts = <7>; 378 interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */ 379 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */ 380 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */ 381 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */ 382 /* Performance counter interrupts */ 383 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS1_0 */ 384 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS1_1 */ 385 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, /* for IMEM_0 */ 386 /* Per context non-secure context interrupts, 0-3 interrupts */ 387 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */ 388 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_1 */ 389 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_2 */ 390 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_3 */ 391 }; 392 393 smmu_isp: iommu@12100000 { 394 compatible = "arm,mmu-500"; 395 reg = <0x0 0x12100000 0x0 0x10000>; 396 #iommu-cells = <2>; 397 #global-interrupts = <11>; 398 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */ 399 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */ 400 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */ 401 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */ 402 /* Performance counter interrupts */ 403 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_CSI */ 404 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_DP_0 */ 405 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_DP_1 */ 406 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_ISP_0 */ 407 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_ISP_1 */ 408 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_MFC_0 */ 409 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_MFC_1 */ 410 /* Per context non-secure context interrupts, 0-7 interrupts */ 411 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */ 412 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_1 */ 413 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_2 */ 414 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_3 */ 415 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_4 */ 416 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_5 */ 417 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_6 */ 418 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_7 */ 419 }; 420 421 smmu_peric: iommu@14900000 { 422 compatible = "arm,mmu-500"; 423 reg = <0x0 0x14900000 0x0 0x10000>; 424 #iommu-cells = <2>; 425 #global-interrupts = <5>; 426 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */ 427 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */ 428 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */ 429 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */ 430 /* Performance counter interrupts */ 431 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, /* for PERIC */ 432 /* Per context non-secure context interrupts, 0-1 interrupts */ 433 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */ 434 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_1 */ 435 }; 436 437 smmu_fsys0: iommu@15450000 { 438 compatible = "arm,mmu-500"; 439 reg = <0x0 0x15450000 0x0 0x10000>; 440 #iommu-cells = <2>; 441 #global-interrupts = <5>; 442 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */ 443 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */ 444 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */ 445 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */ 446 /* Performance counter interrupts */ 447 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS0 */ 448 /* Per context non-secure context interrupts, 0-1 interrupts */ 449 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */ 450 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_1 */ 451 }; 452 453 clock_imem: clock-controller@10010000 { 454 compatible = "tesla,fsd-clock-imem"; 455 reg = <0x0 0x10010000 0x0 0x3000>; 456 #clock-cells = <1>; 457 clocks = <&fin_pll>, 458 <&clock_cmu DOUT_CMU_IMEM_TCUCLK>, 459 <&clock_cmu DOUT_CMU_IMEM_ACLK>, 460 <&clock_cmu DOUT_CMU_IMEM_DMACLK>; 461 clock-names = "fin_pll", 462 "dout_cmu_imem_tcuclk", 463 "dout_cmu_imem_aclk", 464 "dout_cmu_imem_dmaclk"; 465 }; 466 467 clock_cmu: clock-controller@11c10000 { 468 compatible = "tesla,fsd-clock-cmu"; 469 reg = <0x0 0x11c10000 0x0 0x3000>; 470 #clock-cells = <1>; 471 clocks = <&fin_pll>; 472 clock-names = "fin_pll"; 473 }; 474 475 clock_csi: clock-controller@12610000 { 476 compatible = "tesla,fsd-clock-cam_csi"; 477 reg = <0x0 0x12610000 0x0 0x3000>; 478 #clock-cells = <1>; 479 clocks = <&fin_pll>; 480 clock-names = "fin_pll"; 481 }; 482 483 sysreg_cam: system-controller@12630000 { 484 compatible = "tesla,fsd-cam-sysreg", "syscon"; 485 reg = <0x0 0x12630000 0x0 0x500>; 486 }; 487 488 clock_mfc: clock-controller@12810000 { 489 compatible = "tesla,fsd-clock-mfc"; 490 reg = <0x0 0x12810000 0x0 0x3000>; 491 #clock-cells = <1>; 492 clocks = <&fin_pll>; 493 clock-names = "fin_pll"; 494 }; 495 496 clock_peric: clock-controller@14010000 { 497 compatible = "tesla,fsd-clock-peric"; 498 reg = <0x0 0x14010000 0x0 0x3000>; 499 #clock-cells = <1>; 500 clocks = <&fin_pll>, 501 <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV4>, 502 <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV36>, 503 <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK>, 504 <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV20>, 505 <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV4_DMACLK>; 506 clock-names = "fin_pll", 507 "dout_cmu_pll_shared0_div4", 508 "dout_cmu_peric_shared1div36", 509 "dout_cmu_peric_shared0div3_tbuclk", 510 "dout_cmu_peric_shared0div20", 511 "dout_cmu_peric_shared1div4_dmaclk"; 512 }; 513 514 sysreg_peric: system-controller@14030000 { 515 compatible = "tesla,fsd-peric-sysreg", "syscon"; 516 reg = <0x0 0x14030000 0x0 0x1000>; 517 }; 518 519 clock_fsys0: clock-controller@15010000 { 520 compatible = "tesla,fsd-clock-fsys0"; 521 reg = <0x0 0x15010000 0x0 0x3000>; 522 #clock-cells = <1>; 523 clocks = <&fin_pll>, 524 <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV6>, 525 <&clock_cmu DOUT_CMU_FSYS0_SHARED1DIV4>, 526 <&clock_cmu DOUT_CMU_FSYS0_SHARED0DIV4>; 527 clock-names = "fin_pll", 528 "dout_cmu_pll_shared0_div6", 529 "dout_cmu_fsys0_shared1div4", 530 "dout_cmu_fsys0_shared0div4"; 531 }; 532 533 sysreg_fsys0: system-controller@15030000 { 534 compatible = "tesla,fsd-fsys0-sysreg", "syscon"; 535 reg = <0x0 0x15030000 0x0 0x1000>; 536 }; 537 538 clock_fsys1: clock-controller@16810000 { 539 compatible = "tesla,fsd-clock-fsys1"; 540 reg = <0x0 0x16810000 0x0 0x3000>; 541 #clock-cells = <1>; 542 clocks = <&fin_pll>, 543 <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>, 544 <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>; 545 clock-names = "fin_pll", 546 "dout_cmu_fsys1_shared0div8", 547 "dout_cmu_fsys1_shared0div4"; 548 }; 549 550 sysreg_fsys1: system-controller@16830000 { 551 compatible = "tesla,fsd-fsys1-sysreg", "syscon"; 552 reg = <0x0 0x16830000 0x0 0x1000>; 553 }; 554 555 mdma0: dma-controller@10100000 { 556 compatible = "arm,pl330", "arm,primecell"; 557 reg = <0x0 0x10100000 0x0 0x1000>; 558 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>; 559 #dma-cells = <1>; 560 clocks = <&clock_imem IMEM_DMA0_IPCLKPORT_ACLK>; 561 clock-names = "apb_pclk"; 562 iommus = <&smmu_imem 0x800 0x0>; 563 }; 564 565 mdma1: dma-controller@10110000 { 566 compatible = "arm,pl330", "arm,primecell"; 567 reg = <0x0 0x10110000 0x0 0x1000>; 568 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 569 #dma-cells = <1>; 570 clocks = <&clock_imem IMEM_DMA1_IPCLKPORT_ACLK>; 571 clock-names = "apb_pclk"; 572 iommus = <&smmu_imem 0x801 0x0>; 573 }; 574 575 pdma0: dma-controller@14280000 { 576 compatible = "arm,pl330", "arm,primecell"; 577 reg = <0x0 0x14280000 0x0 0x1000>; 578 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 579 #dma-cells = <1>; 580 clocks = <&clock_peric PERIC_DMA0_IPCLKPORT_ACLK>; 581 clock-names = "apb_pclk"; 582 iommus = <&smmu_peric 0x2 0x0>; 583 }; 584 585 pdma1: dma-controller@14290000 { 586 compatible = "arm,pl330", "arm,primecell"; 587 reg = <0x0 0x14290000 0x0 0x1000>; 588 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 589 #dma-cells = <1>; 590 clocks = <&clock_peric PERIC_DMA1_IPCLKPORT_ACLK>; 591 clock-names = "apb_pclk"; 592 iommus = <&smmu_peric 0x1 0x0>; 593 }; 594 595 serial_0: serial@14180000 { 596 compatible = "tesla,fsd-uart", "samsung,exynos4210-uart"; 597 reg = <0x0 0x14180000 0x0 0x100>; 598 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 599 dmas = <&pdma1 1>, <&pdma1 0>; 600 dma-names = "rx", "tx"; 601 clocks = <&clock_peric PERIC_PCLK_UART0>, 602 <&clock_peric PERIC_SCLK_UART0>; 603 clock-names = "uart", "clk_uart_baud0"; 604 status = "disabled"; 605 }; 606 607 serial_1: serial@14190000 { 608 compatible = "tesla,fsd-uart", "samsung,exynos4210-uart"; 609 reg = <0x0 0x14190000 0x0 0x100>; 610 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 611 dmas = <&pdma1 3>, <&pdma1 2>; 612 dma-names = "rx", "tx"; 613 clocks = <&clock_peric PERIC_PCLK_UART1>, 614 <&clock_peric PERIC_SCLK_UART1>; 615 clock-names = "uart", "clk_uart_baud0"; 616 status = "disabled"; 617 }; 618 619 pmu_system_controller: system-controller@11400000 { 620 compatible = "tesla,fsd-pmu", "samsung,exynos7-pmu", "syscon"; 621 reg = <0x0 0x11400000 0x0 0x5000>; 622 }; 623 624 watchdog_0: watchdog@100a0000 { 625 compatible = "tesla,fsd-wdt", "samsung,exynos7-wdt"; 626 reg = <0x0 0x100a0000 0x0 0x100>; 627 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 628 samsung,syscon-phandle = <&pmu_system_controller>; 629 clocks = <&fin_pll>; 630 clock-names = "watchdog"; 631 }; 632 633 watchdog_1: watchdog@100b0000 { 634 compatible = "tesla,fsd-wdt", "samsung,exynos7-wdt"; 635 reg = <0x0 0x100b0000 0x0 0x100>; 636 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 637 samsung,syscon-phandle = <&pmu_system_controller>; 638 clocks = <&fin_pll>; 639 clock-names = "watchdog"; 640 }; 641 642 watchdog_2: watchdog@100c0000 { 643 compatible = "tesla,fsd-wdt", "samsung,exynos7-wdt"; 644 reg = <0x0 0x100c0000 0x0 0x100>; 645 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 646 samsung,syscon-phandle = <&pmu_system_controller>; 647 clocks = <&fin_pll>; 648 clock-names = "watchdog"; 649 }; 650 651 pwm_0: pwm@14100000 { 652 compatible = "tesla,fsd-pwm", "samsung,exynos4210-pwm"; 653 reg = <0x0 0x14100000 0x0 0x100>; 654 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 655 #pwm-cells = <3>; 656 clocks = <&clock_peric PERIC_PWM0_IPCLKPORT_I_PCLK_S0>; 657 clock-names = "timers"; 658 status = "disabled"; 659 }; 660 661 pwm_1: pwm@14110000 { 662 compatible = "tesla,fsd-pwm", "samsung,exynos4210-pwm"; 663 reg = <0x0 0x14110000 0x0 0x100>; 664 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 665 #pwm-cells = <3>; 666 clocks = <&clock_peric PERIC_PWM1_IPCLKPORT_I_PCLK_S0>; 667 clock-names = "timers"; 668 status = "disabled"; 669 }; 670 671 hsi2c_0: i2c@14200000 { 672 compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c"; 673 reg = <0x0 0x14200000 0x0 0x1000>; 674 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 675 #address-cells = <1>; 676 #size-cells = <0>; 677 pinctrl-names = "default"; 678 pinctrl-0 = <&hs_i2c0_bus>; 679 clocks = <&clock_peric PERIC_PCLK_HSI2C0>; 680 clock-names = "hsi2c"; 681 status = "disabled"; 682 }; 683 684 hsi2c_1: i2c@14210000 { 685 compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c"; 686 reg = <0x0 0x14210000 0x0 0x1000>; 687 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 688 #address-cells = <1>; 689 #size-cells = <0>; 690 pinctrl-names = "default"; 691 pinctrl-0 = <&hs_i2c1_bus>; 692 clocks = <&clock_peric PERIC_PCLK_HSI2C1>; 693 clock-names = "hsi2c"; 694 status = "disabled"; 695 }; 696 697 hsi2c_2: i2c@14220000 { 698 compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c"; 699 reg = <0x0 0x14220000 0x0 0x1000>; 700 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 701 #address-cells = <1>; 702 #size-cells = <0>; 703 pinctrl-names = "default"; 704 pinctrl-0 = <&hs_i2c2_bus>; 705 clocks = <&clock_peric PERIC_PCLK_HSI2C2>; 706 clock-names = "hsi2c"; 707 status = "disabled"; 708 }; 709 710 hsi2c_3: i2c@14230000 { 711 compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c"; 712 reg = <0x0 0x14230000 0x0 0x1000>; 713 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 714 #address-cells = <1>; 715 #size-cells = <0>; 716 pinctrl-names = "default"; 717 pinctrl-0 = <&hs_i2c3_bus>; 718 clocks = <&clock_peric PERIC_PCLK_HSI2C3>; 719 clock-names = "hsi2c"; 720 status = "disabled"; 721 }; 722 723 hsi2c_4: i2c@14240000 { 724 compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c"; 725 reg = <0x0 0x14240000 0x0 0x1000>; 726 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 727 #address-cells = <1>; 728 #size-cells = <0>; 729 pinctrl-names = "default"; 730 pinctrl-0 = <&hs_i2c4_bus>; 731 clocks = <&clock_peric PERIC_PCLK_HSI2C4>; 732 clock-names = "hsi2c"; 733 status = "disabled"; 734 }; 735 736 hsi2c_5: i2c@14250000 { 737 compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c"; 738 reg = <0x0 0x14250000 0x0 0x1000>; 739 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 740 #address-cells = <1>; 741 #size-cells = <0>; 742 pinctrl-names = "default"; 743 pinctrl-0 = <&hs_i2c5_bus>; 744 clocks = <&clock_peric PERIC_PCLK_HSI2C5>; 745 clock-names = "hsi2c"; 746 status = "disabled"; 747 }; 748 749 hsi2c_6: i2c@14260000 { 750 compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c"; 751 reg = <0x0 0x14260000 0x0 0x1000>; 752 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 753 #address-cells = <1>; 754 #size-cells = <0>; 755 pinctrl-names = "default"; 756 pinctrl-0 = <&hs_i2c6_bus>; 757 clocks = <&clock_peric PERIC_PCLK_HSI2C6>; 758 clock-names = "hsi2c"; 759 status = "disabled"; 760 }; 761 762 hsi2c_7: i2c@14270000 { 763 compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c"; 764 reg = <0x0 0x14270000 0x0 0x1000>; 765 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 766 #address-cells = <1>; 767 #size-cells = <0>; 768 pinctrl-names = "default"; 769 pinctrl-0 = <&hs_i2c7_bus>; 770 clocks = <&clock_peric PERIC_PCLK_HSI2C7>; 771 clock-names = "hsi2c"; 772 status = "disabled"; 773 }; 774 775 i2s_0: i2s@140e0000 { 776 compatible = "tesla,fsd-i2s"; 777 reg = <0x0 0x140e0000 0x0 0x100>; 778 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 779 dmas = <&pdma1 14>, <&pdma1 13>, <&pdma1 12>; 780 dma-names = "tx", "rx", "tx-sec"; 781 #clock-cells = <1>; 782 clocks = <&clock_peric PERIC_PCLK_TDM0>, 783 <&clock_peric PERIC_HCLK_TDM0>, 784 <&clock_peric PERIC_HCLK_TDM0>; 785 clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; 786 pinctrl-names = "default"; 787 pinctrl-0 = <&i2s0_bus>; 788 #sound-dai-cells = <1>; 789 status = "disabled"; 790 }; 791 792 i2s_1: i2s@140f0000 { 793 compatible = "tesla,fsd-i2s"; 794 reg = <0x0 0x140f0000 0x0 0x100>; 795 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 796 dmas = <&pdma1 17>, <&pdma1 16>, <&pdma1 15>; 797 dma-names = "tx", "rx", "tx-sec"; 798 #clock-cells = <1>; 799 clocks = <&clock_peric PERIC_PCLK_TDM1>, 800 <&clock_peric PERIC_HCLK_TDM1>, 801 <&clock_peric PERIC_HCLK_TDM1>; 802 clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; 803 pinctrl-names = "default"; 804 pinctrl-0 = <&i2s1_bus>; 805 #sound-dai-cells = <1>; 806 status = "disabled"; 807 }; 808 809 pinctrl_pmu: pinctrl@114f0000 { 810 compatible = "tesla,fsd-pinctrl"; 811 reg = <0x0 0x114f0000 0x0 0x1000>; 812 }; 813 814 pinctrl_peric: pinctrl@141f0000 { 815 compatible = "tesla,fsd-pinctrl"; 816 reg = <0x0 0x141f0000 0x0 0x1000>; 817 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 818 }; 819 820 pinctrl_fsys0: pinctrl@15020000 { 821 compatible = "tesla,fsd-pinctrl"; 822 reg = <0x0 0x15020000 0x0 0x1000>; 823 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 824 }; 825 826 m_can0: can@14088000 { 827 compatible = "bosch,m_can"; 828 reg = <0x0 0x14088000 0x0 0x0200>, 829 <0x0 0x14080000 0x0 0x8000>; 830 reg-names = "m_can", "message_ram"; 831 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 833 interrupt-names = "int0", "int1"; 834 pinctrl-names = "default"; 835 pinctrl-0 = <&m_can0_bus>; 836 clocks = <&clock_peric PERIC_MCAN0_IPCLKPORT_PCLK>, 837 <&clock_peric PERIC_MCAN0_IPCLKPORT_CCLK>; 838 clock-names = "hclk", "cclk"; 839 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 840 status = "disabled"; 841 }; 842 843 m_can1: can@14098000 { 844 compatible = "bosch,m_can"; 845 reg = <0x0 0x14098000 0x0 0x0200>, 846 <0x0 0x14090000 0x0 0x8000>; 847 reg-names = "m_can", "message_ram"; 848 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 849 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 850 interrupt-names = "int0", "int1"; 851 pinctrl-names = "default"; 852 pinctrl-0 = <&m_can1_bus>; 853 clocks = <&clock_peric PERIC_MCAN1_IPCLKPORT_PCLK>, 854 <&clock_peric PERIC_MCAN1_IPCLKPORT_CCLK>; 855 clock-names = "hclk", "cclk"; 856 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 857 status = "disabled"; 858 }; 859 860 m_can2: can@140a8000 { 861 compatible = "bosch,m_can"; 862 reg = <0x0 0x140a8000 0x0 0x0200>, 863 <0x0 0x140a0000 0x0 0x8000>; 864 reg-names = "m_can", "message_ram"; 865 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 867 interrupt-names = "int0", "int1"; 868 pinctrl-names = "default"; 869 pinctrl-0 = <&m_can2_bus>; 870 clocks = <&clock_peric PERIC_MCAN2_IPCLKPORT_PCLK>, 871 <&clock_peric PERIC_MCAN2_IPCLKPORT_CCLK>; 872 clock-names = "hclk", "cclk"; 873 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 874 status = "disabled"; 875 }; 876 877 m_can3: can@140b8000 { 878 compatible = "bosch,m_can"; 879 reg = <0x0 0x140b8000 0x0 0x0200>, 880 <0x0 0x140b0000 0x0 0x8000>; 881 reg-names = "m_can", "message_ram"; 882 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 884 interrupt-names = "int0", "int1"; 885 pinctrl-names = "default"; 886 pinctrl-0 = <&m_can3_bus>; 887 clocks = <&clock_peric PERIC_MCAN3_IPCLKPORT_PCLK>, 888 <&clock_peric PERIC_MCAN3_IPCLKPORT_CCLK>; 889 clock-names = "hclk", "cclk"; 890 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 891 status = "disabled"; 892 }; 893 894 spi_0: spi@14140000 { 895 compatible = "tesla,fsd-spi"; 896 reg = <0x0 0x14140000 0x0 0x100>; 897 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 898 dmas = <&pdma1 4>, <&pdma1 5>; 899 dma-names = "tx", "rx"; 900 #address-cells = <1>; 901 #size-cells = <0>; 902 clocks = <&clock_peric PERIC_PCLK_SPI0>, 903 <&clock_peric PERIC_SCLK_SPI0>; 904 clock-names = "spi", "spi_busclk0"; 905 samsung,spi-src-clk = <0>; 906 pinctrl-names = "default"; 907 pinctrl-0 = <&spi0_bus>; 908 num-cs = <1>; 909 status = "disabled"; 910 }; 911 912 spi_1: spi@14150000 { 913 compatible = "tesla,fsd-spi"; 914 reg = <0x0 0x14150000 0x0 0x100>; 915 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 916 dmas = <&pdma1 6>, <&pdma1 7>; 917 dma-names = "tx", "rx"; 918 #address-cells = <1>; 919 #size-cells = <0>; 920 clocks = <&clock_peric PERIC_PCLK_SPI1>, 921 <&clock_peric PERIC_SCLK_SPI1>; 922 clock-names = "spi", "spi_busclk0"; 923 samsung,spi-src-clk = <0>; 924 pinctrl-names = "default"; 925 pinctrl-0 = <&spi1_bus>; 926 num-cs = <1>; 927 status = "disabled"; 928 }; 929 930 spi_2: spi@14160000 { 931 compatible = "tesla,fsd-spi"; 932 reg = <0x0 0x14160000 0x0 0x100>; 933 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 934 dmas = <&pdma1 8>, <&pdma1 9>; 935 dma-names = "tx", "rx"; 936 #address-cells = <1>; 937 #size-cells = <0>; 938 clocks = <&clock_peric PERIC_PCLK_SPI2>, 939 <&clock_peric PERIC_SCLK_SPI2>; 940 clock-names = "spi", "spi_busclk0"; 941 samsung,spi-src-clk = <0>; 942 pinctrl-names = "default"; 943 pinctrl-0 = <&spi2_bus>; 944 num-cs = <1>; 945 status = "disabled"; 946 }; 947 948 timer@10040000 { 949 compatible = "tesla,fsd-mct", "samsung,exynos4210-mct"; 950 reg = <0x0 0x10040000 0x0 0x800>; 951 interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 962 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 965 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 967 clocks = <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>; 968 clock-names = "fin_pll", "mct"; 969 }; 970 971 mfc: mfc@12880000 { 972 compatible = "tesla,fsd-mfc"; 973 reg = <0x0 0x12880000 0x0 0x10000>; 974 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 975 clock-names = "mfc"; 976 clocks = <&clock_mfc MFC_MFC_IPCLKPORT_ACLK>; 977 memory-region = <&mfc_left>; 978 }; 979 980 ufs: ufs@15120000 { 981 compatible = "tesla,fsd-ufs"; 982 reg = <0x0 0x15120000 0x0 0x200>, /* 0: HCI standard */ 983 <0x0 0x15121100 0x0 0x200>, /* 1: Vendor specified */ 984 <0x0 0x15110000 0x0 0x8000>, /* 2: UNIPRO */ 985 <0x0 0x15130000 0x0 0x100>; /* 3: UFS protector */ 986 reg-names = "hci", "vs_hci", "unipro", "ufsp"; 987 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 988 clocks = <&clock_fsys0 UFS0_TOP0_HCLK_BUS>, 989 <&clock_fsys0 UFS0_TOP0_CLK_UNIPRO>; 990 clock-names = "core_clk", "sclk_unipro_main"; 991 freq-table-hz = <0 0>, <0 0>; 992 pinctrl-names = "default"; 993 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; 994 phys = <&ufs_phy>; 995 phy-names = "ufs-phy"; 996 status = "disabled"; 997 }; 998 999 ufs_phy: ufs-phy@15124000 { 1000 compatible = "tesla,fsd-ufs-phy"; 1001 reg = <0x0 0x15124000 0x0 0x800>; 1002 reg-names = "phy-pma"; 1003 samsung,pmu-syscon = <&pmu_system_controller>; 1004 #phy-cells = <0>; 1005 clocks = <&clock_fsys0 UFS0_MPHY_REFCLK_IXTAL26>; 1006 clock-names = "ref_clk"; 1007 }; 1008 }; 1009}; 1010 1011#include "fsd-pinctrl.dtsi" 1012