1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/clock/st,stm32mp25-rcc.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/reset/st,stm32mp25-rcc.h> 9#include <dt-bindings/regulator/st,stm32mp25-regulator.h> 10 11/ { 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a35"; 21 device_type = "cpu"; 22 reg = <0>; 23 enable-method = "psci"; 24 power-domains = <&CPU_PD0>; 25 power-domain-names = "psci"; 26 }; 27 }; 28 29 arm-pmu { 30 compatible = "arm,cortex-a35-pmu"; 31 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 32 interrupt-affinity = <&cpu0>; 33 interrupt-parent = <&intc>; 34 }; 35 36 arm_wdt: watchdog { 37 compatible = "arm,smc-wdt"; 38 arm,smc-id = <0xb200005a>; 39 status = "disabled"; 40 }; 41 42 clocks { 43 clk_dsi_txbyte: txbyteclk { 44 #clock-cells = <0>; 45 compatible = "fixed-clock"; 46 clock-frequency = <0>; 47 }; 48 49 clk_rcbsec: clk-rcbsec { 50 #clock-cells = <0>; 51 compatible = "fixed-clock"; 52 clock-frequency = <64000000>; 53 }; 54 }; 55 56 firmware { 57 optee: optee { 58 compatible = "linaro,optee-tz"; 59 method = "smc"; 60 interrupt-parent = <&intc>; 61 interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 62 }; 63 64 scmi { 65 compatible = "linaro,scmi-optee"; 66 #address-cells = <1>; 67 #size-cells = <0>; 68 linaro,optee-channel-id = <0>; 69 70 scmi_clk: protocol@14 { 71 reg = <0x14>; 72 #clock-cells = <1>; 73 }; 74 75 scmi_reset: protocol@16 { 76 reg = <0x16>; 77 #reset-cells = <1>; 78 }; 79 80 scmi_voltd: protocol@17 { 81 reg = <0x17>; 82 83 scmi_regu: regulators { 84 #address-cells = <1>; 85 #size-cells = <0>; 86 87 scmi_vddio1: regulator@0 { 88 reg = <VOLTD_SCMI_VDDIO1>; 89 regulator-name = "vddio1"; 90 }; 91 scmi_vddio2: regulator@1 { 92 reg = <VOLTD_SCMI_VDDIO2>; 93 regulator-name = "vddio2"; 94 }; 95 scmi_vddio3: regulator@2 { 96 reg = <VOLTD_SCMI_VDDIO3>; 97 regulator-name = "vddio3"; 98 }; 99 scmi_vddio4: regulator@3 { 100 reg = <VOLTD_SCMI_VDDIO4>; 101 regulator-name = "vddio4"; 102 }; 103 scmi_vdd33ucpd: regulator@5 { 104 reg = <VOLTD_SCMI_UCPD>; 105 regulator-name = "vdd33ucpd"; 106 }; 107 scmi_vdda18adc: regulator@7 { 108 reg = <VOLTD_SCMI_ADC>; 109 regulator-name = "vdda18adc"; 110 }; 111 }; 112 }; 113 }; 114 }; 115 116 intc: interrupt-controller@4ac00000 { 117 compatible = "arm,cortex-a7-gic"; 118 #interrupt-cells = <3>; 119 #address-cells = <1>; 120 interrupt-controller; 121 reg = <0x0 0x4ac10000 0x0 0x1000>, 122 <0x0 0x4ac20000 0x0 0x2000>, 123 <0x0 0x4ac40000 0x0 0x2000>, 124 <0x0 0x4ac60000 0x0 0x2000>; 125 }; 126 127 psci { 128 compatible = "arm,psci-1.0"; 129 method = "smc"; 130 131 CPU_PD0: power-domain-cpu0 { 132 #power-domain-cells = <0>; 133 power-domains = <&CLUSTER_PD>; 134 }; 135 136 CLUSTER_PD: power-domain-cluster { 137 #power-domain-cells = <0>; 138 power-domains = <&RET_PD>; 139 }; 140 141 RET_PD: power-domain-retention { 142 #power-domain-cells = <0>; 143 }; 144 }; 145 146 timer { 147 compatible = "arm,armv8-timer"; 148 interrupt-parent = <&intc>; 149 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 150 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 151 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 152 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 153 always-on; 154 }; 155 156 soc@0 { 157 compatible = "simple-bus"; 158 #address-cells = <1>; 159 #size-cells = <1>; 160 interrupt-parent = <&intc>; 161 ranges = <0x0 0x0 0x0 0x80000000>; 162 163 hpdma: dma-controller@40400000 { 164 compatible = "st,stm32mp25-dma3"; 165 reg = <0x40400000 0x1000>; 166 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 182 clocks = <&scmi_clk CK_SCMI_HPDMA1>; 183 #dma-cells = <3>; 184 }; 185 186 hpdma2: dma-controller@40410000 { 187 compatible = "st,stm32mp25-dma3"; 188 reg = <0x40410000 0x1000>; 189 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&scmi_clk CK_SCMI_HPDMA2>; 206 #dma-cells = <3>; 207 }; 208 209 hpdma3: dma-controller@40420000 { 210 compatible = "st,stm32mp25-dma3"; 211 reg = <0x40420000 0x1000>; 212 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&scmi_clk CK_SCMI_HPDMA3>; 229 #dma-cells = <3>; 230 }; 231 232 rifsc: bus@42080000 { 233 compatible = "st,stm32mp25-rifsc", "simple-bus"; 234 reg = <0x42080000 0x1000>; 235 #address-cells = <1>; 236 #size-cells = <1>; 237 #access-controller-cells = <1>; 238 ranges; 239 240 spi2: spi@400b0000 { 241 #address-cells = <1>; 242 #size-cells = <0>; 243 compatible = "st,stm32mp25-spi"; 244 reg = <0x400b0000 0x400>; 245 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&rcc CK_KER_SPI2>; 247 resets = <&rcc SPI2_R>; 248 dmas = <&hpdma 51 0x20 0x3012>, 249 <&hpdma 52 0x20 0x3021>; 250 dma-names = "rx", "tx"; 251 access-controllers = <&rifsc 23>; 252 status = "disabled"; 253 }; 254 255 spi3: spi@400c0000 { 256 #address-cells = <1>; 257 #size-cells = <0>; 258 compatible = "st,stm32mp25-spi"; 259 reg = <0x400c0000 0x400>; 260 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&rcc CK_KER_SPI3>; 262 resets = <&rcc SPI3_R>; 263 dmas = <&hpdma 53 0x20 0x3012>, 264 <&hpdma 54 0x20 0x3021>; 265 dma-names = "rx", "tx"; 266 access-controllers = <&rifsc 24>; 267 status = "disabled"; 268 }; 269 270 usart2: serial@400e0000 { 271 compatible = "st,stm32h7-uart"; 272 reg = <0x400e0000 0x400>; 273 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 274 clocks = <&rcc CK_KER_USART2>; 275 dmas = <&hpdma 11 0x20 0x10012>, 276 <&hpdma 12 0x20 0x3021>; 277 dma-names = "rx", "tx"; 278 access-controllers = <&rifsc 32>; 279 status = "disabled"; 280 }; 281 282 usart3: serial@400f0000 { 283 compatible = "st,stm32h7-uart"; 284 reg = <0x400f0000 0x400>; 285 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&rcc CK_KER_USART3>; 287 dmas = <&hpdma 13 0x20 0x10012>, 288 <&hpdma 14 0x20 0x3021>; 289 dma-names = "rx", "tx"; 290 access-controllers = <&rifsc 33>; 291 status = "disabled"; 292 }; 293 294 uart4: serial@40100000 { 295 compatible = "st,stm32h7-uart"; 296 reg = <0x40100000 0x400>; 297 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 298 clocks = <&rcc CK_KER_UART4>; 299 dmas = <&hpdma 15 0x20 0x10012>, 300 <&hpdma 16 0x20 0x3021>; 301 dma-names = "rx", "tx"; 302 access-controllers = <&rifsc 34>; 303 status = "disabled"; 304 }; 305 306 uart5: serial@40110000 { 307 compatible = "st,stm32h7-uart"; 308 reg = <0x40110000 0x400>; 309 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&rcc CK_KER_UART5>; 311 dmas = <&hpdma 17 0x20 0x10012>, 312 <&hpdma 18 0x20 0x3021>; 313 dma-names = "rx", "tx"; 314 access-controllers = <&rifsc 35>; 315 status = "disabled"; 316 }; 317 318 i2c1: i2c@40120000 { 319 compatible = "st,stm32mp25-i2c"; 320 reg = <0x40120000 0x400>; 321 interrupt-names = "event"; 322 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&rcc CK_KER_I2C1>; 324 resets = <&rcc I2C1_R>; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 dmas = <&hpdma 27 0x20 0x3012>, 328 <&hpdma 28 0x20 0x3021>; 329 dma-names = "rx", "tx"; 330 access-controllers = <&rifsc 41>; 331 status = "disabled"; 332 }; 333 334 i2c2: i2c@40130000 { 335 compatible = "st,stm32mp25-i2c"; 336 reg = <0x40130000 0x400>; 337 interrupt-names = "event"; 338 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&rcc CK_KER_I2C2>; 340 resets = <&rcc I2C2_R>; 341 #address-cells = <1>; 342 #size-cells = <0>; 343 dmas = <&hpdma 30 0x20 0x3012>, 344 <&hpdma 31 0x20 0x3021>; 345 dma-names = "rx", "tx"; 346 access-controllers = <&rifsc 42>; 347 status = "disabled"; 348 }; 349 350 i2c3: i2c@40140000 { 351 compatible = "st,stm32mp25-i2c"; 352 reg = <0x40140000 0x400>; 353 interrupt-names = "event"; 354 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 355 clocks = <&rcc CK_KER_I2C3>; 356 resets = <&rcc I2C3_R>; 357 #address-cells = <1>; 358 #size-cells = <0>; 359 dmas = <&hpdma 33 0x20 0x3012>, 360 <&hpdma 34 0x20 0x3021>; 361 dma-names = "rx", "tx"; 362 access-controllers = <&rifsc 43>; 363 status = "disabled"; 364 }; 365 366 i2c4: i2c@40150000 { 367 compatible = "st,stm32mp25-i2c"; 368 reg = <0x40150000 0x400>; 369 interrupt-names = "event"; 370 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&rcc CK_KER_I2C4>; 372 resets = <&rcc I2C4_R>; 373 #address-cells = <1>; 374 #size-cells = <0>; 375 dmas = <&hpdma 36 0x20 0x3012>, 376 <&hpdma 37 0x20 0x3021>; 377 dma-names = "rx", "tx"; 378 access-controllers = <&rifsc 44>; 379 status = "disabled"; 380 }; 381 382 i2c5: i2c@40160000 { 383 compatible = "st,stm32mp25-i2c"; 384 reg = <0x40160000 0x400>; 385 interrupt-names = "event"; 386 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&rcc CK_KER_I2C5>; 388 resets = <&rcc I2C5_R>; 389 #address-cells = <1>; 390 #size-cells = <0>; 391 dmas = <&hpdma 39 0x20 0x3012>, 392 <&hpdma 40 0x20 0x3021>; 393 dma-names = "rx", "tx"; 394 access-controllers = <&rifsc 45>; 395 status = "disabled"; 396 }; 397 398 i2c6: i2c@40170000 { 399 compatible = "st,stm32mp25-i2c"; 400 reg = <0x40170000 0x400>; 401 interrupt-names = "event"; 402 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&rcc CK_KER_I2C6>; 404 resets = <&rcc I2C6_R>; 405 #address-cells = <1>; 406 #size-cells = <0>; 407 dmas = <&hpdma 42 0x20 0x3012>, 408 <&hpdma 43 0x20 0x3021>; 409 dma-names = "rx", "tx"; 410 access-controllers = <&rifsc 46>; 411 status = "disabled"; 412 }; 413 414 i2c7: i2c@40180000 { 415 compatible = "st,stm32mp25-i2c"; 416 reg = <0x40180000 0x400>; 417 interrupt-names = "event"; 418 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&rcc CK_KER_I2C7>; 420 resets = <&rcc I2C7_R>; 421 #address-cells = <1>; 422 #size-cells = <0>; 423 dmas = <&hpdma 45 0x20 0x3012>, 424 <&hpdma 46 0x20 0x3021>; 425 dma-names = "rx", "tx"; 426 access-controllers = <&rifsc 47>; 427 status = "disabled"; 428 }; 429 430 usart6: serial@40220000 { 431 compatible = "st,stm32h7-uart"; 432 reg = <0x40220000 0x400>; 433 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 434 clocks = <&rcc CK_KER_USART6>; 435 dmas = <&hpdma 19 0x20 0x10012>, 436 <&hpdma 20 0x20 0x3021>; 437 dma-names = "rx", "tx"; 438 access-controllers = <&rifsc 36>; 439 status = "disabled"; 440 }; 441 442 spi1: spi@40230000 { 443 #address-cells = <1>; 444 #size-cells = <0>; 445 compatible = "st,stm32mp25-spi"; 446 reg = <0x40230000 0x400>; 447 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&rcc CK_KER_SPI1>; 449 resets = <&rcc SPI1_R>; 450 dmas = <&hpdma 49 0x20 0x3012>, 451 <&hpdma 50 0x20 0x3021>; 452 dma-names = "rx", "tx"; 453 access-controllers = <&rifsc 22>; 454 status = "disabled"; 455 }; 456 457 spi4: spi@40240000 { 458 #address-cells = <1>; 459 #size-cells = <0>; 460 compatible = "st,stm32mp25-spi"; 461 reg = <0x40240000 0x400>; 462 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&rcc CK_KER_SPI4>; 464 resets = <&rcc SPI4_R>; 465 dmas = <&hpdma 55 0x20 0x3012>, 466 <&hpdma 56 0x20 0x3021>; 467 dma-names = "rx", "tx"; 468 access-controllers = <&rifsc 25>; 469 status = "disabled"; 470 }; 471 472 spi5: spi@40280000 { 473 #address-cells = <1>; 474 #size-cells = <0>; 475 compatible = "st,stm32mp25-spi"; 476 reg = <0x40280000 0x400>; 477 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 478 clocks = <&rcc CK_KER_SPI5>; 479 resets = <&rcc SPI5_R>; 480 dmas = <&hpdma 57 0x20 0x3012>, 481 <&hpdma 58 0x20 0x3021>; 482 dma-names = "rx", "tx"; 483 access-controllers = <&rifsc 26>; 484 status = "disabled"; 485 }; 486 487 uart9: serial@402c0000 { 488 compatible = "st,stm32h7-uart"; 489 reg = <0x402c0000 0x400>; 490 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 491 clocks = <&rcc CK_KER_UART9>; 492 dmas = <&hpdma 25 0x20 0x10012>, 493 <&hpdma 26 0x20 0x3021>; 494 dma-names = "rx", "tx"; 495 access-controllers = <&rifsc 39>; 496 status = "disabled"; 497 }; 498 499 usart1: serial@40330000 { 500 compatible = "st,stm32h7-uart"; 501 reg = <0x40330000 0x400>; 502 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&rcc CK_KER_USART1>; 504 dmas = <&hpdma 9 0x20 0x10012>, 505 <&hpdma 10 0x20 0x3021>; 506 dma-names = "rx", "tx"; 507 access-controllers = <&rifsc 31>; 508 status = "disabled"; 509 }; 510 511 spi6: spi@40350000 { 512 #address-cells = <1>; 513 #size-cells = <0>; 514 compatible = "st,stm32mp25-spi"; 515 reg = <0x40350000 0x400>; 516 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&rcc CK_KER_SPI6>; 518 resets = <&rcc SPI6_R>; 519 dmas = <&hpdma 59 0x20 0x3012>, 520 <&hpdma 60 0x20 0x3021>; 521 dma-names = "rx", "tx"; 522 access-controllers = <&rifsc 27>; 523 status = "disabled"; 524 }; 525 526 spi7: spi@40360000 { 527 #address-cells = <1>; 528 #size-cells = <0>; 529 compatible = "st,stm32mp25-spi"; 530 reg = <0x40360000 0x400>; 531 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&rcc CK_KER_SPI7>; 533 resets = <&rcc SPI7_R>; 534 dmas = <&hpdma 61 0x20 0x3012>, 535 <&hpdma 62 0x20 0x3021>; 536 dma-names = "rx", "tx"; 537 access-controllers = <&rifsc 28>; 538 status = "disabled"; 539 }; 540 541 uart7: serial@40370000 { 542 compatible = "st,stm32h7-uart"; 543 reg = <0x40370000 0x400>; 544 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 545 clocks = <&rcc CK_KER_UART7>; 546 dmas = <&hpdma 21 0x20 0x10012>, 547 <&hpdma 22 0x20 0x3021>; 548 dma-names = "rx", "tx"; 549 access-controllers = <&rifsc 37>; 550 status = "disabled"; 551 }; 552 553 uart8: serial@40380000 { 554 compatible = "st,stm32h7-uart"; 555 reg = <0x40380000 0x400>; 556 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 557 clocks = <&rcc CK_KER_UART8>; 558 dmas = <&hpdma 23 0x20 0x10012>, 559 <&hpdma 24 0x20 0x3021>; 560 dma-names = "rx", "tx"; 561 access-controllers = <&rifsc 38>; 562 status = "disabled"; 563 }; 564 565 rng: rng@42020000 { 566 compatible = "st,stm32mp25-rng"; 567 reg = <0x42020000 0x400>; 568 clocks = <&clk_rcbsec>, <&rcc CK_BUS_RNG>; 569 clock-names = "core", "bus"; 570 resets = <&rcc RNG_R>; 571 access-controllers = <&rifsc 92>; 572 status = "disabled"; 573 }; 574 575 spi8: spi@46020000 { 576 #address-cells = <1>; 577 #size-cells = <0>; 578 compatible = "st,stm32mp25-spi"; 579 reg = <0x46020000 0x400>; 580 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&rcc CK_KER_SPI8>; 582 resets = <&rcc SPI8_R>; 583 dmas = <&hpdma 171 0x20 0x3012>, 584 <&hpdma 172 0x20 0x3021>; 585 dma-names = "rx", "tx"; 586 access-controllers = <&rifsc 29>; 587 status = "disabled"; 588 }; 589 590 i2c8: i2c@46040000 { 591 compatible = "st,stm32mp25-i2c"; 592 reg = <0x46040000 0x400>; 593 interrupt-names = "event"; 594 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&rcc CK_KER_I2C8>; 596 resets = <&rcc I2C8_R>; 597 #address-cells = <1>; 598 #size-cells = <0>; 599 dmas = <&hpdma 168 0x20 0x3012>, 600 <&hpdma 169 0x20 0x3021>; 601 dma-names = "rx", "tx"; 602 access-controllers = <&rifsc 48>; 603 status = "disabled"; 604 }; 605 606 sdmmc1: mmc@48220000 { 607 compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; 608 arm,primecell-periphid = <0x00353180>; 609 reg = <0x48220000 0x400>, <0x44230400 0x8>; 610 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 611 clocks = <&rcc CK_KER_SDMMC1 >; 612 clock-names = "apb_pclk"; 613 resets = <&rcc SDMMC1_R>; 614 cap-sd-highspeed; 615 cap-mmc-highspeed; 616 max-frequency = <120000000>; 617 access-controllers = <&rifsc 76>; 618 status = "disabled"; 619 }; 620 621 ethernet1: ethernet@482c0000 { 622 compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20"; 623 reg = <0x482c0000 0x4000>; 624 reg-names = "stmmaceth"; 625 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 626 interrupt-names = "macirq"; 627 clock-names = "stmmaceth", 628 "mac-clk-tx", 629 "mac-clk-rx", 630 "ptp_ref", 631 "ethstp", 632 "eth-ck"; 633 clocks = <&rcc CK_ETH1_MAC>, 634 <&rcc CK_ETH1_TX>, 635 <&rcc CK_ETH1_RX>, 636 <&rcc CK_KER_ETH1PTP>, 637 <&rcc CK_ETH1_STP>, 638 <&rcc CK_KER_ETH1>; 639 snps,axi-config = <&stmmac_axi_config_1>; 640 snps,mixed-burst; 641 snps,mtl-rx-config = <&mtl_rx_setup_1>; 642 snps,mtl-tx-config = <&mtl_tx_setup_1>; 643 snps,pbl = <2>; 644 snps,tso; 645 st,syscon = <&syscfg 0x3000>; 646 access-controllers = <&rifsc 60>; 647 status = "disabled"; 648 649 mtl_rx_setup_1: rx-queues-config { 650 snps,rx-queues-to-use = <2>; 651 queue0 {}; 652 queue1 {}; 653 }; 654 655 mtl_tx_setup_1: tx-queues-config { 656 snps,tx-queues-to-use = <4>; 657 queue0 {}; 658 queue1 {}; 659 queue2 {}; 660 queue3 {}; 661 }; 662 663 stmmac_axi_config_1: stmmac-axi-config { 664 snps,blen = <0 0 0 0 16 8 4>; 665 snps,rd_osr_lmt = <0x7>; 666 snps,wr_osr_lmt = <0x7>; 667 }; 668 }; 669 }; 670 671 bsec: efuse@44000000 { 672 compatible = "st,stm32mp25-bsec"; 673 reg = <0x44000000 0x1000>; 674 #address-cells = <1>; 675 #size-cells = <1>; 676 677 part_number_otp@24 { 678 reg = <0x24 0x4>; 679 }; 680 681 package_otp@1e8 { 682 reg = <0x1e8 0x1>; 683 bits = <0 3>; 684 }; 685 }; 686 687 rcc: clock-controller@44200000 { 688 compatible = "st,stm32mp25-rcc"; 689 reg = <0x44200000 0x10000>; 690 #clock-cells = <1>; 691 #reset-cells = <1>; 692 clocks = <&scmi_clk CK_SCMI_HSE>, 693 <&scmi_clk CK_SCMI_HSI>, 694 <&scmi_clk CK_SCMI_MSI>, 695 <&scmi_clk CK_SCMI_LSE>, 696 <&scmi_clk CK_SCMI_LSI>, 697 <&scmi_clk CK_SCMI_HSE_DIV2>, 698 <&scmi_clk CK_SCMI_ICN_HS_MCU>, 699 <&scmi_clk CK_SCMI_ICN_LS_MCU>, 700 <&scmi_clk CK_SCMI_ICN_SDMMC>, 701 <&scmi_clk CK_SCMI_ICN_DDR>, 702 <&scmi_clk CK_SCMI_ICN_DISPLAY>, 703 <&scmi_clk CK_SCMI_ICN_HSL>, 704 <&scmi_clk CK_SCMI_ICN_NIC>, 705 <&scmi_clk CK_SCMI_ICN_VID>, 706 <&scmi_clk CK_SCMI_FLEXGEN_07>, 707 <&scmi_clk CK_SCMI_FLEXGEN_08>, 708 <&scmi_clk CK_SCMI_FLEXGEN_09>, 709 <&scmi_clk CK_SCMI_FLEXGEN_10>, 710 <&scmi_clk CK_SCMI_FLEXGEN_11>, 711 <&scmi_clk CK_SCMI_FLEXGEN_12>, 712 <&scmi_clk CK_SCMI_FLEXGEN_13>, 713 <&scmi_clk CK_SCMI_FLEXGEN_14>, 714 <&scmi_clk CK_SCMI_FLEXGEN_15>, 715 <&scmi_clk CK_SCMI_FLEXGEN_16>, 716 <&scmi_clk CK_SCMI_FLEXGEN_17>, 717 <&scmi_clk CK_SCMI_FLEXGEN_18>, 718 <&scmi_clk CK_SCMI_FLEXGEN_19>, 719 <&scmi_clk CK_SCMI_FLEXGEN_20>, 720 <&scmi_clk CK_SCMI_FLEXGEN_21>, 721 <&scmi_clk CK_SCMI_FLEXGEN_22>, 722 <&scmi_clk CK_SCMI_FLEXGEN_23>, 723 <&scmi_clk CK_SCMI_FLEXGEN_24>, 724 <&scmi_clk CK_SCMI_FLEXGEN_25>, 725 <&scmi_clk CK_SCMI_FLEXGEN_26>, 726 <&scmi_clk CK_SCMI_FLEXGEN_27>, 727 <&scmi_clk CK_SCMI_FLEXGEN_28>, 728 <&scmi_clk CK_SCMI_FLEXGEN_29>, 729 <&scmi_clk CK_SCMI_FLEXGEN_30>, 730 <&scmi_clk CK_SCMI_FLEXGEN_31>, 731 <&scmi_clk CK_SCMI_FLEXGEN_32>, 732 <&scmi_clk CK_SCMI_FLEXGEN_33>, 733 <&scmi_clk CK_SCMI_FLEXGEN_34>, 734 <&scmi_clk CK_SCMI_FLEXGEN_35>, 735 <&scmi_clk CK_SCMI_FLEXGEN_36>, 736 <&scmi_clk CK_SCMI_FLEXGEN_37>, 737 <&scmi_clk CK_SCMI_FLEXGEN_38>, 738 <&scmi_clk CK_SCMI_FLEXGEN_39>, 739 <&scmi_clk CK_SCMI_FLEXGEN_40>, 740 <&scmi_clk CK_SCMI_FLEXGEN_41>, 741 <&scmi_clk CK_SCMI_FLEXGEN_42>, 742 <&scmi_clk CK_SCMI_FLEXGEN_43>, 743 <&scmi_clk CK_SCMI_FLEXGEN_44>, 744 <&scmi_clk CK_SCMI_FLEXGEN_45>, 745 <&scmi_clk CK_SCMI_FLEXGEN_46>, 746 <&scmi_clk CK_SCMI_FLEXGEN_47>, 747 <&scmi_clk CK_SCMI_FLEXGEN_48>, 748 <&scmi_clk CK_SCMI_FLEXGEN_49>, 749 <&scmi_clk CK_SCMI_FLEXGEN_50>, 750 <&scmi_clk CK_SCMI_FLEXGEN_51>, 751 <&scmi_clk CK_SCMI_FLEXGEN_52>, 752 <&scmi_clk CK_SCMI_FLEXGEN_53>, 753 <&scmi_clk CK_SCMI_FLEXGEN_54>, 754 <&scmi_clk CK_SCMI_FLEXGEN_55>, 755 <&scmi_clk CK_SCMI_FLEXGEN_56>, 756 <&scmi_clk CK_SCMI_FLEXGEN_57>, 757 <&scmi_clk CK_SCMI_FLEXGEN_58>, 758 <&scmi_clk CK_SCMI_FLEXGEN_59>, 759 <&scmi_clk CK_SCMI_FLEXGEN_60>, 760 <&scmi_clk CK_SCMI_FLEXGEN_61>, 761 <&scmi_clk CK_SCMI_FLEXGEN_62>, 762 <&scmi_clk CK_SCMI_FLEXGEN_63>, 763 <&scmi_clk CK_SCMI_ICN_APB1>, 764 <&scmi_clk CK_SCMI_ICN_APB2>, 765 <&scmi_clk CK_SCMI_ICN_APB3>, 766 <&scmi_clk CK_SCMI_ICN_APB4>, 767 <&scmi_clk CK_SCMI_ICN_APBDBG>, 768 <&scmi_clk CK_SCMI_TIMG1>, 769 <&scmi_clk CK_SCMI_TIMG2>, 770 <&scmi_clk CK_SCMI_PLL3>, 771 <&clk_dsi_txbyte>; 772 access-controllers = <&rifsc 156>; 773 }; 774 775 exti1: interrupt-controller@44220000 { 776 compatible = "st,stm32mp1-exti", "syscon"; 777 interrupt-controller; 778 #interrupt-cells = <2>; 779 reg = <0x44220000 0x400>; 780 interrupts-extended = 781 <&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 782 <&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 783 <&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 784 <&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 785 <&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 786 <&intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 787 <&intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 788 <&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 789 <&intc GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 790 <&intc GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 791 <&intc GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 792 <&intc GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 793 <&intc GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 794 <&intc GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 795 <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 796 <&intc GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 797 <&intc GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 798 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 799 <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 800 <&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 801 <0>, /* EXTI_20 */ 802 <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 803 <&intc GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 804 <&intc GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 805 <&intc GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 806 <&intc GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 807 <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 808 <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 809 <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 810 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 811 <&intc GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 812 <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 813 <&intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 814 <&intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 815 <&intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 816 <0>, 817 <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 818 <&intc GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 819 <&intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 820 <&intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 821 <&intc GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 822 <&intc GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 823 <&intc GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 824 <&intc GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 825 <&intc GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 826 <&intc GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 827 <&intc GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 828 <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 829 <&intc GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 830 <&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 831 <&intc GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 832 <0>, 833 <0>, 834 <0>, 835 <0>, 836 <0>, 837 <0>, 838 <0>, 839 <0>, 840 <&intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 841 <0>, /* EXTI_60 */ 842 <&intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 843 <0>, 844 <0>, 845 <&intc GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 846 <0>, 847 <0>, 848 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 849 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 850 <0>, 851 <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ 852 <0>, 853 <&intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 854 <&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 855 <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 856 <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 857 <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 858 <&intc GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 859 <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 860 <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 861 <0>, /* EXTI_80 */ 862 <0>, 863 <0>, 864 <&intc GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 865 <&intc GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 866 }; 867 868 syscfg: syscon@44230000 { 869 compatible = "st,stm32mp25-syscfg", "syscon"; 870 reg = <0x44230000 0x10000>; 871 }; 872 873 pinctrl: pinctrl@44240000 { 874 #address-cells = <1>; 875 #size-cells = <1>; 876 compatible = "st,stm32mp257-pinctrl"; 877 ranges = <0 0x44240000 0xa0400>; 878 interrupt-parent = <&exti1>; 879 st,syscfg = <&exti1 0x60 0xff>; 880 pins-are-numbered; 881 882 gpioa: gpio@44240000 { 883 gpio-controller; 884 #gpio-cells = <2>; 885 interrupt-controller; 886 #interrupt-cells = <2>; 887 reg = <0x0 0x400>; 888 clocks = <&scmi_clk CK_SCMI_GPIOA>; 889 st,bank-name = "GPIOA"; 890 status = "disabled"; 891 }; 892 893 gpiob: gpio@44250000 { 894 gpio-controller; 895 #gpio-cells = <2>; 896 interrupt-controller; 897 #interrupt-cells = <2>; 898 reg = <0x10000 0x400>; 899 clocks = <&scmi_clk CK_SCMI_GPIOB>; 900 st,bank-name = "GPIOB"; 901 status = "disabled"; 902 }; 903 904 gpioc: gpio@44260000 { 905 gpio-controller; 906 #gpio-cells = <2>; 907 interrupt-controller; 908 #interrupt-cells = <2>; 909 reg = <0x20000 0x400>; 910 clocks = <&scmi_clk CK_SCMI_GPIOC>; 911 st,bank-name = "GPIOC"; 912 status = "disabled"; 913 }; 914 915 gpiod: gpio@44270000 { 916 gpio-controller; 917 #gpio-cells = <2>; 918 interrupt-controller; 919 #interrupt-cells = <2>; 920 reg = <0x30000 0x400>; 921 clocks = <&scmi_clk CK_SCMI_GPIOD>; 922 st,bank-name = "GPIOD"; 923 status = "disabled"; 924 }; 925 926 gpioe: gpio@44280000 { 927 gpio-controller; 928 #gpio-cells = <2>; 929 interrupt-controller; 930 #interrupt-cells = <2>; 931 reg = <0x40000 0x400>; 932 clocks = <&scmi_clk CK_SCMI_GPIOE>; 933 st,bank-name = "GPIOE"; 934 status = "disabled"; 935 }; 936 937 gpiof: gpio@44290000 { 938 gpio-controller; 939 #gpio-cells = <2>; 940 interrupt-controller; 941 #interrupt-cells = <2>; 942 reg = <0x50000 0x400>; 943 clocks = <&scmi_clk CK_SCMI_GPIOF>; 944 st,bank-name = "GPIOF"; 945 status = "disabled"; 946 }; 947 948 gpiog: gpio@442a0000 { 949 gpio-controller; 950 #gpio-cells = <2>; 951 interrupt-controller; 952 #interrupt-cells = <2>; 953 reg = <0x60000 0x400>; 954 clocks = <&scmi_clk CK_SCMI_GPIOG>; 955 st,bank-name = "GPIOG"; 956 status = "disabled"; 957 }; 958 959 gpioh: gpio@442b0000 { 960 gpio-controller; 961 #gpio-cells = <2>; 962 interrupt-controller; 963 #interrupt-cells = <2>; 964 reg = <0x70000 0x400>; 965 clocks = <&scmi_clk CK_SCMI_GPIOH>; 966 st,bank-name = "GPIOH"; 967 status = "disabled"; 968 }; 969 970 gpioi: gpio@442c0000 { 971 gpio-controller; 972 #gpio-cells = <2>; 973 interrupt-controller; 974 #interrupt-cells = <2>; 975 reg = <0x80000 0x400>; 976 clocks = <&scmi_clk CK_SCMI_GPIOI>; 977 st,bank-name = "GPIOI"; 978 status = "disabled"; 979 }; 980 981 gpioj: gpio@442d0000 { 982 gpio-controller; 983 #gpio-cells = <2>; 984 interrupt-controller; 985 #interrupt-cells = <2>; 986 reg = <0x90000 0x400>; 987 clocks = <&scmi_clk CK_SCMI_GPIOJ>; 988 st,bank-name = "GPIOJ"; 989 status = "disabled"; 990 }; 991 992 gpiok: gpio@442e0000 { 993 gpio-controller; 994 #gpio-cells = <2>; 995 interrupt-controller; 996 #interrupt-cells = <2>; 997 reg = <0xa0000 0x400>; 998 clocks = <&scmi_clk CK_SCMI_GPIOK>; 999 st,bank-name = "GPIOK"; 1000 status = "disabled"; 1001 }; 1002 }; 1003 1004 rtc: rtc@46000000 { 1005 compatible = "st,stm32mp25-rtc"; 1006 reg = <0x46000000 0x400>; 1007 clocks = <&scmi_clk CK_SCMI_RTC>, 1008 <&scmi_clk CK_SCMI_RTCCK>; 1009 clock-names = "pclk", "rtc_ck"; 1010 interrupts-extended = <&exti2 17 IRQ_TYPE_LEVEL_HIGH>; 1011 status = "disabled"; 1012 }; 1013 1014 pinctrl_z: pinctrl@46200000 { 1015 #address-cells = <1>; 1016 #size-cells = <1>; 1017 compatible = "st,stm32mp257-z-pinctrl"; 1018 ranges = <0 0x46200000 0x400>; 1019 interrupt-parent = <&exti1>; 1020 st,syscfg = <&exti1 0x60 0xff>; 1021 pins-are-numbered; 1022 1023 gpioz: gpio@46200000 { 1024 gpio-controller; 1025 #gpio-cells = <2>; 1026 interrupt-controller; 1027 #interrupt-cells = <2>; 1028 reg = <0 0x400>; 1029 clocks = <&scmi_clk CK_SCMI_GPIOZ>; 1030 st,bank-name = "GPIOZ"; 1031 st,bank-ioport = <11>; 1032 status = "disabled"; 1033 }; 1034 1035 }; 1036 1037 exti2: interrupt-controller@46230000 { 1038 compatible = "st,stm32mp1-exti", "syscon"; 1039 interrupt-controller; 1040 #interrupt-cells = <2>; 1041 reg = <0x46230000 0x400>; 1042 interrupts-extended = 1043 <&intc GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 1044 <&intc GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1045 <&intc GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1046 <&intc GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1047 <&intc GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1048 <&intc GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1049 <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1050 <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1051 <&intc GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1052 <&intc GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1053 <&intc GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 1054 <&intc GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1055 <&intc GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1056 <&intc GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1057 <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1058 <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1059 <&intc GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1060 <&intc GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1061 <0>, 1062 <0>, 1063 <0>, /* EXTI_20 */ 1064 <&intc GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1065 <&intc GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1066 <0>, 1067 <0>, 1068 <&intc GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1069 <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1070 <&intc GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 1071 <0>, 1072 <&intc GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1073 <&intc GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 1074 <&intc GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1075 <0>, 1076 <&intc GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1077 <&intc GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 1078 <0>, 1079 <0>, 1080 <&intc GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 1081 <0>, 1082 <0>, 1083 <&intc GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 1084 <0>, 1085 <0>, 1086 <&intc GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1087 <0>, 1088 <0>, 1089 <&intc GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1090 <0>, 1091 <&intc GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 1092 <&intc GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1093 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 1094 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1095 <&intc GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 1096 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1097 <0>, 1098 <0>, 1099 <0>, 1100 <0>, 1101 <0>, 1102 <0>, 1103 <0>, /* EXTI_60 */ 1104 <&intc GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 1105 <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1106 <0>, 1107 <&intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1108 <&intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1109 <&intc GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1110 <&intc GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1111 <0>, 1112 <0>, 1113 <&intc GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ 1114 }; 1115 }; 1116}; 1117