1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/clock/st,stm32mp25-rcc.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/reset/st,stm32mp25-rcc.h> 9#include <dt-bindings/regulator/st,stm32mp25-regulator.h> 10#include <dt-bindings/phy/phy.h> 11 12/ { 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu0: cpu@0 { 21 compatible = "arm,cortex-a35"; 22 device_type = "cpu"; 23 reg = <0>; 24 enable-method = "psci"; 25 power-domains = <&CPU_PD0>; 26 power-domain-names = "psci"; 27 }; 28 }; 29 30 arm-pmu { 31 compatible = "arm,cortex-a35-pmu"; 32 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 33 interrupt-affinity = <&cpu0>; 34 interrupt-parent = <&intc>; 35 }; 36 37 arm_wdt: watchdog { 38 compatible = "arm,smc-wdt"; 39 arm,smc-id = <0xb200005a>; 40 status = "disabled"; 41 }; 42 43 clocks { 44 clk_dsi_txbyte: txbyteclk { 45 #clock-cells = <0>; 46 compatible = "fixed-clock"; 47 clock-frequency = <0>; 48 }; 49 50 clk_rcbsec: clk-rcbsec { 51 #clock-cells = <0>; 52 compatible = "fixed-clock"; 53 clock-frequency = <64000000>; 54 }; 55 }; 56 57 firmware { 58 optee: optee { 59 compatible = "linaro,optee-tz"; 60 method = "smc"; 61 interrupt-parent = <&intc>; 62 interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 63 }; 64 65 scmi { 66 compatible = "linaro,scmi-optee"; 67 #address-cells = <1>; 68 #size-cells = <0>; 69 linaro,optee-channel-id = <0>; 70 71 scmi_clk: protocol@14 { 72 reg = <0x14>; 73 #clock-cells = <1>; 74 }; 75 76 scmi_reset: protocol@16 { 77 reg = <0x16>; 78 #reset-cells = <1>; 79 }; 80 81 scmi_voltd: protocol@17 { 82 reg = <0x17>; 83 84 scmi_regu: regulators { 85 #address-cells = <1>; 86 #size-cells = <0>; 87 88 scmi_vddio1: regulator@0 { 89 reg = <VOLTD_SCMI_VDDIO1>; 90 regulator-name = "vddio1"; 91 }; 92 scmi_vddio2: regulator@1 { 93 reg = <VOLTD_SCMI_VDDIO2>; 94 regulator-name = "vddio2"; 95 }; 96 scmi_vddio3: regulator@2 { 97 reg = <VOLTD_SCMI_VDDIO3>; 98 regulator-name = "vddio3"; 99 }; 100 scmi_vddio4: regulator@3 { 101 reg = <VOLTD_SCMI_VDDIO4>; 102 regulator-name = "vddio4"; 103 }; 104 scmi_vdd33ucpd: regulator@5 { 105 reg = <VOLTD_SCMI_UCPD>; 106 regulator-name = "vdd33ucpd"; 107 }; 108 scmi_vdda18adc: regulator@7 { 109 reg = <VOLTD_SCMI_ADC>; 110 regulator-name = "vdda18adc"; 111 }; 112 }; 113 }; 114 }; 115 }; 116 117 intc: interrupt-controller@4ac00000 { 118 compatible = "arm,gic-400"; 119 #interrupt-cells = <3>; 120 interrupt-controller; 121 reg = <0x0 0x4ac10000 0x0 0x1000>, 122 <0x0 0x4ac20000 0x0 0x20000>, 123 <0x0 0x4ac40000 0x0 0x20000>, 124 <0x0 0x4ac60000 0x0 0x20000>; 125 }; 126 127 psci { 128 compatible = "arm,psci-1.0"; 129 method = "smc"; 130 131 CPU_PD0: power-domain-cpu0 { 132 #power-domain-cells = <0>; 133 power-domains = <&CLUSTER_PD>; 134 }; 135 136 CLUSTER_PD: power-domain-cluster { 137 #power-domain-cells = <0>; 138 power-domains = <&RET_PD>; 139 }; 140 141 RET_PD: power-domain-retention { 142 #power-domain-cells = <0>; 143 }; 144 }; 145 146 timer { 147 compatible = "arm,armv8-timer"; 148 interrupt-parent = <&intc>; 149 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 150 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 151 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 152 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 153 arm,no-tick-in-suspend; 154 }; 155 156 soc@0 { 157 compatible = "simple-bus"; 158 #address-cells = <1>; 159 #size-cells = <1>; 160 interrupt-parent = <&intc>; 161 ranges = <0x0 0x0 0x0 0x80000000>; 162 163 hpdma: dma-controller@40400000 { 164 compatible = "st,stm32mp25-dma3"; 165 reg = <0x40400000 0x1000>; 166 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 182 clocks = <&scmi_clk CK_SCMI_HPDMA1>; 183 #dma-cells = <3>; 184 }; 185 186 hpdma2: dma-controller@40410000 { 187 compatible = "st,stm32mp25-dma3"; 188 reg = <0x40410000 0x1000>; 189 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&scmi_clk CK_SCMI_HPDMA2>; 206 #dma-cells = <3>; 207 }; 208 209 hpdma3: dma-controller@40420000 { 210 compatible = "st,stm32mp25-dma3"; 211 reg = <0x40420000 0x1000>; 212 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&scmi_clk CK_SCMI_HPDMA3>; 229 #dma-cells = <3>; 230 }; 231 232 ommanager: ommanager@40500000 { 233 compatible = "st,stm32mp25-omm"; 234 reg = <0x40500000 0x400>, <0x60000000 0x10000000>; 235 reg-names = "regs", "memory_map"; 236 ranges = <0 0 0x40430000 0x400>, 237 <1 0 0x40440000 0x400>; 238 clocks = <&rcc CK_BUS_OSPIIOM>, 239 <&scmi_clk CK_SCMI_OSPI1>, 240 <&scmi_clk CK_SCMI_OSPI2>; 241 clock-names = "omm", "ospi1", "ospi2"; 242 resets = <&rcc OSPIIOM_R>, 243 <&scmi_reset RST_SCMI_OSPI1>, 244 <&scmi_reset RST_SCMI_OSPI2>; 245 reset-names = "omm", "ospi1", "ospi2"; 246 access-controllers = <&rifsc 111>; 247 power-domains = <&CLUSTER_PD>; 248 #address-cells = <2>; 249 #size-cells = <1>; 250 st,syscfg-amcr = <&syscfg 0x2c00 0x7>; 251 status = "disabled"; 252 253 ospi1: spi@0 { 254 compatible = "st,stm32mp25-ospi"; 255 reg = <0 0 0x400>; 256 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 257 dmas = <&hpdma 2 0x62 0x3121>, 258 <&hpdma 2 0x42 0x3112>; 259 dma-names = "tx", "rx"; 260 clocks = <&scmi_clk CK_SCMI_OSPI1>; 261 resets = <&scmi_reset RST_SCMI_OSPI1>, 262 <&scmi_reset RST_SCMI_OSPI1DLL>; 263 access-controllers = <&rifsc 74>; 264 power-domains = <&CLUSTER_PD>; 265 st,syscfg-dlyb = <&syscfg 0x1000>; 266 status = "disabled"; 267 }; 268 269 ospi2: spi@1 { 270 compatible = "st,stm32mp25-ospi"; 271 reg = <1 0 0x400>; 272 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 273 dmas = <&hpdma 3 0x62 0x3121>, 274 <&hpdma 3 0x42 0x3112>; 275 dma-names = "tx", "rx"; 276 clocks = <&scmi_clk CK_SCMI_OSPI2>; 277 resets = <&scmi_reset RST_SCMI_OSPI2>, 278 <&scmi_reset RST_SCMI_OSPI2DLL>; 279 access-controllers = <&rifsc 75>; 280 power-domains = <&CLUSTER_PD>; 281 st,syscfg-dlyb = <&syscfg 0x1400>; 282 status = "disabled"; 283 }; 284 }; 285 286 rifsc: bus@42080000 { 287 compatible = "st,stm32mp25-rifsc", "simple-bus"; 288 reg = <0x42080000 0x1000>; 289 #address-cells = <1>; 290 #size-cells = <1>; 291 #access-controller-cells = <1>; 292 ranges; 293 294 timers2: timer@40000000 { 295 compatible = "st,stm32mp25-timers"; 296 reg = <0x40000000 0x400>; 297 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 298 interrupt-names = "global"; 299 clocks = <&rcc CK_KER_TIM2>; 300 clock-names = "int"; 301 #address-cells = <1>; 302 #size-cells = <0>; 303 access-controllers = <&rifsc 1>; 304 power-domains = <&CLUSTER_PD>; 305 status = "disabled"; 306 307 counter { 308 compatible = "st,stm32mp25-timer-counter"; 309 status = "disabled"; 310 }; 311 312 pwm { 313 compatible = "st,stm32mp25-pwm"; 314 #pwm-cells = <3>; 315 status = "disabled"; 316 }; 317 318 timer@1 { 319 compatible = "st,stm32mp25-timer-trigger"; 320 reg = <1>; 321 status = "disabled"; 322 }; 323 }; 324 325 timers3: timer@40010000 { 326 compatible = "st,stm32mp25-timers"; 327 reg = <0x40010000 0x400>; 328 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 329 interrupt-names = "global"; 330 clocks = <&rcc CK_KER_TIM3>; 331 clock-names = "int"; 332 #address-cells = <1>; 333 #size-cells = <0>; 334 access-controllers = <&rifsc 2>; 335 power-domains = <&CLUSTER_PD>; 336 status = "disabled"; 337 338 counter { 339 compatible = "st,stm32mp25-timer-counter"; 340 status = "disabled"; 341 }; 342 343 pwm { 344 compatible = "st,stm32mp25-pwm"; 345 #pwm-cells = <3>; 346 status = "disabled"; 347 }; 348 349 timer@2 { 350 compatible = "st,stm32mp25-timer-trigger"; 351 reg = <2>; 352 status = "disabled"; 353 }; 354 }; 355 356 timers4: timer@40020000 { 357 compatible = "st,stm32mp25-timers"; 358 reg = <0x40020000 0x400>; 359 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 360 interrupt-names = "global"; 361 clocks = <&rcc CK_KER_TIM4>; 362 clock-names = "int"; 363 #address-cells = <1>; 364 #size-cells = <0>; 365 access-controllers = <&rifsc 3>; 366 power-domains = <&CLUSTER_PD>; 367 status = "disabled"; 368 369 counter { 370 compatible = "st,stm32mp25-timer-counter"; 371 status = "disabled"; 372 }; 373 374 pwm { 375 compatible = "st,stm32mp25-pwm"; 376 #pwm-cells = <3>; 377 status = "disabled"; 378 }; 379 380 timer@3 { 381 compatible = "st,stm32mp25-timer-trigger"; 382 reg = <3>; 383 status = "disabled"; 384 }; 385 }; 386 387 timers5: timer@40030000 { 388 compatible = "st,stm32mp25-timers"; 389 reg = <0x40030000 0x400>; 390 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 391 interrupt-names = "global"; 392 clocks = <&rcc CK_KER_TIM5>; 393 clock-names = "int"; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 access-controllers = <&rifsc 4>; 397 power-domains = <&CLUSTER_PD>; 398 status = "disabled"; 399 400 counter { 401 compatible = "st,stm32mp25-timer-counter"; 402 status = "disabled"; 403 }; 404 405 pwm { 406 compatible = "st,stm32mp25-pwm"; 407 #pwm-cells = <3>; 408 status = "disabled"; 409 }; 410 411 timer@4 { 412 compatible = "st,stm32mp25-timer-trigger"; 413 reg = <4>; 414 status = "disabled"; 415 }; 416 }; 417 418 timers6: timer@40040000 { 419 compatible = "st,stm32mp25-timers"; 420 reg = <0x40040000 0x400>; 421 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 422 interrupt-names = "global"; 423 clocks = <&rcc CK_KER_TIM6>; 424 clock-names = "int"; 425 #address-cells = <1>; 426 #size-cells = <0>; 427 access-controllers = <&rifsc 5>; 428 power-domains = <&CLUSTER_PD>; 429 status = "disabled"; 430 431 counter { 432 compatible = "st,stm32mp25-timer-counter"; 433 status = "disabled"; 434 }; 435 436 timer@5 { 437 compatible = "st,stm32mp25-timer-trigger"; 438 reg = <5>; 439 status = "disabled"; 440 }; 441 }; 442 443 timers7: timer@40050000 { 444 compatible = "st,stm32mp25-timers"; 445 reg = <0x40050000 0x400>; 446 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 447 interrupt-names = "global"; 448 clocks = <&rcc CK_KER_TIM7>; 449 clock-names = "int"; 450 #address-cells = <1>; 451 #size-cells = <0>; 452 access-controllers = <&rifsc 6>; 453 power-domains = <&CLUSTER_PD>; 454 status = "disabled"; 455 456 counter { 457 compatible = "st,stm32mp25-timer-counter"; 458 status = "disabled"; 459 }; 460 461 timer@6 { 462 compatible = "st,stm32mp25-timer-trigger"; 463 reg = <6>; 464 status = "disabled"; 465 }; 466 }; 467 468 timers12: timer@40060000 { 469 compatible = "st,stm32mp25-timers"; 470 reg = <0x40060000 0x400>; 471 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 472 interrupt-names = "global"; 473 clocks = <&rcc CK_KER_TIM12>; 474 clock-names = "int"; 475 #address-cells = <1>; 476 #size-cells = <0>; 477 access-controllers = <&rifsc 10>; 478 power-domains = <&CLUSTER_PD>; 479 status = "disabled"; 480 481 counter { 482 compatible = "st,stm32mp25-timer-counter"; 483 status = "disabled"; 484 }; 485 486 pwm { 487 compatible = "st,stm32mp25-pwm"; 488 #pwm-cells = <3>; 489 status = "disabled"; 490 }; 491 492 timer@11 { 493 compatible = "st,stm32mp25-timer-trigger"; 494 reg = <11>; 495 status = "disabled"; 496 }; 497 }; 498 499 timers13: timer@40070000 { 500 compatible = "st,stm32mp25-timers"; 501 reg = <0x40070000 0x400>; 502 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 503 interrupt-names = "global"; 504 clocks = <&rcc CK_KER_TIM13>; 505 clock-names = "int"; 506 #address-cells = <1>; 507 #size-cells = <0>; 508 access-controllers = <&rifsc 11>; 509 power-domains = <&CLUSTER_PD>; 510 status = "disabled"; 511 512 counter { 513 compatible = "st,stm32mp25-timer-counter"; 514 status = "disabled"; 515 }; 516 517 pwm { 518 compatible = "st,stm32mp25-pwm"; 519 #pwm-cells = <3>; 520 status = "disabled"; 521 }; 522 523 timer@12 { 524 compatible = "st,stm32mp25-timer-trigger"; 525 reg = <12>; 526 status = "disabled"; 527 }; 528 }; 529 530 timers14: timer@40080000 { 531 compatible = "st,stm32mp25-timers"; 532 reg = <0x40080000 0x400>; 533 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 534 interrupt-names = "global"; 535 clocks = <&rcc CK_KER_TIM14>; 536 clock-names = "int"; 537 #address-cells = <1>; 538 #size-cells = <0>; 539 access-controllers = <&rifsc 12>; 540 power-domains = <&CLUSTER_PD>; 541 status = "disabled"; 542 543 counter { 544 compatible = "st,stm32mp25-timer-counter"; 545 status = "disabled"; 546 }; 547 548 pwm { 549 compatible = "st,stm32mp25-pwm"; 550 #pwm-cells = <3>; 551 status = "disabled"; 552 }; 553 554 timer@13 { 555 compatible = "st,stm32mp25-timer-trigger"; 556 reg = <13>; 557 status = "disabled"; 558 }; 559 }; 560 561 lptimer1: timer@40090000 { 562 compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer"; 563 reg = <0x40090000 0x400>; 564 interrupts-extended = <&exti1 47 IRQ_TYPE_LEVEL_HIGH>; 565 clocks = <&rcc CK_KER_LPTIM1>; 566 clock-names = "mux"; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 access-controllers = <&rifsc 17>; 570 power-domains = <&RET_PD>; 571 wakeup-source; 572 status = "disabled"; 573 574 counter { 575 compatible = "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-counter"; 576 status = "disabled"; 577 }; 578 579 pwm { 580 compatible = "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp"; 581 #pwm-cells = <3>; 582 status = "disabled"; 583 }; 584 585 timer { 586 compatible = "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer"; 587 status = "disabled"; 588 }; 589 590 trigger@0 { 591 compatible = "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trigger"; 592 reg = <0>; 593 status = "disabled"; 594 }; 595 }; 596 597 lptimer2: timer@400a0000 { 598 compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer"; 599 reg = <0x400a0000 0x400>; 600 interrupts-extended = <&exti1 48 IRQ_TYPE_LEVEL_HIGH>; 601 clocks = <&rcc CK_KER_LPTIM2>; 602 clock-names = "mux"; 603 #address-cells = <1>; 604 #size-cells = <0>; 605 access-controllers = <&rifsc 18>; 606 power-domains = <&RET_PD>; 607 wakeup-source; 608 status = "disabled"; 609 610 counter { 611 compatible = "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-counter"; 612 status = "disabled"; 613 }; 614 615 pwm { 616 compatible = "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp"; 617 #pwm-cells = <3>; 618 status = "disabled"; 619 }; 620 621 timer { 622 compatible = "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer"; 623 status = "disabled"; 624 }; 625 626 trigger@1 { 627 compatible = "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trigger"; 628 reg = <1>; 629 status = "disabled"; 630 }; 631 }; 632 633 i2s2: audio-controller@400b0000 { 634 compatible = "st,stm32mp25-i2s"; 635 reg = <0x400b0000 0x400>; 636 #sound-dai-cells = <0>; 637 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 638 clocks = <&rcc CK_BUS_SPI2>, <&rcc CK_KER_SPI2>; 639 clock-names = "pclk", "i2sclk"; 640 resets = <&rcc SPI2_R>; 641 dmas = <&hpdma 51 0x43 0x12>, 642 <&hpdma 52 0x43 0x21>; 643 dma-names = "rx", "tx"; 644 access-controllers = <&rifsc 23>; 645 status = "disabled"; 646 }; 647 648 spi2: spi@400b0000 { 649 #address-cells = <1>; 650 #size-cells = <0>; 651 compatible = "st,stm32mp25-spi"; 652 reg = <0x400b0000 0x400>; 653 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 654 clocks = <&rcc CK_KER_SPI2>; 655 resets = <&rcc SPI2_R>; 656 dmas = <&hpdma 51 0x20 0x3012>, 657 <&hpdma 52 0x20 0x3021>; 658 dma-names = "rx", "tx"; 659 access-controllers = <&rifsc 23>; 660 status = "disabled"; 661 }; 662 663 i2s3: audio-controller@400c0000 { 664 compatible = "st,stm32mp25-i2s"; 665 reg = <0x400c0000 0x400>; 666 #sound-dai-cells = <0>; 667 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 668 clocks = <&rcc CK_BUS_SPI3>, <&rcc CK_KER_SPI3>; 669 clock-names = "pclk", "i2sclk"; 670 resets = <&rcc SPI3_R>; 671 dmas = <&hpdma 53 0x43 0x12>, 672 <&hpdma 54 0x43 0x21>; 673 dma-names = "rx", "tx"; 674 access-controllers = <&rifsc 24>; 675 status = "disabled"; 676 }; 677 678 spi3: spi@400c0000 { 679 #address-cells = <1>; 680 #size-cells = <0>; 681 compatible = "st,stm32mp25-spi"; 682 reg = <0x400c0000 0x400>; 683 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 684 clocks = <&rcc CK_KER_SPI3>; 685 resets = <&rcc SPI3_R>; 686 dmas = <&hpdma 53 0x20 0x3012>, 687 <&hpdma 54 0x20 0x3021>; 688 dma-names = "rx", "tx"; 689 access-controllers = <&rifsc 24>; 690 status = "disabled"; 691 }; 692 693 spdifrx: audio-controller@400d0000 { 694 compatible = "st,stm32h7-spdifrx"; 695 #sound-dai-cells = <0>; 696 reg = <0x400d0000 0x400>; 697 clocks = <&rcc CK_KER_SPDIFRX>; 698 clock-names = "kclk"; 699 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 700 dmas = <&hpdma 71 0x43 0x212>, 701 <&hpdma 72 0x43 0x212>; 702 dma-names = "rx", "rx-ctrl"; 703 access-controllers = <&rifsc 30>; 704 status = "disabled"; 705 }; 706 707 usart2: serial@400e0000 { 708 compatible = "st,stm32h7-uart"; 709 reg = <0x400e0000 0x400>; 710 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 711 clocks = <&rcc CK_KER_USART2>; 712 dmas = <&hpdma 11 0x20 0x10012>, 713 <&hpdma 12 0x20 0x3021>; 714 dma-names = "rx", "tx"; 715 access-controllers = <&rifsc 32>; 716 status = "disabled"; 717 }; 718 719 usart3: serial@400f0000 { 720 compatible = "st,stm32h7-uart"; 721 reg = <0x400f0000 0x400>; 722 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 723 clocks = <&rcc CK_KER_USART3>; 724 dmas = <&hpdma 13 0x20 0x10012>, 725 <&hpdma 14 0x20 0x3021>; 726 dma-names = "rx", "tx"; 727 access-controllers = <&rifsc 33>; 728 status = "disabled"; 729 }; 730 731 uart4: serial@40100000 { 732 compatible = "st,stm32h7-uart"; 733 reg = <0x40100000 0x400>; 734 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 735 clocks = <&rcc CK_KER_UART4>; 736 dmas = <&hpdma 15 0x20 0x10012>, 737 <&hpdma 16 0x20 0x3021>; 738 dma-names = "rx", "tx"; 739 access-controllers = <&rifsc 34>; 740 status = "disabled"; 741 }; 742 743 uart5: serial@40110000 { 744 compatible = "st,stm32h7-uart"; 745 reg = <0x40110000 0x400>; 746 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 747 clocks = <&rcc CK_KER_UART5>; 748 dmas = <&hpdma 17 0x20 0x10012>, 749 <&hpdma 18 0x20 0x3021>; 750 dma-names = "rx", "tx"; 751 access-controllers = <&rifsc 35>; 752 status = "disabled"; 753 }; 754 755 i2c1: i2c@40120000 { 756 compatible = "st,stm32mp25-i2c"; 757 reg = <0x40120000 0x400>; 758 interrupt-names = "event"; 759 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 760 clocks = <&rcc CK_KER_I2C1>; 761 resets = <&rcc I2C1_R>; 762 #address-cells = <1>; 763 #size-cells = <0>; 764 dmas = <&hpdma 27 0x20 0x3012>, 765 <&hpdma 28 0x20 0x3021>; 766 dma-names = "rx", "tx"; 767 access-controllers = <&rifsc 41>; 768 status = "disabled"; 769 }; 770 771 i2c2: i2c@40130000 { 772 compatible = "st,stm32mp25-i2c"; 773 reg = <0x40130000 0x400>; 774 interrupt-names = "event"; 775 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 776 clocks = <&rcc CK_KER_I2C2>; 777 resets = <&rcc I2C2_R>; 778 #address-cells = <1>; 779 #size-cells = <0>; 780 dmas = <&hpdma 30 0x20 0x3012>, 781 <&hpdma 31 0x20 0x3021>; 782 dma-names = "rx", "tx"; 783 access-controllers = <&rifsc 42>; 784 status = "disabled"; 785 }; 786 787 i2c3: i2c@40140000 { 788 compatible = "st,stm32mp25-i2c"; 789 reg = <0x40140000 0x400>; 790 interrupt-names = "event"; 791 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&rcc CK_KER_I2C3>; 793 resets = <&rcc I2C3_R>; 794 #address-cells = <1>; 795 #size-cells = <0>; 796 dmas = <&hpdma 33 0x20 0x3012>, 797 <&hpdma 34 0x20 0x3021>; 798 dma-names = "rx", "tx"; 799 access-controllers = <&rifsc 43>; 800 status = "disabled"; 801 }; 802 803 i2c4: i2c@40150000 { 804 compatible = "st,stm32mp25-i2c"; 805 reg = <0x40150000 0x400>; 806 interrupt-names = "event"; 807 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 808 clocks = <&rcc CK_KER_I2C4>; 809 resets = <&rcc I2C4_R>; 810 #address-cells = <1>; 811 #size-cells = <0>; 812 dmas = <&hpdma 36 0x20 0x3012>, 813 <&hpdma 37 0x20 0x3021>; 814 dma-names = "rx", "tx"; 815 access-controllers = <&rifsc 44>; 816 status = "disabled"; 817 }; 818 819 i2c5: i2c@40160000 { 820 compatible = "st,stm32mp25-i2c"; 821 reg = <0x40160000 0x400>; 822 interrupt-names = "event"; 823 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 824 clocks = <&rcc CK_KER_I2C5>; 825 resets = <&rcc I2C5_R>; 826 #address-cells = <1>; 827 #size-cells = <0>; 828 dmas = <&hpdma 39 0x20 0x3012>, 829 <&hpdma 40 0x20 0x3021>; 830 dma-names = "rx", "tx"; 831 access-controllers = <&rifsc 45>; 832 status = "disabled"; 833 }; 834 835 i2c6: i2c@40170000 { 836 compatible = "st,stm32mp25-i2c"; 837 reg = <0x40170000 0x400>; 838 interrupt-names = "event"; 839 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 840 clocks = <&rcc CK_KER_I2C6>; 841 resets = <&rcc I2C6_R>; 842 #address-cells = <1>; 843 #size-cells = <0>; 844 dmas = <&hpdma 42 0x20 0x3012>, 845 <&hpdma 43 0x20 0x3021>; 846 dma-names = "rx", "tx"; 847 access-controllers = <&rifsc 46>; 848 status = "disabled"; 849 }; 850 851 i2c7: i2c@40180000 { 852 compatible = "st,stm32mp25-i2c"; 853 reg = <0x40180000 0x400>; 854 interrupt-names = "event"; 855 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; 856 clocks = <&rcc CK_KER_I2C7>; 857 resets = <&rcc I2C7_R>; 858 #address-cells = <1>; 859 #size-cells = <0>; 860 dmas = <&hpdma 45 0x20 0x3012>, 861 <&hpdma 46 0x20 0x3021>; 862 dma-names = "rx", "tx"; 863 access-controllers = <&rifsc 47>; 864 status = "disabled"; 865 }; 866 867 timers10: timer@401c0000 { 868 compatible = "st,stm32mp25-timers"; 869 reg = <0x401c0000 0x400>; 870 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 871 interrupt-names = "global"; 872 clocks = <&rcc CK_KER_TIM10>; 873 clock-names = "int"; 874 #address-cells = <1>; 875 #size-cells = <0>; 876 access-controllers = <&rifsc 8>; 877 power-domains = <&CLUSTER_PD>; 878 status = "disabled"; 879 880 counter { 881 compatible = "st,stm32mp25-timer-counter"; 882 status = "disabled"; 883 }; 884 885 pwm { 886 compatible = "st,stm32mp25-pwm"; 887 #pwm-cells = <3>; 888 status = "disabled"; 889 }; 890 891 timer@9 { 892 compatible = "st,stm32mp25-timer-trigger"; 893 reg = <9>; 894 status = "disabled"; 895 }; 896 }; 897 898 timers11: timer@401d0000 { 899 compatible = "st,stm32mp25-timers"; 900 reg = <0x401d0000 0x400>; 901 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 902 interrupt-names = "global"; 903 clocks = <&rcc CK_KER_TIM11>; 904 clock-names = "int"; 905 #address-cells = <1>; 906 #size-cells = <0>; 907 access-controllers = <&rifsc 9>; 908 power-domains = <&CLUSTER_PD>; 909 status = "disabled"; 910 911 counter { 912 compatible = "st,stm32mp25-timer-counter"; 913 status = "disabled"; 914 }; 915 916 pwm { 917 compatible = "st,stm32mp25-pwm"; 918 #pwm-cells = <3>; 919 status = "disabled"; 920 }; 921 922 timer@10 { 923 compatible = "st,stm32mp25-timer-trigger"; 924 reg = <10>; 925 status = "disabled"; 926 }; 927 }; 928 929 timers1: timer@40200000 { 930 compatible = "st,stm32mp25-timers"; 931 reg = <0x40200000 0x400>; 932 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 936 interrupt-names = "brk", "up", "trg-com", "cc"; 937 clocks = <&rcc CK_KER_TIM1>; 938 clock-names = "int"; 939 #address-cells = <1>; 940 #size-cells = <0>; 941 access-controllers = <&rifsc 0>; 942 power-domains = <&CLUSTER_PD>; 943 status = "disabled"; 944 945 counter { 946 compatible = "st,stm32mp25-timer-counter"; 947 status = "disabled"; 948 }; 949 950 pwm { 951 compatible = "st,stm32mp25-pwm"; 952 #pwm-cells = <3>; 953 status = "disabled"; 954 }; 955 956 timer@0 { 957 compatible = "st,stm32mp25-timer-trigger"; 958 reg = <0>; 959 status = "disabled"; 960 }; 961 }; 962 963 timers8: timer@40210000 { 964 compatible = "st,stm32mp25-timers"; 965 reg = <0x40210000 0x400>; 966 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 970 interrupt-names = "brk", "up", "trg-com", "cc"; 971 clocks = <&rcc CK_KER_TIM8>; 972 clock-names = "int"; 973 #address-cells = <1>; 974 #size-cells = <0>; 975 access-controllers = <&rifsc 7>; 976 power-domains = <&CLUSTER_PD>; 977 status = "disabled"; 978 979 counter { 980 compatible = "st,stm32mp25-timer-counter"; 981 status = "disabled"; 982 }; 983 984 pwm { 985 compatible = "st,stm32mp25-pwm"; 986 #pwm-cells = <3>; 987 status = "disabled"; 988 }; 989 990 timer@7 { 991 compatible = "st,stm32mp25-timer-trigger"; 992 reg = <7>; 993 status = "disabled"; 994 }; 995 }; 996 997 usart6: serial@40220000 { 998 compatible = "st,stm32h7-uart"; 999 reg = <0x40220000 0x400>; 1000 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1001 clocks = <&rcc CK_KER_USART6>; 1002 dmas = <&hpdma 19 0x20 0x10012>, 1003 <&hpdma 20 0x20 0x3021>; 1004 dma-names = "rx", "tx"; 1005 access-controllers = <&rifsc 36>; 1006 status = "disabled"; 1007 }; 1008 1009 i2s1: audio-controller@40230000 { 1010 compatible = "st,stm32mp25-i2s"; 1011 reg = <0x40230000 0x400>; 1012 #sound-dai-cells = <0>; 1013 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1014 clocks = <&rcc CK_BUS_SPI1>, <&rcc CK_KER_SPI1>; 1015 clock-names = "pclk", "i2sclk"; 1016 resets = <&rcc SPI1_R>; 1017 dmas = <&hpdma 49 0x43 0x12>, 1018 <&hpdma 50 0x43 0x21>; 1019 dma-names = "rx", "tx"; 1020 access-controllers = <&rifsc 22>; 1021 status = "disabled"; 1022 }; 1023 1024 spi1: spi@40230000 { 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 compatible = "st,stm32mp25-spi"; 1028 reg = <0x40230000 0x400>; 1029 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1030 clocks = <&rcc CK_KER_SPI1>; 1031 resets = <&rcc SPI1_R>; 1032 dmas = <&hpdma 49 0x20 0x3012>, 1033 <&hpdma 50 0x20 0x3021>; 1034 dma-names = "rx", "tx"; 1035 access-controllers = <&rifsc 22>; 1036 status = "disabled"; 1037 }; 1038 1039 spi4: spi@40240000 { 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 compatible = "st,stm32mp25-spi"; 1043 reg = <0x40240000 0x400>; 1044 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1045 clocks = <&rcc CK_KER_SPI4>; 1046 resets = <&rcc SPI4_R>; 1047 dmas = <&hpdma 55 0x20 0x3012>, 1048 <&hpdma 56 0x20 0x3021>; 1049 dma-names = "rx", "tx"; 1050 access-controllers = <&rifsc 25>; 1051 status = "disabled"; 1052 }; 1053 1054 timers15: timer@40250000 { 1055 compatible = "st,stm32mp25-timers"; 1056 reg = <0x40250000 0x400>; 1057 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 1058 interrupt-names = "global"; 1059 clocks = <&rcc CK_KER_TIM15>; 1060 clock-names = "int"; 1061 #address-cells = <1>; 1062 #size-cells = <0>; 1063 access-controllers = <&rifsc 13>; 1064 power-domains = <&CLUSTER_PD>; 1065 status = "disabled"; 1066 1067 counter { 1068 compatible = "st,stm32mp25-timer-counter"; 1069 status = "disabled"; 1070 }; 1071 1072 pwm { 1073 compatible = "st,stm32mp25-pwm"; 1074 #pwm-cells = <3>; 1075 status = "disabled"; 1076 }; 1077 1078 timer@14 { 1079 compatible = "st,stm32mp25-timer-trigger"; 1080 reg = <14>; 1081 status = "disabled"; 1082 }; 1083 }; 1084 1085 timers16: timer@40260000 { 1086 compatible = "st,stm32mp25-timers"; 1087 reg = <0x40260000 0x400>; 1088 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 1089 interrupt-names = "global"; 1090 clocks = <&rcc CK_KER_TIM16>; 1091 clock-names = "int"; 1092 #address-cells = <1>; 1093 #size-cells = <0>; 1094 access-controllers = <&rifsc 14>; 1095 power-domains = <&CLUSTER_PD>; 1096 status = "disabled"; 1097 1098 counter { 1099 compatible = "st,stm32mp25-timer-counter"; 1100 status = "disabled"; 1101 }; 1102 1103 pwm { 1104 compatible = "st,stm32mp25-pwm"; 1105 #pwm-cells = <3>; 1106 status = "disabled"; 1107 }; 1108 1109 timer@15 { 1110 compatible = "st,stm32mp25-timer-trigger"; 1111 reg = <15>; 1112 status = "disabled"; 1113 }; 1114 }; 1115 1116 timers17: timer@40270000 { 1117 compatible = "st,stm32mp25-timers"; 1118 reg = <0x40270000 0x400>; 1119 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 1120 interrupt-names = "global"; 1121 clocks = <&rcc CK_KER_TIM17>; 1122 clock-names = "int"; 1123 #address-cells = <1>; 1124 #size-cells = <0>; 1125 access-controllers = <&rifsc 15>; 1126 power-domains = <&CLUSTER_PD>; 1127 status = "disabled"; 1128 1129 counter { 1130 compatible = "st,stm32mp25-timer-counter"; 1131 status = "disabled"; 1132 }; 1133 1134 pwm { 1135 compatible = "st,stm32mp25-pwm"; 1136 #pwm-cells = <3>; 1137 status = "disabled"; 1138 }; 1139 1140 timer@16 { 1141 compatible = "st,stm32mp25-timer-trigger"; 1142 reg = <16>; 1143 status = "disabled"; 1144 }; 1145 }; 1146 1147 spi5: spi@40280000 { 1148 #address-cells = <1>; 1149 #size-cells = <0>; 1150 compatible = "st,stm32mp25-spi"; 1151 reg = <0x40280000 0x400>; 1152 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1153 clocks = <&rcc CK_KER_SPI5>; 1154 resets = <&rcc SPI5_R>; 1155 dmas = <&hpdma 57 0x20 0x3012>, 1156 <&hpdma 58 0x20 0x3021>; 1157 dma-names = "rx", "tx"; 1158 access-controllers = <&rifsc 26>; 1159 status = "disabled"; 1160 }; 1161 1162 sai1: sai@40290000 { 1163 compatible = "st,stm32mp25-sai"; 1164 reg = <0x40290000 0x4>, <0x4029a3f0 0x10>; 1165 ranges = <0 0x40290000 0x400>; 1166 #address-cells = <1>; 1167 #size-cells = <1>; 1168 clocks = <&rcc CK_BUS_SAI1>; 1169 clock-names = "pclk"; 1170 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1171 resets = <&rcc SAI1_R>; 1172 access-controllers = <&rifsc 49>; 1173 status = "disabled"; 1174 1175 sai1a: audio-controller@40290004 { 1176 compatible = "st,stm32-sai-sub-a"; 1177 reg = <0x4 0x20>; 1178 #sound-dai-cells = <0>; 1179 clocks = <&rcc CK_KER_SAI1>; 1180 clock-names = "sai_ck"; 1181 dmas = <&hpdma 73 0x43 0x21>; 1182 status = "disabled"; 1183 }; 1184 1185 sai1b: audio-controller@40290024 { 1186 compatible = "st,stm32-sai-sub-b"; 1187 reg = <0x24 0x20>; 1188 #sound-dai-cells = <0>; 1189 clocks = <&rcc CK_KER_SAI1>; 1190 clock-names = "sai_ck"; 1191 dmas = <&hpdma 74 0x43 0x12>; 1192 status = "disabled"; 1193 }; 1194 }; 1195 1196 sai2: sai@402a0000 { 1197 compatible = "st,stm32mp25-sai"; 1198 reg = <0x402a0000 0x4>, <0x402aa3f0 0x10>; 1199 ranges = <0 0x402a0000 0x400>; 1200 #address-cells = <1>; 1201 #size-cells = <1>; 1202 clocks = <&rcc CK_BUS_SAI2>; 1203 clock-names = "pclk"; 1204 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1205 resets = <&rcc SAI2_R>; 1206 access-controllers = <&rifsc 50>; 1207 status = "disabled"; 1208 1209 sai2a: audio-controller@402a0004 { 1210 compatible = "st,stm32-sai-sub-a"; 1211 reg = <0x4 0x20>; 1212 #sound-dai-cells = <0>; 1213 clocks = <&rcc CK_KER_SAI2>; 1214 clock-names = "sai_ck"; 1215 dmas = <&hpdma 75 0x43 0x21>; 1216 status = "disabled"; 1217 }; 1218 1219 sai2b: audio-controller@402a0024 { 1220 compatible = "st,stm32-sai-sub-b"; 1221 reg = <0x24 0x20>; 1222 #sound-dai-cells = <0>; 1223 clocks = <&rcc CK_KER_SAI2>; 1224 clock-names = "sai_ck"; 1225 dmas = <&hpdma 76 0x43 0x12>; 1226 status = "disabled"; 1227 }; 1228 }; 1229 1230 sai3: sai@402b0000 { 1231 compatible = "st,stm32mp25-sai"; 1232 reg = <0x402b0000 0x4>, <0x402ba3f0 0x10>; 1233 ranges = <0 0x402b0000 0x400>; 1234 #address-cells = <1>; 1235 #size-cells = <1>; 1236 clocks = <&rcc CK_BUS_SAI3>; 1237 clock-names = "pclk"; 1238 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 1239 resets = <&rcc SAI3_R>; 1240 access-controllers = <&rifsc 51>; 1241 status = "disabled"; 1242 1243 sai3a: audio-controller@402b0004 { 1244 compatible = "st,stm32-sai-sub-a"; 1245 reg = <0x4 0x20>; 1246 #sound-dai-cells = <0>; 1247 clocks = <&rcc CK_KER_SAI3>; 1248 clock-names = "sai_ck"; 1249 dmas = <&hpdma 77 0x43 0x21>; 1250 status = "disabled"; 1251 }; 1252 1253 sai3b: audio-controller@502b0024 { 1254 compatible = "st,stm32-sai-sub-b"; 1255 reg = <0x24 0x20>; 1256 #sound-dai-cells = <0>; 1257 clocks = <&rcc CK_KER_SAI3>; 1258 clock-names = "sai_ck"; 1259 dmas = <&hpdma 78 0x43 0x12>; 1260 status = "disabled"; 1261 }; 1262 }; 1263 1264 uart9: serial@402c0000 { 1265 compatible = "st,stm32h7-uart"; 1266 reg = <0x402c0000 0x400>; 1267 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1268 clocks = <&rcc CK_KER_UART9>; 1269 dmas = <&hpdma 25 0x20 0x10012>, 1270 <&hpdma 26 0x20 0x3021>; 1271 dma-names = "rx", "tx"; 1272 access-controllers = <&rifsc 39>; 1273 status = "disabled"; 1274 }; 1275 1276 timers20: timer@40320000 { 1277 compatible = "st,stm32mp25-timers"; 1278 reg = <0x40320000 0x400>; 1279 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1280 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1281 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1282 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1283 interrupt-names = "brk", "up", "trg-com", "cc"; 1284 clocks = <&rcc CK_KER_TIM20>; 1285 clock-names = "int"; 1286 #address-cells = <1>; 1287 #size-cells = <0>; 1288 access-controllers = <&rifsc 16>; 1289 power-domains = <&CLUSTER_PD>; 1290 status = "disabled"; 1291 1292 counter { 1293 compatible = "st,stm32mp25-timer-counter"; 1294 status = "disabled"; 1295 }; 1296 1297 pwm { 1298 compatible = "st,stm32mp25-pwm"; 1299 #pwm-cells = <3>; 1300 status = "disabled"; 1301 }; 1302 1303 timer@19 { 1304 compatible = "st,stm32mp25-timer-trigger"; 1305 reg = <19>; 1306 status = "disabled"; 1307 }; 1308 }; 1309 1310 usart1: serial@40330000 { 1311 compatible = "st,stm32h7-uart"; 1312 reg = <0x40330000 0x400>; 1313 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1314 clocks = <&rcc CK_KER_USART1>; 1315 dmas = <&hpdma 9 0x20 0x10012>, 1316 <&hpdma 10 0x20 0x3021>; 1317 dma-names = "rx", "tx"; 1318 access-controllers = <&rifsc 31>; 1319 status = "disabled"; 1320 }; 1321 1322 sai4: sai@40340000 { 1323 compatible = "st,stm32mp25-sai"; 1324 reg = <0x40340000 0x4>, <0x4034a3f0 0x10>; 1325 ranges = <0 0x40340000 0x400>; 1326 #address-cells = <1>; 1327 #size-cells = <1>; 1328 clocks = <&rcc CK_BUS_SAI4>; 1329 clock-names = "pclk"; 1330 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1331 resets = <&rcc SAI4_R>; 1332 access-controllers = <&rifsc 52>; 1333 status = "disabled"; 1334 1335 sai4a: audio-controller@40340004 { 1336 compatible = "st,stm32-sai-sub-a"; 1337 reg = <0x4 0x20>; 1338 #sound-dai-cells = <0>; 1339 clocks = <&rcc CK_KER_SAI4>; 1340 clock-names = "sai_ck"; 1341 dmas = <&hpdma 79 0x63 0x21>; 1342 status = "disabled"; 1343 }; 1344 1345 sai4b: audio-controller@40340024 { 1346 compatible = "st,stm32-sai-sub-b"; 1347 reg = <0x24 0x20>; 1348 #sound-dai-cells = <0>; 1349 clocks = <&rcc CK_KER_SAI4>; 1350 clock-names = "sai_ck"; 1351 dmas = <&hpdma 80 0x43 0x12>; 1352 status = "disabled"; 1353 }; 1354 }; 1355 1356 spi6: spi@40350000 { 1357 #address-cells = <1>; 1358 #size-cells = <0>; 1359 compatible = "st,stm32mp25-spi"; 1360 reg = <0x40350000 0x400>; 1361 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1362 clocks = <&rcc CK_KER_SPI6>; 1363 resets = <&rcc SPI6_R>; 1364 dmas = <&hpdma 59 0x20 0x3012>, 1365 <&hpdma 60 0x20 0x3021>; 1366 dma-names = "rx", "tx"; 1367 access-controllers = <&rifsc 27>; 1368 status = "disabled"; 1369 }; 1370 1371 spi7: spi@40360000 { 1372 #address-cells = <1>; 1373 #size-cells = <0>; 1374 compatible = "st,stm32mp25-spi"; 1375 reg = <0x40360000 0x400>; 1376 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1377 clocks = <&rcc CK_KER_SPI7>; 1378 resets = <&rcc SPI7_R>; 1379 dmas = <&hpdma 61 0x20 0x3012>, 1380 <&hpdma 62 0x20 0x3021>; 1381 dma-names = "rx", "tx"; 1382 access-controllers = <&rifsc 28>; 1383 status = "disabled"; 1384 }; 1385 1386 uart7: serial@40370000 { 1387 compatible = "st,stm32h7-uart"; 1388 reg = <0x40370000 0x400>; 1389 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1390 clocks = <&rcc CK_KER_UART7>; 1391 dmas = <&hpdma 21 0x20 0x10012>, 1392 <&hpdma 22 0x20 0x3021>; 1393 dma-names = "rx", "tx"; 1394 access-controllers = <&rifsc 37>; 1395 status = "disabled"; 1396 }; 1397 1398 uart8: serial@40380000 { 1399 compatible = "st,stm32h7-uart"; 1400 reg = <0x40380000 0x400>; 1401 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 1402 clocks = <&rcc CK_KER_UART8>; 1403 dmas = <&hpdma 23 0x20 0x10012>, 1404 <&hpdma 24 0x20 0x3021>; 1405 dma-names = "rx", "tx"; 1406 access-controllers = <&rifsc 38>; 1407 status = "disabled"; 1408 }; 1409 1410 rng: rng@42020000 { 1411 compatible = "st,stm32mp25-rng"; 1412 reg = <0x42020000 0x400>; 1413 clocks = <&clk_rcbsec>, <&rcc CK_BUS_RNG>; 1414 clock-names = "core", "bus"; 1415 resets = <&rcc RNG_R>; 1416 access-controllers = <&rifsc 92>; 1417 status = "disabled"; 1418 }; 1419 1420 spi8: spi@46020000 { 1421 #address-cells = <1>; 1422 #size-cells = <0>; 1423 compatible = "st,stm32mp25-spi"; 1424 reg = <0x46020000 0x400>; 1425 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1426 clocks = <&rcc CK_KER_SPI8>; 1427 resets = <&rcc SPI8_R>; 1428 dmas = <&hpdma 171 0x20 0x3012>, 1429 <&hpdma 172 0x20 0x3021>; 1430 dma-names = "rx", "tx"; 1431 access-controllers = <&rifsc 29>; 1432 status = "disabled"; 1433 }; 1434 1435 i2c8: i2c@46040000 { 1436 compatible = "st,stm32mp25-i2c"; 1437 reg = <0x46040000 0x400>; 1438 interrupt-names = "event"; 1439 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 1440 clocks = <&rcc CK_KER_I2C8>; 1441 resets = <&rcc I2C8_R>; 1442 #address-cells = <1>; 1443 #size-cells = <0>; 1444 dmas = <&hpdma 168 0x20 0x3012>, 1445 <&hpdma 169 0x20 0x3021>; 1446 dma-names = "rx", "tx"; 1447 access-controllers = <&rifsc 48>; 1448 status = "disabled"; 1449 }; 1450 1451 lptimer3: timer@46050000 { 1452 compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer"; 1453 reg = <0x46050000 0x400>; 1454 interrupts-extended = <&exti2 29 IRQ_TYPE_LEVEL_HIGH>; 1455 clocks = <&rcc CK_KER_LPTIM3>; 1456 clock-names = "mux"; 1457 #address-cells = <1>; 1458 #size-cells = <0>; 1459 access-controllers = <&rifsc 19>; 1460 wakeup-source; 1461 status = "disabled"; 1462 1463 counter { 1464 compatible = "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-counter"; 1465 status = "disabled"; 1466 }; 1467 1468 pwm { 1469 compatible = "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp"; 1470 #pwm-cells = <3>; 1471 status = "disabled"; 1472 }; 1473 1474 timer { 1475 compatible = "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer"; 1476 status = "disabled"; 1477 }; 1478 1479 trigger@2 { 1480 compatible = "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trigger"; 1481 reg = <2>; 1482 status = "disabled"; 1483 }; 1484 }; 1485 1486 lptimer4: timer@46060000 { 1487 compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer"; 1488 reg = <0x46060000 0x400>; 1489 interrupts-extended = <&exti2 30 IRQ_TYPE_LEVEL_HIGH>; 1490 clocks = <&rcc CK_KER_LPTIM4>; 1491 clock-names = "mux"; 1492 #address-cells = <1>; 1493 #size-cells = <0>; 1494 access-controllers = <&rifsc 20>; 1495 wakeup-source; 1496 status = "disabled"; 1497 1498 counter { 1499 compatible = "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-counter"; 1500 status = "disabled"; 1501 }; 1502 1503 pwm { 1504 compatible = "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp"; 1505 #pwm-cells = <3>; 1506 status = "disabled"; 1507 }; 1508 1509 timer { 1510 compatible = "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer"; 1511 status = "disabled"; 1512 }; 1513 1514 trigger@3 { 1515 compatible = "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trigger"; 1516 reg = <3>; 1517 status = "disabled"; 1518 }; 1519 }; 1520 1521 lptimer5: timer@46070000 { 1522 compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer"; 1523 reg = <0x46070000 0x400>; 1524 interrupts-extended = <&exti2 31 IRQ_TYPE_LEVEL_HIGH>; 1525 clocks = <&rcc CK_KER_LPTIM5>; 1526 clock-names = "mux"; 1527 #address-cells = <1>; 1528 #size-cells = <0>; 1529 access-controllers = <&rifsc 21>; 1530 wakeup-source; 1531 status = "disabled"; 1532 1533 counter { 1534 compatible = "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-counter"; 1535 status = "disabled"; 1536 }; 1537 1538 pwm { 1539 compatible = "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp"; 1540 #pwm-cells = <3>; 1541 status = "disabled"; 1542 }; 1543 1544 timer { 1545 compatible = "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer"; 1546 status = "disabled"; 1547 }; 1548 1549 trigger@4 { 1550 compatible = "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trigger"; 1551 reg = <4>; 1552 status = "disabled"; 1553 }; 1554 }; 1555 1556 csi: csi@48020000 { 1557 compatible = "st,stm32mp25-csi"; 1558 reg = <0x48020000 0x2000>; 1559 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 1560 resets = <&rcc CSI_R>; 1561 clocks = <&rcc CK_KER_CSI>, <&rcc CK_KER_CSITXESC>, 1562 <&rcc CK_KER_CSIPHY>; 1563 clock-names = "pclk", "txesc", "csi2phy"; 1564 access-controllers = <&rifsc 86>; 1565 status = "disabled"; 1566 }; 1567 1568 dcmipp: dcmipp@48030000 { 1569 compatible = "st,stm32mp25-dcmipp"; 1570 reg = <0x48030000 0x1000>; 1571 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 1572 resets = <&rcc DCMIPP_R>; 1573 clocks = <&rcc CK_BUS_DCMIPP>, <&rcc CK_KER_CSI>; 1574 clock-names = "kclk", "mclk"; 1575 access-controllers = <&rifsc 87>; 1576 status = "disabled"; 1577 }; 1578 1579 combophy: phy@480c0000 { 1580 compatible = "st,stm32mp25-combophy"; 1581 reg = <0x480c0000 0x1000>; 1582 #phy-cells = <1>; 1583 clocks = <&rcc CK_BUS_USB3PCIEPHY>, <&rcc CK_KER_USB3PCIEPHY>; 1584 clock-names = "apb", "ker"; 1585 resets = <&rcc USB3PCIEPHY_R>; 1586 reset-names = "phy"; 1587 access-controllers = <&rifsc 67>; 1588 power-domains = <&CLUSTER_PD>; 1589 wakeup-source; 1590 interrupts-extended = <&exti1 45 IRQ_TYPE_EDGE_FALLING>; 1591 status = "disabled"; 1592 }; 1593 1594 sdmmc1: mmc@48220000 { 1595 compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; 1596 arm,primecell-periphid = <0x00353180>; 1597 reg = <0x48220000 0x400>, <0x44230400 0x8>; 1598 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1599 clocks = <&rcc CK_KER_SDMMC1 >; 1600 clock-names = "apb_pclk"; 1601 resets = <&rcc SDMMC1_R>; 1602 cap-sd-highspeed; 1603 cap-mmc-highspeed; 1604 max-frequency = <120000000>; 1605 access-controllers = <&rifsc 76>; 1606 status = "disabled"; 1607 }; 1608 1609 ethernet1: ethernet@482c0000 { 1610 compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20"; 1611 reg = <0x482c0000 0x4000>; 1612 reg-names = "stmmaceth"; 1613 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 1614 interrupt-names = "macirq"; 1615 clock-names = "stmmaceth", 1616 "mac-clk-tx", 1617 "mac-clk-rx", 1618 "ptp_ref", 1619 "ethstp", 1620 "eth-ck"; 1621 clocks = <&rcc CK_ETH1_MAC>, 1622 <&rcc CK_ETH1_TX>, 1623 <&rcc CK_ETH1_RX>, 1624 <&rcc CK_KER_ETH1PTP>, 1625 <&rcc CK_ETH1_STP>, 1626 <&rcc CK_KER_ETH1>; 1627 snps,axi-config = <&stmmac_axi_config_1>; 1628 snps,mixed-burst; 1629 snps,mtl-rx-config = <&mtl_rx_setup_1>; 1630 snps,mtl-tx-config = <&mtl_tx_setup_1>; 1631 snps,pbl = <2>; 1632 snps,tso; 1633 st,syscon = <&syscfg 0x3000>; 1634 access-controllers = <&rifsc 60>; 1635 status = "disabled"; 1636 1637 mtl_rx_setup_1: rx-queues-config { 1638 snps,rx-queues-to-use = <2>; 1639 queue0 {}; 1640 queue1 {}; 1641 }; 1642 1643 mtl_tx_setup_1: tx-queues-config { 1644 snps,tx-queues-to-use = <4>; 1645 queue0 {}; 1646 queue1 {}; 1647 queue2 {}; 1648 queue3 {}; 1649 }; 1650 1651 stmmac_axi_config_1: stmmac-axi-config { 1652 snps,blen = <0 0 0 0 16 8 4>; 1653 snps,rd_osr_lmt = <0x7>; 1654 snps,wr_osr_lmt = <0x7>; 1655 }; 1656 }; 1657 }; 1658 1659 bsec: efuse@44000000 { 1660 compatible = "st,stm32mp25-bsec"; 1661 reg = <0x44000000 0x1000>; 1662 #address-cells = <1>; 1663 #size-cells = <1>; 1664 1665 part_number_otp@24 { 1666 reg = <0x24 0x4>; 1667 }; 1668 1669 package_otp@1e8 { 1670 reg = <0x1e8 0x1>; 1671 bits = <0 3>; 1672 }; 1673 }; 1674 1675 rcc: clock-controller@44200000 { 1676 compatible = "st,stm32mp25-rcc"; 1677 reg = <0x44200000 0x10000>; 1678 #clock-cells = <1>; 1679 #reset-cells = <1>; 1680 clocks = <&scmi_clk CK_SCMI_HSE>, 1681 <&scmi_clk CK_SCMI_HSI>, 1682 <&scmi_clk CK_SCMI_MSI>, 1683 <&scmi_clk CK_SCMI_LSE>, 1684 <&scmi_clk CK_SCMI_LSI>, 1685 <&scmi_clk CK_SCMI_HSE_DIV2>, 1686 <&scmi_clk CK_SCMI_ICN_HS_MCU>, 1687 <&scmi_clk CK_SCMI_ICN_LS_MCU>, 1688 <&scmi_clk CK_SCMI_ICN_SDMMC>, 1689 <&scmi_clk CK_SCMI_ICN_DDR>, 1690 <&scmi_clk CK_SCMI_ICN_DISPLAY>, 1691 <&scmi_clk CK_SCMI_ICN_HSL>, 1692 <&scmi_clk CK_SCMI_ICN_NIC>, 1693 <&scmi_clk CK_SCMI_ICN_VID>, 1694 <&scmi_clk CK_SCMI_FLEXGEN_07>, 1695 <&scmi_clk CK_SCMI_FLEXGEN_08>, 1696 <&scmi_clk CK_SCMI_FLEXGEN_09>, 1697 <&scmi_clk CK_SCMI_FLEXGEN_10>, 1698 <&scmi_clk CK_SCMI_FLEXGEN_11>, 1699 <&scmi_clk CK_SCMI_FLEXGEN_12>, 1700 <&scmi_clk CK_SCMI_FLEXGEN_13>, 1701 <&scmi_clk CK_SCMI_FLEXGEN_14>, 1702 <&scmi_clk CK_SCMI_FLEXGEN_15>, 1703 <&scmi_clk CK_SCMI_FLEXGEN_16>, 1704 <&scmi_clk CK_SCMI_FLEXGEN_17>, 1705 <&scmi_clk CK_SCMI_FLEXGEN_18>, 1706 <&scmi_clk CK_SCMI_FLEXGEN_19>, 1707 <&scmi_clk CK_SCMI_FLEXGEN_20>, 1708 <&scmi_clk CK_SCMI_FLEXGEN_21>, 1709 <&scmi_clk CK_SCMI_FLEXGEN_22>, 1710 <&scmi_clk CK_SCMI_FLEXGEN_23>, 1711 <&scmi_clk CK_SCMI_FLEXGEN_24>, 1712 <&scmi_clk CK_SCMI_FLEXGEN_25>, 1713 <&scmi_clk CK_SCMI_FLEXGEN_26>, 1714 <&scmi_clk CK_SCMI_FLEXGEN_27>, 1715 <&scmi_clk CK_SCMI_FLEXGEN_28>, 1716 <&scmi_clk CK_SCMI_FLEXGEN_29>, 1717 <&scmi_clk CK_SCMI_FLEXGEN_30>, 1718 <&scmi_clk CK_SCMI_FLEXGEN_31>, 1719 <&scmi_clk CK_SCMI_FLEXGEN_32>, 1720 <&scmi_clk CK_SCMI_FLEXGEN_33>, 1721 <&scmi_clk CK_SCMI_FLEXGEN_34>, 1722 <&scmi_clk CK_SCMI_FLEXGEN_35>, 1723 <&scmi_clk CK_SCMI_FLEXGEN_36>, 1724 <&scmi_clk CK_SCMI_FLEXGEN_37>, 1725 <&scmi_clk CK_SCMI_FLEXGEN_38>, 1726 <&scmi_clk CK_SCMI_FLEXGEN_39>, 1727 <&scmi_clk CK_SCMI_FLEXGEN_40>, 1728 <&scmi_clk CK_SCMI_FLEXGEN_41>, 1729 <&scmi_clk CK_SCMI_FLEXGEN_42>, 1730 <&scmi_clk CK_SCMI_FLEXGEN_43>, 1731 <&scmi_clk CK_SCMI_FLEXGEN_44>, 1732 <&scmi_clk CK_SCMI_FLEXGEN_45>, 1733 <&scmi_clk CK_SCMI_FLEXGEN_46>, 1734 <&scmi_clk CK_SCMI_FLEXGEN_47>, 1735 <&scmi_clk CK_SCMI_FLEXGEN_48>, 1736 <&scmi_clk CK_SCMI_FLEXGEN_49>, 1737 <&scmi_clk CK_SCMI_FLEXGEN_50>, 1738 <&scmi_clk CK_SCMI_FLEXGEN_51>, 1739 <&scmi_clk CK_SCMI_FLEXGEN_52>, 1740 <&scmi_clk CK_SCMI_FLEXGEN_53>, 1741 <&scmi_clk CK_SCMI_FLEXGEN_54>, 1742 <&scmi_clk CK_SCMI_FLEXGEN_55>, 1743 <&scmi_clk CK_SCMI_FLEXGEN_56>, 1744 <&scmi_clk CK_SCMI_FLEXGEN_57>, 1745 <&scmi_clk CK_SCMI_FLEXGEN_58>, 1746 <&scmi_clk CK_SCMI_FLEXGEN_59>, 1747 <&scmi_clk CK_SCMI_FLEXGEN_60>, 1748 <&scmi_clk CK_SCMI_FLEXGEN_61>, 1749 <&scmi_clk CK_SCMI_FLEXGEN_62>, 1750 <&scmi_clk CK_SCMI_FLEXGEN_63>, 1751 <&scmi_clk CK_SCMI_ICN_APB1>, 1752 <&scmi_clk CK_SCMI_ICN_APB2>, 1753 <&scmi_clk CK_SCMI_ICN_APB3>, 1754 <&scmi_clk CK_SCMI_ICN_APB4>, 1755 <&scmi_clk CK_SCMI_ICN_APBDBG>, 1756 <&scmi_clk CK_SCMI_TIMG1>, 1757 <&scmi_clk CK_SCMI_TIMG2>, 1758 <&scmi_clk CK_SCMI_PLL3>, 1759 <&clk_dsi_txbyte>; 1760 access-controllers = <&rifsc 156>; 1761 }; 1762 1763 exti1: interrupt-controller@44220000 { 1764 compatible = "st,stm32mp1-exti", "syscon"; 1765 interrupt-controller; 1766 #interrupt-cells = <2>; 1767 reg = <0x44220000 0x400>; 1768 interrupts-extended = 1769 <&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 1770 <&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 1771 <&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 1772 <&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 1773 <&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 1774 <&intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 1775 <&intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 1776 <&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 1777 <&intc GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 1778 <&intc GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 1779 <&intc GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 1780 <&intc GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1781 <&intc GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1782 <&intc GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1783 <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1784 <&intc GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1785 <&intc GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 1786 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 1787 <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1788 <&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1789 <0>, /* EXTI_20 */ 1790 <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1791 <&intc GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1792 <&intc GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1793 <&intc GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1794 <&intc GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1795 <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1796 <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1797 <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1798 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1799 <&intc GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 1800 <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1801 <&intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1802 <&intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1803 <&intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1804 <0>, 1805 <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1806 <&intc GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1807 <&intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1808 <&intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 1809 <&intc GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 1810 <&intc GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 1811 <&intc GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1812 <&intc GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1813 <&intc GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1814 <&intc GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 1815 <&intc GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1816 <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 1817 <&intc GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 1818 <&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1819 <&intc GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 1820 <0>, 1821 <0>, 1822 <0>, 1823 <0>, 1824 <0>, 1825 <0>, 1826 <0>, 1827 <0>, 1828 <&intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1829 <0>, /* EXTI_60 */ 1830 <&intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1831 <0>, 1832 <0>, 1833 <&intc GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1834 <0>, 1835 <0>, 1836 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1837 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1838 <0>, 1839 <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ 1840 <0>, 1841 <&intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 1842 <&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 1843 <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1844 <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1845 <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 1846 <&intc GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1847 <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1848 <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1849 <0>, /* EXTI_80 */ 1850 <0>, 1851 <0>, 1852 <&intc GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 1853 <&intc GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 1854 }; 1855 1856 syscfg: syscon@44230000 { 1857 compatible = "st,stm32mp25-syscfg", "syscon"; 1858 reg = <0x44230000 0x10000>; 1859 }; 1860 1861 pinctrl: pinctrl@44240000 { 1862 #address-cells = <1>; 1863 #size-cells = <1>; 1864 compatible = "st,stm32mp257-pinctrl"; 1865 ranges = <0 0x44240000 0xa0400>; 1866 interrupt-parent = <&exti1>; 1867 st,syscfg = <&exti1 0x60 0xff>; 1868 pins-are-numbered; 1869 1870 gpioa: gpio@44240000 { 1871 gpio-controller; 1872 #gpio-cells = <2>; 1873 interrupt-controller; 1874 #interrupt-cells = <2>; 1875 reg = <0x0 0x400>; 1876 clocks = <&scmi_clk CK_SCMI_GPIOA>; 1877 st,bank-name = "GPIOA"; 1878 status = "disabled"; 1879 }; 1880 1881 gpiob: gpio@44250000 { 1882 gpio-controller; 1883 #gpio-cells = <2>; 1884 interrupt-controller; 1885 #interrupt-cells = <2>; 1886 reg = <0x10000 0x400>; 1887 clocks = <&scmi_clk CK_SCMI_GPIOB>; 1888 st,bank-name = "GPIOB"; 1889 status = "disabled"; 1890 }; 1891 1892 gpioc: gpio@44260000 { 1893 gpio-controller; 1894 #gpio-cells = <2>; 1895 interrupt-controller; 1896 #interrupt-cells = <2>; 1897 reg = <0x20000 0x400>; 1898 clocks = <&scmi_clk CK_SCMI_GPIOC>; 1899 st,bank-name = "GPIOC"; 1900 status = "disabled"; 1901 }; 1902 1903 gpiod: gpio@44270000 { 1904 gpio-controller; 1905 #gpio-cells = <2>; 1906 interrupt-controller; 1907 #interrupt-cells = <2>; 1908 reg = <0x30000 0x400>; 1909 clocks = <&scmi_clk CK_SCMI_GPIOD>; 1910 st,bank-name = "GPIOD"; 1911 status = "disabled"; 1912 }; 1913 1914 gpioe: gpio@44280000 { 1915 gpio-controller; 1916 #gpio-cells = <2>; 1917 interrupt-controller; 1918 #interrupt-cells = <2>; 1919 reg = <0x40000 0x400>; 1920 clocks = <&scmi_clk CK_SCMI_GPIOE>; 1921 st,bank-name = "GPIOE"; 1922 status = "disabled"; 1923 }; 1924 1925 gpiof: gpio@44290000 { 1926 gpio-controller; 1927 #gpio-cells = <2>; 1928 interrupt-controller; 1929 #interrupt-cells = <2>; 1930 reg = <0x50000 0x400>; 1931 clocks = <&scmi_clk CK_SCMI_GPIOF>; 1932 st,bank-name = "GPIOF"; 1933 status = "disabled"; 1934 }; 1935 1936 gpiog: gpio@442a0000 { 1937 gpio-controller; 1938 #gpio-cells = <2>; 1939 interrupt-controller; 1940 #interrupt-cells = <2>; 1941 reg = <0x60000 0x400>; 1942 clocks = <&scmi_clk CK_SCMI_GPIOG>; 1943 st,bank-name = "GPIOG"; 1944 status = "disabled"; 1945 }; 1946 1947 gpioh: gpio@442b0000 { 1948 gpio-controller; 1949 #gpio-cells = <2>; 1950 interrupt-controller; 1951 #interrupt-cells = <2>; 1952 reg = <0x70000 0x400>; 1953 clocks = <&scmi_clk CK_SCMI_GPIOH>; 1954 st,bank-name = "GPIOH"; 1955 status = "disabled"; 1956 }; 1957 1958 gpioi: gpio@442c0000 { 1959 gpio-controller; 1960 #gpio-cells = <2>; 1961 interrupt-controller; 1962 #interrupt-cells = <2>; 1963 reg = <0x80000 0x400>; 1964 clocks = <&scmi_clk CK_SCMI_GPIOI>; 1965 st,bank-name = "GPIOI"; 1966 status = "disabled"; 1967 }; 1968 1969 gpioj: gpio@442d0000 { 1970 gpio-controller; 1971 #gpio-cells = <2>; 1972 interrupt-controller; 1973 #interrupt-cells = <2>; 1974 reg = <0x90000 0x400>; 1975 clocks = <&scmi_clk CK_SCMI_GPIOJ>; 1976 st,bank-name = "GPIOJ"; 1977 status = "disabled"; 1978 }; 1979 1980 gpiok: gpio@442e0000 { 1981 gpio-controller; 1982 #gpio-cells = <2>; 1983 interrupt-controller; 1984 #interrupt-cells = <2>; 1985 reg = <0xa0000 0x400>; 1986 clocks = <&scmi_clk CK_SCMI_GPIOK>; 1987 st,bank-name = "GPIOK"; 1988 status = "disabled"; 1989 }; 1990 }; 1991 1992 rtc: rtc@46000000 { 1993 compatible = "st,stm32mp25-rtc"; 1994 reg = <0x46000000 0x400>; 1995 clocks = <&scmi_clk CK_SCMI_RTC>, 1996 <&scmi_clk CK_SCMI_RTCCK>; 1997 clock-names = "pclk", "rtc_ck"; 1998 interrupts-extended = <&exti2 17 IRQ_TYPE_LEVEL_HIGH>; 1999 status = "disabled"; 2000 }; 2001 2002 pinctrl_z: pinctrl@46200000 { 2003 #address-cells = <1>; 2004 #size-cells = <1>; 2005 compatible = "st,stm32mp257-z-pinctrl"; 2006 ranges = <0 0x46200000 0x400>; 2007 interrupt-parent = <&exti1>; 2008 st,syscfg = <&exti1 0x60 0xff>; 2009 pins-are-numbered; 2010 2011 gpioz: gpio@46200000 { 2012 gpio-controller; 2013 #gpio-cells = <2>; 2014 interrupt-controller; 2015 #interrupt-cells = <2>; 2016 reg = <0 0x400>; 2017 clocks = <&scmi_clk CK_SCMI_GPIOZ>; 2018 st,bank-name = "GPIOZ"; 2019 st,bank-ioport = <11>; 2020 status = "disabled"; 2021 }; 2022 }; 2023 2024 exti2: interrupt-controller@46230000 { 2025 compatible = "st,stm32mp1-exti", "syscon"; 2026 interrupt-controller; 2027 #interrupt-cells = <2>; 2028 reg = <0x46230000 0x400>; 2029 interrupts-extended = 2030 <&intc GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 2031 <&intc GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 2032 <&intc GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 2033 <&intc GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 2034 <&intc GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 2035 <&intc GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 2036 <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 2037 <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 2038 <&intc GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 2039 <&intc GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 2040 <&intc GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 2041 <&intc GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 2042 <&intc GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 2043 <&intc GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 2044 <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 2045 <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 2046 <&intc GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 2047 <&intc GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 2048 <0>, 2049 <0>, 2050 <0>, /* EXTI_20 */ 2051 <&intc GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 2052 <&intc GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 2053 <0>, 2054 <0>, 2055 <&intc GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 2056 <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 2057 <&intc GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 2058 <0>, 2059 <&intc GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 2060 <&intc GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 2061 <&intc GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 2062 <0>, 2063 <&intc GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2064 <&intc GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 2065 <0>, 2066 <0>, 2067 <&intc GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 2068 <0>, 2069 <0>, 2070 <&intc GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 2071 <0>, 2072 <0>, 2073 <&intc GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 2074 <0>, 2075 <0>, 2076 <&intc GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 2077 <0>, 2078 <&intc GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 2079 <&intc GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2080 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 2081 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 2082 <&intc GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 2083 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2084 <0>, 2085 <0>, 2086 <0>, 2087 <0>, 2088 <0>, 2089 <0>, 2090 <0>, /* EXTI_60 */ 2091 <&intc GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 2092 <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 2093 <0>, 2094 <&intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 2095 <&intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 2096 <&intc GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 2097 <&intc GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2098 <0>, 2099 <0>, 2100 <&intc GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ 2101 }; 2102 }; 2103}; 2104