1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/clock/st,stm32mp25-rcc.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/reset/st,stm32mp25-rcc.h> 9#include <dt-bindings/regulator/st,stm32mp25-regulator.h> 10 11/ { 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a35"; 21 device_type = "cpu"; 22 reg = <0>; 23 enable-method = "psci"; 24 power-domains = <&CPU_PD0>; 25 power-domain-names = "psci"; 26 }; 27 }; 28 29 arm-pmu { 30 compatible = "arm,cortex-a35-pmu"; 31 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 32 interrupt-affinity = <&cpu0>; 33 interrupt-parent = <&intc>; 34 }; 35 36 arm_wdt: watchdog { 37 compatible = "arm,smc-wdt"; 38 arm,smc-id = <0xb200005a>; 39 status = "disabled"; 40 }; 41 42 clocks { 43 clk_dsi_txbyte: txbyteclk { 44 #clock-cells = <0>; 45 compatible = "fixed-clock"; 46 clock-frequency = <0>; 47 }; 48 49 clk_rcbsec: clk-rcbsec { 50 #clock-cells = <0>; 51 compatible = "fixed-clock"; 52 clock-frequency = <64000000>; 53 }; 54 }; 55 56 firmware { 57 optee: optee { 58 compatible = "linaro,optee-tz"; 59 method = "smc"; 60 interrupt-parent = <&intc>; 61 interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 62 }; 63 64 scmi { 65 compatible = "linaro,scmi-optee"; 66 #address-cells = <1>; 67 #size-cells = <0>; 68 linaro,optee-channel-id = <0>; 69 70 scmi_clk: protocol@14 { 71 reg = <0x14>; 72 #clock-cells = <1>; 73 }; 74 75 scmi_reset: protocol@16 { 76 reg = <0x16>; 77 #reset-cells = <1>; 78 }; 79 80 scmi_voltd: protocol@17 { 81 reg = <0x17>; 82 83 scmi_regu: regulators { 84 #address-cells = <1>; 85 #size-cells = <0>; 86 87 scmi_vddio1: regulator@0 { 88 reg = <VOLTD_SCMI_VDDIO1>; 89 regulator-name = "vddio1"; 90 }; 91 scmi_vddio2: regulator@1 { 92 reg = <VOLTD_SCMI_VDDIO2>; 93 regulator-name = "vddio2"; 94 }; 95 scmi_vddio3: regulator@2 { 96 reg = <VOLTD_SCMI_VDDIO3>; 97 regulator-name = "vddio3"; 98 }; 99 scmi_vddio4: regulator@3 { 100 reg = <VOLTD_SCMI_VDDIO4>; 101 regulator-name = "vddio4"; 102 }; 103 scmi_vdd33ucpd: regulator@5 { 104 reg = <VOLTD_SCMI_UCPD>; 105 regulator-name = "vdd33ucpd"; 106 }; 107 scmi_vdda18adc: regulator@7 { 108 reg = <VOLTD_SCMI_ADC>; 109 regulator-name = "vdda18adc"; 110 }; 111 }; 112 }; 113 }; 114 }; 115 116 intc: interrupt-controller@4ac00000 { 117 compatible = "arm,cortex-a7-gic"; 118 #interrupt-cells = <3>; 119 #address-cells = <1>; 120 interrupt-controller; 121 reg = <0x0 0x4ac10000 0x0 0x1000>, 122 <0x0 0x4ac20000 0x0 0x2000>, 123 <0x0 0x4ac40000 0x0 0x2000>, 124 <0x0 0x4ac60000 0x0 0x2000>; 125 }; 126 127 psci { 128 compatible = "arm,psci-1.0"; 129 method = "smc"; 130 131 CPU_PD0: power-domain-cpu0 { 132 #power-domain-cells = <0>; 133 power-domains = <&CLUSTER_PD>; 134 }; 135 136 CLUSTER_PD: power-domain-cluster { 137 #power-domain-cells = <0>; 138 power-domains = <&RET_PD>; 139 }; 140 141 RET_PD: power-domain-retention { 142 #power-domain-cells = <0>; 143 }; 144 }; 145 146 timer { 147 compatible = "arm,armv8-timer"; 148 interrupt-parent = <&intc>; 149 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 150 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 151 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 152 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 153 always-on; 154 }; 155 156 soc@0 { 157 compatible = "simple-bus"; 158 #address-cells = <1>; 159 #size-cells = <1>; 160 interrupt-parent = <&intc>; 161 ranges = <0x0 0x0 0x0 0x80000000>; 162 163 hpdma: dma-controller@40400000 { 164 compatible = "st,stm32mp25-dma3"; 165 reg = <0x40400000 0x1000>; 166 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 182 clocks = <&scmi_clk CK_SCMI_HPDMA1>; 183 #dma-cells = <3>; 184 }; 185 186 hpdma2: dma-controller@40410000 { 187 compatible = "st,stm32mp25-dma3"; 188 reg = <0x40410000 0x1000>; 189 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&scmi_clk CK_SCMI_HPDMA2>; 206 #dma-cells = <3>; 207 }; 208 209 hpdma3: dma-controller@40420000 { 210 compatible = "st,stm32mp25-dma3"; 211 reg = <0x40420000 0x1000>; 212 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&scmi_clk CK_SCMI_HPDMA3>; 229 #dma-cells = <3>; 230 }; 231 232 rifsc: bus@42080000 { 233 compatible = "st,stm32mp25-rifsc", "simple-bus"; 234 reg = <0x42080000 0x1000>; 235 #address-cells = <1>; 236 #size-cells = <1>; 237 #access-controller-cells = <1>; 238 ranges; 239 240 spi2: spi@400b0000 { 241 #address-cells = <1>; 242 #size-cells = <0>; 243 compatible = "st,stm32mp25-spi"; 244 reg = <0x400b0000 0x400>; 245 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&rcc CK_KER_SPI2>; 247 resets = <&rcc SPI2_R>; 248 access-controllers = <&rifsc 23>; 249 status = "disabled"; 250 }; 251 252 spi3: spi@400c0000 { 253 #address-cells = <1>; 254 #size-cells = <0>; 255 compatible = "st,stm32mp25-spi"; 256 reg = <0x400c0000 0x400>; 257 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&rcc CK_KER_SPI3>; 259 resets = <&rcc SPI3_R>; 260 access-controllers = <&rifsc 24>; 261 status = "disabled"; 262 }; 263 264 usart2: serial@400e0000 { 265 compatible = "st,stm32h7-uart"; 266 reg = <0x400e0000 0x400>; 267 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&rcc CK_KER_USART2>; 269 access-controllers = <&rifsc 32>; 270 status = "disabled"; 271 }; 272 273 usart3: serial@400f0000 { 274 compatible = "st,stm32h7-uart"; 275 reg = <0x400f0000 0x400>; 276 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 277 clocks = <&rcc CK_KER_USART3>; 278 access-controllers = <&rifsc 33>; 279 status = "disabled"; 280 }; 281 282 uart4: serial@40100000 { 283 compatible = "st,stm32h7-uart"; 284 reg = <0x40100000 0x400>; 285 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&rcc CK_KER_UART4>; 287 access-controllers = <&rifsc 34>; 288 status = "disabled"; 289 }; 290 291 uart5: serial@40110000 { 292 compatible = "st,stm32h7-uart"; 293 reg = <0x40110000 0x400>; 294 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&rcc CK_KER_UART5>; 296 access-controllers = <&rifsc 35>; 297 status = "disabled"; 298 }; 299 300 i2c1: i2c@40120000 { 301 compatible = "st,stm32mp25-i2c"; 302 reg = <0x40120000 0x400>; 303 interrupt-names = "event"; 304 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&rcc CK_KER_I2C1>; 306 resets = <&rcc I2C1_R>; 307 #address-cells = <1>; 308 #size-cells = <0>; 309 access-controllers = <&rifsc 41>; 310 status = "disabled"; 311 }; 312 313 i2c2: i2c@40130000 { 314 compatible = "st,stm32mp25-i2c"; 315 reg = <0x40130000 0x400>; 316 interrupt-names = "event"; 317 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&rcc CK_KER_I2C2>; 319 resets = <&rcc I2C2_R>; 320 #address-cells = <1>; 321 #size-cells = <0>; 322 access-controllers = <&rifsc 42>; 323 status = "disabled"; 324 }; 325 326 i2c3: i2c@40140000 { 327 compatible = "st,stm32mp25-i2c"; 328 reg = <0x40140000 0x400>; 329 interrupt-names = "event"; 330 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&rcc CK_KER_I2C3>; 332 resets = <&rcc I2C3_R>; 333 #address-cells = <1>; 334 #size-cells = <0>; 335 access-controllers = <&rifsc 43>; 336 status = "disabled"; 337 }; 338 339 i2c4: i2c@40150000 { 340 compatible = "st,stm32mp25-i2c"; 341 reg = <0x40150000 0x400>; 342 interrupt-names = "event"; 343 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&rcc CK_KER_I2C4>; 345 resets = <&rcc I2C4_R>; 346 #address-cells = <1>; 347 #size-cells = <0>; 348 access-controllers = <&rifsc 44>; 349 status = "disabled"; 350 }; 351 352 i2c5: i2c@40160000 { 353 compatible = "st,stm32mp25-i2c"; 354 reg = <0x40160000 0x400>; 355 interrupt-names = "event"; 356 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&rcc CK_KER_I2C5>; 358 resets = <&rcc I2C5_R>; 359 #address-cells = <1>; 360 #size-cells = <0>; 361 access-controllers = <&rifsc 45>; 362 status = "disabled"; 363 }; 364 365 i2c6: i2c@40170000 { 366 compatible = "st,stm32mp25-i2c"; 367 reg = <0x40170000 0x400>; 368 interrupt-names = "event"; 369 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 370 clocks = <&rcc CK_KER_I2C6>; 371 resets = <&rcc I2C6_R>; 372 #address-cells = <1>; 373 #size-cells = <0>; 374 access-controllers = <&rifsc 46>; 375 status = "disabled"; 376 }; 377 378 i2c7: i2c@40180000 { 379 compatible = "st,stm32mp25-i2c"; 380 reg = <0x40180000 0x400>; 381 interrupt-names = "event"; 382 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&rcc CK_KER_I2C7>; 384 resets = <&rcc I2C7_R>; 385 #address-cells = <1>; 386 #size-cells = <0>; 387 access-controllers = <&rifsc 47>; 388 status = "disabled"; 389 }; 390 391 usart6: serial@40220000 { 392 compatible = "st,stm32h7-uart"; 393 reg = <0x40220000 0x400>; 394 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&rcc CK_KER_USART6>; 396 access-controllers = <&rifsc 36>; 397 status = "disabled"; 398 }; 399 400 spi1: spi@40230000 { 401 #address-cells = <1>; 402 #size-cells = <0>; 403 compatible = "st,stm32mp25-spi"; 404 reg = <0x40230000 0x400>; 405 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&rcc CK_KER_SPI1>; 407 resets = <&rcc SPI1_R>; 408 access-controllers = <&rifsc 22>; 409 status = "disabled"; 410 }; 411 412 spi4: spi@40240000 { 413 #address-cells = <1>; 414 #size-cells = <0>; 415 compatible = "st,stm32mp25-spi"; 416 reg = <0x40240000 0x400>; 417 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&rcc CK_KER_SPI4>; 419 resets = <&rcc SPI4_R>; 420 access-controllers = <&rifsc 25>; 421 status = "disabled"; 422 }; 423 424 spi5: spi@40280000 { 425 #address-cells = <1>; 426 #size-cells = <0>; 427 compatible = "st,stm32mp25-spi"; 428 reg = <0x40280000 0x400>; 429 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&rcc CK_KER_SPI5>; 431 resets = <&rcc SPI5_R>; 432 access-controllers = <&rifsc 26>; 433 status = "disabled"; 434 }; 435 436 uart9: serial@402c0000 { 437 compatible = "st,stm32h7-uart"; 438 reg = <0x402c0000 0x400>; 439 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&rcc CK_KER_UART9>; 441 access-controllers = <&rifsc 39>; 442 status = "disabled"; 443 }; 444 445 usart1: serial@40330000 { 446 compatible = "st,stm32h7-uart"; 447 reg = <0x40330000 0x400>; 448 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&rcc CK_KER_USART1>; 450 access-controllers = <&rifsc 31>; 451 status = "disabled"; 452 }; 453 454 spi6: spi@40350000 { 455 #address-cells = <1>; 456 #size-cells = <0>; 457 compatible = "st,stm32mp25-spi"; 458 reg = <0x40350000 0x400>; 459 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&rcc CK_KER_SPI6>; 461 resets = <&rcc SPI6_R>; 462 access-controllers = <&rifsc 27>; 463 status = "disabled"; 464 }; 465 466 spi7: spi@40360000 { 467 #address-cells = <1>; 468 #size-cells = <0>; 469 compatible = "st,stm32mp25-spi"; 470 reg = <0x40360000 0x400>; 471 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&rcc CK_KER_SPI7>; 473 resets = <&rcc SPI7_R>; 474 access-controllers = <&rifsc 28>; 475 status = "disabled"; 476 }; 477 478 uart7: serial@40370000 { 479 compatible = "st,stm32h7-uart"; 480 reg = <0x40370000 0x400>; 481 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 482 clocks = <&rcc CK_KER_UART7>; 483 access-controllers = <&rifsc 37>; 484 status = "disabled"; 485 }; 486 487 uart8: serial@40380000 { 488 compatible = "st,stm32h7-uart"; 489 reg = <0x40380000 0x400>; 490 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 491 clocks = <&rcc CK_KER_UART8>; 492 access-controllers = <&rifsc 38>; 493 status = "disabled"; 494 }; 495 496 spi8: spi@46020000 { 497 #address-cells = <1>; 498 #size-cells = <0>; 499 compatible = "st,stm32mp25-spi"; 500 reg = <0x46020000 0x400>; 501 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&rcc CK_KER_SPI8>; 503 resets = <&rcc SPI8_R>; 504 access-controllers = <&rifsc 29>; 505 status = "disabled"; 506 }; 507 508 i2c8: i2c@46040000 { 509 compatible = "st,stm32mp25-i2c"; 510 reg = <0x46040000 0x400>; 511 interrupt-names = "event"; 512 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 513 clocks = <&rcc CK_KER_I2C8>; 514 resets = <&rcc I2C8_R>; 515 #address-cells = <1>; 516 #size-cells = <0>; 517 access-controllers = <&rifsc 48>; 518 status = "disabled"; 519 }; 520 521 sdmmc1: mmc@48220000 { 522 compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; 523 arm,primecell-periphid = <0x00353180>; 524 reg = <0x48220000 0x400>, <0x44230400 0x8>; 525 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 526 clocks = <&rcc CK_KER_SDMMC1 >; 527 clock-names = "apb_pclk"; 528 resets = <&rcc SDMMC1_R>; 529 cap-sd-highspeed; 530 cap-mmc-highspeed; 531 max-frequency = <120000000>; 532 access-controllers = <&rifsc 76>; 533 status = "disabled"; 534 }; 535 536 ethernet1: ethernet@482c0000 { 537 compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20"; 538 reg = <0x482c0000 0x4000>; 539 reg-names = "stmmaceth"; 540 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 541 interrupt-names = "macirq"; 542 clock-names = "stmmaceth", 543 "mac-clk-tx", 544 "mac-clk-rx", 545 "ptp_ref", 546 "ethstp", 547 "eth-ck"; 548 clocks = <&rcc CK_ETH1_MAC>, 549 <&rcc CK_ETH1_TX>, 550 <&rcc CK_ETH1_RX>, 551 <&rcc CK_KER_ETH1PTP>, 552 <&rcc CK_ETH1_STP>, 553 <&rcc CK_KER_ETH1>; 554 snps,axi-config = <&stmmac_axi_config_1>; 555 snps,mixed-burst; 556 snps,mtl-rx-config = <&mtl_rx_setup_1>; 557 snps,mtl-tx-config = <&mtl_tx_setup_1>; 558 snps,pbl = <2>; 559 snps,tso; 560 st,syscon = <&syscfg 0x3000>; 561 access-controllers = <&rifsc 60>; 562 status = "disabled"; 563 564 mtl_rx_setup_1: rx-queues-config { 565 snps,rx-queues-to-use = <2>; 566 queue0 {}; 567 queue1 {}; 568 }; 569 570 mtl_tx_setup_1: tx-queues-config { 571 snps,tx-queues-to-use = <4>; 572 queue0 {}; 573 queue1 {}; 574 queue2 {}; 575 queue3 {}; 576 }; 577 578 stmmac_axi_config_1: stmmac-axi-config { 579 snps,blen = <0 0 0 0 16 8 4>; 580 snps,rd_osr_lmt = <0x7>; 581 snps,wr_osr_lmt = <0x7>; 582 }; 583 }; 584 }; 585 586 bsec: efuse@44000000 { 587 compatible = "st,stm32mp25-bsec"; 588 reg = <0x44000000 0x1000>; 589 #address-cells = <1>; 590 #size-cells = <1>; 591 592 part_number_otp@24 { 593 reg = <0x24 0x4>; 594 }; 595 596 package_otp@1e8 { 597 reg = <0x1e8 0x1>; 598 bits = <0 3>; 599 }; 600 }; 601 602 rcc: clock-controller@44200000 { 603 compatible = "st,stm32mp25-rcc"; 604 reg = <0x44200000 0x10000>; 605 #clock-cells = <1>; 606 #reset-cells = <1>; 607 clocks = <&scmi_clk CK_SCMI_HSE>, 608 <&scmi_clk CK_SCMI_HSI>, 609 <&scmi_clk CK_SCMI_MSI>, 610 <&scmi_clk CK_SCMI_LSE>, 611 <&scmi_clk CK_SCMI_LSI>, 612 <&scmi_clk CK_SCMI_HSE_DIV2>, 613 <&scmi_clk CK_SCMI_ICN_HS_MCU>, 614 <&scmi_clk CK_SCMI_ICN_LS_MCU>, 615 <&scmi_clk CK_SCMI_ICN_SDMMC>, 616 <&scmi_clk CK_SCMI_ICN_DDR>, 617 <&scmi_clk CK_SCMI_ICN_DISPLAY>, 618 <&scmi_clk CK_SCMI_ICN_HSL>, 619 <&scmi_clk CK_SCMI_ICN_NIC>, 620 <&scmi_clk CK_SCMI_ICN_VID>, 621 <&scmi_clk CK_SCMI_FLEXGEN_07>, 622 <&scmi_clk CK_SCMI_FLEXGEN_08>, 623 <&scmi_clk CK_SCMI_FLEXGEN_09>, 624 <&scmi_clk CK_SCMI_FLEXGEN_10>, 625 <&scmi_clk CK_SCMI_FLEXGEN_11>, 626 <&scmi_clk CK_SCMI_FLEXGEN_12>, 627 <&scmi_clk CK_SCMI_FLEXGEN_13>, 628 <&scmi_clk CK_SCMI_FLEXGEN_14>, 629 <&scmi_clk CK_SCMI_FLEXGEN_15>, 630 <&scmi_clk CK_SCMI_FLEXGEN_16>, 631 <&scmi_clk CK_SCMI_FLEXGEN_17>, 632 <&scmi_clk CK_SCMI_FLEXGEN_18>, 633 <&scmi_clk CK_SCMI_FLEXGEN_19>, 634 <&scmi_clk CK_SCMI_FLEXGEN_20>, 635 <&scmi_clk CK_SCMI_FLEXGEN_21>, 636 <&scmi_clk CK_SCMI_FLEXGEN_22>, 637 <&scmi_clk CK_SCMI_FLEXGEN_23>, 638 <&scmi_clk CK_SCMI_FLEXGEN_24>, 639 <&scmi_clk CK_SCMI_FLEXGEN_25>, 640 <&scmi_clk CK_SCMI_FLEXGEN_26>, 641 <&scmi_clk CK_SCMI_FLEXGEN_27>, 642 <&scmi_clk CK_SCMI_FLEXGEN_28>, 643 <&scmi_clk CK_SCMI_FLEXGEN_29>, 644 <&scmi_clk CK_SCMI_FLEXGEN_30>, 645 <&scmi_clk CK_SCMI_FLEXGEN_31>, 646 <&scmi_clk CK_SCMI_FLEXGEN_32>, 647 <&scmi_clk CK_SCMI_FLEXGEN_33>, 648 <&scmi_clk CK_SCMI_FLEXGEN_34>, 649 <&scmi_clk CK_SCMI_FLEXGEN_35>, 650 <&scmi_clk CK_SCMI_FLEXGEN_36>, 651 <&scmi_clk CK_SCMI_FLEXGEN_37>, 652 <&scmi_clk CK_SCMI_FLEXGEN_38>, 653 <&scmi_clk CK_SCMI_FLEXGEN_39>, 654 <&scmi_clk CK_SCMI_FLEXGEN_40>, 655 <&scmi_clk CK_SCMI_FLEXGEN_41>, 656 <&scmi_clk CK_SCMI_FLEXGEN_42>, 657 <&scmi_clk CK_SCMI_FLEXGEN_43>, 658 <&scmi_clk CK_SCMI_FLEXGEN_44>, 659 <&scmi_clk CK_SCMI_FLEXGEN_45>, 660 <&scmi_clk CK_SCMI_FLEXGEN_46>, 661 <&scmi_clk CK_SCMI_FLEXGEN_47>, 662 <&scmi_clk CK_SCMI_FLEXGEN_48>, 663 <&scmi_clk CK_SCMI_FLEXGEN_49>, 664 <&scmi_clk CK_SCMI_FLEXGEN_50>, 665 <&scmi_clk CK_SCMI_FLEXGEN_51>, 666 <&scmi_clk CK_SCMI_FLEXGEN_52>, 667 <&scmi_clk CK_SCMI_FLEXGEN_53>, 668 <&scmi_clk CK_SCMI_FLEXGEN_54>, 669 <&scmi_clk CK_SCMI_FLEXGEN_55>, 670 <&scmi_clk CK_SCMI_FLEXGEN_56>, 671 <&scmi_clk CK_SCMI_FLEXGEN_57>, 672 <&scmi_clk CK_SCMI_FLEXGEN_58>, 673 <&scmi_clk CK_SCMI_FLEXGEN_59>, 674 <&scmi_clk CK_SCMI_FLEXGEN_60>, 675 <&scmi_clk CK_SCMI_FLEXGEN_61>, 676 <&scmi_clk CK_SCMI_FLEXGEN_62>, 677 <&scmi_clk CK_SCMI_FLEXGEN_63>, 678 <&scmi_clk CK_SCMI_ICN_APB1>, 679 <&scmi_clk CK_SCMI_ICN_APB2>, 680 <&scmi_clk CK_SCMI_ICN_APB3>, 681 <&scmi_clk CK_SCMI_ICN_APB4>, 682 <&scmi_clk CK_SCMI_ICN_APBDBG>, 683 <&scmi_clk CK_SCMI_TIMG1>, 684 <&scmi_clk CK_SCMI_TIMG2>, 685 <&scmi_clk CK_SCMI_PLL3>, 686 <&clk_dsi_txbyte>; 687 access-controllers = <&rifsc 156>; 688 }; 689 690 exti1: interrupt-controller@44220000 { 691 compatible = "st,stm32mp1-exti", "syscon"; 692 interrupt-controller; 693 #interrupt-cells = <2>; 694 reg = <0x44220000 0x400>; 695 interrupts-extended = 696 <&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 697 <&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 698 <&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 699 <&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 700 <&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 701 <&intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 702 <&intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 703 <&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 704 <&intc GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 705 <&intc GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 706 <&intc GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 707 <&intc GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 708 <&intc GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 709 <&intc GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 710 <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 711 <&intc GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 712 <&intc GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 713 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 714 <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 715 <&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 716 <0>, /* EXTI_20 */ 717 <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 718 <&intc GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 719 <&intc GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 720 <&intc GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 721 <&intc GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 722 <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 723 <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 724 <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 725 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 726 <&intc GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 727 <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 728 <&intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 729 <&intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 730 <&intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 731 <0>, 732 <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 733 <&intc GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 734 <&intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 735 <&intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 736 <&intc GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 737 <&intc GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 738 <&intc GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 739 <&intc GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 740 <&intc GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 741 <&intc GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 742 <&intc GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 743 <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 744 <&intc GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 745 <&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 746 <&intc GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 747 <0>, 748 <0>, 749 <0>, 750 <0>, 751 <0>, 752 <0>, 753 <0>, 754 <0>, 755 <&intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 756 <0>, /* EXTI_60 */ 757 <&intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 758 <0>, 759 <0>, 760 <&intc GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 761 <0>, 762 <0>, 763 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 764 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 765 <0>, 766 <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ 767 <0>, 768 <&intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 769 <&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 770 <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 771 <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 772 <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 773 <&intc GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 774 <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 775 <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 776 <0>, /* EXTI_80 */ 777 <0>, 778 <0>, 779 <&intc GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 780 <&intc GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 781 }; 782 783 syscfg: syscon@44230000 { 784 compatible = "st,stm32mp25-syscfg", "syscon"; 785 reg = <0x44230000 0x10000>; 786 }; 787 788 pinctrl: pinctrl@44240000 { 789 #address-cells = <1>; 790 #size-cells = <1>; 791 compatible = "st,stm32mp257-pinctrl"; 792 ranges = <0 0x44240000 0xa0400>; 793 interrupt-parent = <&exti1>; 794 st,syscfg = <&exti1 0x60 0xff>; 795 pins-are-numbered; 796 797 gpioa: gpio@44240000 { 798 gpio-controller; 799 #gpio-cells = <2>; 800 interrupt-controller; 801 #interrupt-cells = <2>; 802 reg = <0x0 0x400>; 803 clocks = <&scmi_clk CK_SCMI_GPIOA>; 804 st,bank-name = "GPIOA"; 805 status = "disabled"; 806 }; 807 808 gpiob: gpio@44250000 { 809 gpio-controller; 810 #gpio-cells = <2>; 811 interrupt-controller; 812 #interrupt-cells = <2>; 813 reg = <0x10000 0x400>; 814 clocks = <&scmi_clk CK_SCMI_GPIOB>; 815 st,bank-name = "GPIOB"; 816 status = "disabled"; 817 }; 818 819 gpioc: gpio@44260000 { 820 gpio-controller; 821 #gpio-cells = <2>; 822 interrupt-controller; 823 #interrupt-cells = <2>; 824 reg = <0x20000 0x400>; 825 clocks = <&scmi_clk CK_SCMI_GPIOC>; 826 st,bank-name = "GPIOC"; 827 status = "disabled"; 828 }; 829 830 gpiod: gpio@44270000 { 831 gpio-controller; 832 #gpio-cells = <2>; 833 interrupt-controller; 834 #interrupt-cells = <2>; 835 reg = <0x30000 0x400>; 836 clocks = <&scmi_clk CK_SCMI_GPIOD>; 837 st,bank-name = "GPIOD"; 838 status = "disabled"; 839 }; 840 841 gpioe: gpio@44280000 { 842 gpio-controller; 843 #gpio-cells = <2>; 844 interrupt-controller; 845 #interrupt-cells = <2>; 846 reg = <0x40000 0x400>; 847 clocks = <&scmi_clk CK_SCMI_GPIOE>; 848 st,bank-name = "GPIOE"; 849 status = "disabled"; 850 }; 851 852 gpiof: gpio@44290000 { 853 gpio-controller; 854 #gpio-cells = <2>; 855 interrupt-controller; 856 #interrupt-cells = <2>; 857 reg = <0x50000 0x400>; 858 clocks = <&scmi_clk CK_SCMI_GPIOF>; 859 st,bank-name = "GPIOF"; 860 status = "disabled"; 861 }; 862 863 gpiog: gpio@442a0000 { 864 gpio-controller; 865 #gpio-cells = <2>; 866 interrupt-controller; 867 #interrupt-cells = <2>; 868 reg = <0x60000 0x400>; 869 clocks = <&scmi_clk CK_SCMI_GPIOG>; 870 st,bank-name = "GPIOG"; 871 status = "disabled"; 872 }; 873 874 gpioh: gpio@442b0000 { 875 gpio-controller; 876 #gpio-cells = <2>; 877 interrupt-controller; 878 #interrupt-cells = <2>; 879 reg = <0x70000 0x400>; 880 clocks = <&scmi_clk CK_SCMI_GPIOH>; 881 st,bank-name = "GPIOH"; 882 status = "disabled"; 883 }; 884 885 gpioi: gpio@442c0000 { 886 gpio-controller; 887 #gpio-cells = <2>; 888 interrupt-controller; 889 #interrupt-cells = <2>; 890 reg = <0x80000 0x400>; 891 clocks = <&scmi_clk CK_SCMI_GPIOI>; 892 st,bank-name = "GPIOI"; 893 status = "disabled"; 894 }; 895 896 gpioj: gpio@442d0000 { 897 gpio-controller; 898 #gpio-cells = <2>; 899 interrupt-controller; 900 #interrupt-cells = <2>; 901 reg = <0x90000 0x400>; 902 clocks = <&scmi_clk CK_SCMI_GPIOJ>; 903 st,bank-name = "GPIOJ"; 904 status = "disabled"; 905 }; 906 907 gpiok: gpio@442e0000 { 908 gpio-controller; 909 #gpio-cells = <2>; 910 interrupt-controller; 911 #interrupt-cells = <2>; 912 reg = <0xa0000 0x400>; 913 clocks = <&scmi_clk CK_SCMI_GPIOK>; 914 st,bank-name = "GPIOK"; 915 status = "disabled"; 916 }; 917 }; 918 919 pinctrl_z: pinctrl@46200000 { 920 #address-cells = <1>; 921 #size-cells = <1>; 922 compatible = "st,stm32mp257-z-pinctrl"; 923 ranges = <0 0x46200000 0x400>; 924 interrupt-parent = <&exti1>; 925 st,syscfg = <&exti1 0x60 0xff>; 926 pins-are-numbered; 927 928 gpioz: gpio@46200000 { 929 gpio-controller; 930 #gpio-cells = <2>; 931 interrupt-controller; 932 #interrupt-cells = <2>; 933 reg = <0 0x400>; 934 clocks = <&scmi_clk CK_SCMI_GPIOZ>; 935 st,bank-name = "GPIOZ"; 936 st,bank-ioport = <11>; 937 status = "disabled"; 938 }; 939 940 }; 941 942 exti2: interrupt-controller@46230000 { 943 compatible = "st,stm32mp1-exti", "syscon"; 944 interrupt-controller; 945 #interrupt-cells = <2>; 946 reg = <0x46230000 0x400>; 947 interrupts-extended = 948 <&intc GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 949 <&intc GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 950 <&intc GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 951 <&intc GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 952 <&intc GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 953 <&intc GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 954 <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 955 <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 956 <&intc GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 957 <&intc GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 958 <&intc GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 959 <&intc GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 960 <&intc GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 961 <&intc GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 962 <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 963 <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 964 <&intc GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 965 <&intc GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 966 <0>, 967 <0>, 968 <0>, /* EXTI_20 */ 969 <&intc GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 970 <&intc GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 971 <0>, 972 <0>, 973 <&intc GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 974 <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 975 <&intc GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 976 <0>, 977 <&intc GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 978 <&intc GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 979 <&intc GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 980 <0>, 981 <&intc GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 982 <&intc GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 983 <0>, 984 <0>, 985 <&intc GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 986 <0>, 987 <0>, 988 <&intc GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 989 <0>, 990 <0>, 991 <&intc GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 992 <0>, 993 <0>, 994 <&intc GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 995 <0>, 996 <&intc GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 997 <&intc GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 998 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 999 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1000 <&intc GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 1001 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1002 <0>, 1003 <0>, 1004 <0>, 1005 <0>, 1006 <0>, 1007 <0>, 1008 <0>, /* EXTI_60 */ 1009 <&intc GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 1010 <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1011 <0>, 1012 <&intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1013 <&intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1014 <&intc GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1015 <&intc GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1016 <0>, 1017 <0>, 1018 <&intc GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ 1019 }; 1020 }; 1021}; 1022