1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7 8/ { 9 #address-cells = <2>; 10 #size-cells = <2>; 11 12 cpus { 13 #address-cells = <1>; 14 #size-cells = <0>; 15 16 cpu0: cpu@0 { 17 compatible = "arm,cortex-a35"; 18 device_type = "cpu"; 19 reg = <0>; 20 enable-method = "psci"; 21 }; 22 }; 23 24 arm-pmu { 25 compatible = "arm,cortex-a35-pmu"; 26 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 27 interrupt-affinity = <&cpu0>; 28 interrupt-parent = <&intc>; 29 }; 30 31 arm_wdt: watchdog { 32 compatible = "arm,smc-wdt"; 33 arm,smc-id = <0xb200005a>; 34 status = "disabled"; 35 }; 36 37 clocks { 38 ck_flexgen_08: ck-flexgen-08 { 39 #clock-cells = <0>; 40 compatible = "fixed-clock"; 41 clock-frequency = <100000000>; 42 }; 43 44 ck_flexgen_51: ck-flexgen-51 { 45 #clock-cells = <0>; 46 compatible = "fixed-clock"; 47 clock-frequency = <200000000>; 48 }; 49 50 ck_icn_ls_mcu: ck-icn-ls-mcu { 51 #clock-cells = <0>; 52 compatible = "fixed-clock"; 53 clock-frequency = <200000000>; 54 }; 55 56 ck_icn_p_vdec: ck-icn-p-vdec { 57 #clock-cells = <0>; 58 compatible = "fixed-clock"; 59 clock-frequency = <200000000>; 60 }; 61 62 ck_icn_p_venc: ck-icn-p-venc { 63 #clock-cells = <0>; 64 compatible = "fixed-clock"; 65 clock-frequency = <200000000>; 66 }; 67 }; 68 69 firmware { 70 optee { 71 compatible = "linaro,optee-tz"; 72 method = "smc"; 73 }; 74 75 scmi { 76 compatible = "linaro,scmi-optee"; 77 #address-cells = <1>; 78 #size-cells = <0>; 79 linaro,optee-channel-id = <0>; 80 81 scmi_clk: protocol@14 { 82 reg = <0x14>; 83 #clock-cells = <1>; 84 }; 85 86 scmi_reset: protocol@16 { 87 reg = <0x16>; 88 #reset-cells = <1>; 89 }; 90 }; 91 }; 92 93 intc: interrupt-controller@4ac00000 { 94 compatible = "arm,cortex-a7-gic"; 95 #interrupt-cells = <3>; 96 #address-cells = <1>; 97 interrupt-controller; 98 reg = <0x0 0x4ac10000 0x0 0x1000>, 99 <0x0 0x4ac20000 0x0 0x2000>, 100 <0x0 0x4ac40000 0x0 0x2000>, 101 <0x0 0x4ac60000 0x0 0x2000>; 102 }; 103 104 psci { 105 compatible = "arm,psci-1.0"; 106 method = "smc"; 107 }; 108 109 timer { 110 compatible = "arm,armv8-timer"; 111 interrupt-parent = <&intc>; 112 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 113 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 114 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 115 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 116 always-on; 117 }; 118 119 soc@0 { 120 compatible = "simple-bus"; 121 #address-cells = <1>; 122 #size-cells = <1>; 123 interrupt-parent = <&intc>; 124 ranges = <0x0 0x0 0x0 0x80000000>; 125 126 rifsc: rifsc-bus@42080000 { 127 compatible = "simple-bus"; 128 reg = <0x42080000 0x1000>; 129 #address-cells = <1>; 130 #size-cells = <1>; 131 ranges; 132 133 usart2: serial@400e0000 { 134 compatible = "st,stm32h7-uart"; 135 reg = <0x400e0000 0x400>; 136 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 137 clocks = <&ck_flexgen_08>; 138 status = "disabled"; 139 }; 140 141 sdmmc1: mmc@48220000 { 142 compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; 143 arm,primecell-periphid = <0x00353180>; 144 reg = <0x48220000 0x400>, <0x44230400 0x8>; 145 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 146 clocks = <&ck_flexgen_51>; 147 clock-names = "apb_pclk"; 148 cap-sd-highspeed; 149 cap-mmc-highspeed; 150 max-frequency = <120000000>; 151 status = "disabled"; 152 }; 153 }; 154 155 bsec: efuse@44000000 { 156 compatible = "st,stm32mp25-bsec"; 157 reg = <0x44000000 0x1000>; 158 #address-cells = <1>; 159 #size-cells = <1>; 160 161 part_number_otp@24 { 162 reg = <0x24 0x4>; 163 }; 164 165 package_otp@1e8 { 166 reg = <0x1e8 0x1>; 167 bits = <0 3>; 168 }; 169 }; 170 171 syscfg: syscon@44230000 { 172 compatible = "st,stm32mp25-syscfg", "syscon"; 173 reg = <0x44230000 0x10000>; 174 }; 175 176 pinctrl: pinctrl@44240000 { 177 #address-cells = <1>; 178 #size-cells = <1>; 179 compatible = "st,stm32mp257-pinctrl"; 180 ranges = <0 0x44240000 0xa0400>; 181 pins-are-numbered; 182 183 gpioa: gpio@44240000 { 184 gpio-controller; 185 #gpio-cells = <2>; 186 interrupt-controller; 187 #interrupt-cells = <2>; 188 reg = <0x0 0x400>; 189 clocks = <&ck_icn_ls_mcu>; 190 st,bank-name = "GPIOA"; 191 status = "disabled"; 192 }; 193 194 gpiob: gpio@44250000 { 195 gpio-controller; 196 #gpio-cells = <2>; 197 interrupt-controller; 198 #interrupt-cells = <2>; 199 reg = <0x10000 0x400>; 200 clocks = <&ck_icn_ls_mcu>; 201 st,bank-name = "GPIOB"; 202 status = "disabled"; 203 }; 204 205 gpioc: gpio@44260000 { 206 gpio-controller; 207 #gpio-cells = <2>; 208 interrupt-controller; 209 #interrupt-cells = <2>; 210 reg = <0x20000 0x400>; 211 clocks = <&ck_icn_ls_mcu>; 212 st,bank-name = "GPIOC"; 213 status = "disabled"; 214 }; 215 216 gpiod: gpio@44270000 { 217 gpio-controller; 218 #gpio-cells = <2>; 219 interrupt-controller; 220 #interrupt-cells = <2>; 221 reg = <0x30000 0x400>; 222 clocks = <&ck_icn_ls_mcu>; 223 st,bank-name = "GPIOD"; 224 status = "disabled"; 225 }; 226 227 gpioe: gpio@44280000 { 228 gpio-controller; 229 #gpio-cells = <2>; 230 interrupt-controller; 231 #interrupt-cells = <2>; 232 reg = <0x40000 0x400>; 233 clocks = <&ck_icn_ls_mcu>; 234 st,bank-name = "GPIOE"; 235 status = "disabled"; 236 }; 237 238 gpiof: gpio@44290000 { 239 gpio-controller; 240 #gpio-cells = <2>; 241 interrupt-controller; 242 #interrupt-cells = <2>; 243 reg = <0x50000 0x400>; 244 clocks = <&ck_icn_ls_mcu>; 245 st,bank-name = "GPIOF"; 246 status = "disabled"; 247 }; 248 249 gpiog: gpio@442a0000 { 250 gpio-controller; 251 #gpio-cells = <2>; 252 interrupt-controller; 253 #interrupt-cells = <2>; 254 reg = <0x60000 0x400>; 255 clocks = <&ck_icn_ls_mcu>; 256 st,bank-name = "GPIOG"; 257 status = "disabled"; 258 }; 259 260 gpioh: gpio@442b0000 { 261 gpio-controller; 262 #gpio-cells = <2>; 263 interrupt-controller; 264 #interrupt-cells = <2>; 265 reg = <0x70000 0x400>; 266 clocks = <&ck_icn_ls_mcu>; 267 st,bank-name = "GPIOH"; 268 status = "disabled"; 269 }; 270 271 gpioi: gpio@442c0000 { 272 gpio-controller; 273 #gpio-cells = <2>; 274 interrupt-controller; 275 #interrupt-cells = <2>; 276 reg = <0x80000 0x400>; 277 clocks = <&ck_icn_ls_mcu>; 278 st,bank-name = "GPIOI"; 279 status = "disabled"; 280 }; 281 282 gpioj: gpio@442d0000 { 283 gpio-controller; 284 #gpio-cells = <2>; 285 interrupt-controller; 286 #interrupt-cells = <2>; 287 reg = <0x90000 0x400>; 288 clocks = <&ck_icn_ls_mcu>; 289 st,bank-name = "GPIOJ"; 290 status = "disabled"; 291 }; 292 293 gpiok: gpio@442e0000 { 294 gpio-controller; 295 #gpio-cells = <2>; 296 interrupt-controller; 297 #interrupt-cells = <2>; 298 reg = <0xa0000 0x400>; 299 clocks = <&ck_icn_ls_mcu>; 300 st,bank-name = "GPIOK"; 301 status = "disabled"; 302 }; 303 }; 304 305 pinctrl_z: pinctrl@46200000 { 306 #address-cells = <1>; 307 #size-cells = <1>; 308 compatible = "st,stm32mp257-z-pinctrl"; 309 ranges = <0 0x46200000 0x400>; 310 pins-are-numbered; 311 312 gpioz: gpio@46200000 { 313 gpio-controller; 314 #gpio-cells = <2>; 315 interrupt-controller; 316 #interrupt-cells = <2>; 317 reg = <0 0x400>; 318 clocks = <&ck_icn_ls_mcu>; 319 st,bank-name = "GPIOZ"; 320 st,bank-ioport = <11>; 321 status = "disabled"; 322 }; 323 324 }; 325 }; 326}; 327