1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/clock/st,stm32mp25-rcc.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/reset/st,stm32mp25-rcc.h> 9#include <dt-bindings/regulator/st,stm32mp25-regulator.h> 10#include <dt-bindings/phy/phy.h> 11 12/ { 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu0: cpu@0 { 21 compatible = "arm,cortex-a35"; 22 device_type = "cpu"; 23 reg = <0>; 24 enable-method = "psci"; 25 power-domains = <&CPU_PD0>; 26 power-domain-names = "psci"; 27 }; 28 }; 29 30 arm-pmu { 31 compatible = "arm,cortex-a35-pmu"; 32 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 33 interrupt-affinity = <&cpu0>; 34 interrupt-parent = <&intc>; 35 }; 36 37 arm_wdt: watchdog { 38 compatible = "arm,smc-wdt"; 39 arm,smc-id = <0xb200005a>; 40 status = "disabled"; 41 }; 42 43 clocks { 44 clk_dsi_txbyte: txbyteclk { 45 #clock-cells = <0>; 46 compatible = "fixed-clock"; 47 clock-frequency = <0>; 48 }; 49 50 clk_rcbsec: clk-rcbsec { 51 #clock-cells = <0>; 52 compatible = "fixed-clock"; 53 clock-frequency = <64000000>; 54 }; 55 56 clk_flexgen_27_fixed: clk-54000000 { 57 #clock-cells = <0>; 58 compatible = "fixed-clock"; 59 clock-frequency = <54000000>; 60 }; 61 }; 62 63 firmware { 64 optee: optee { 65 compatible = "linaro,optee-tz"; 66 method = "smc"; 67 interrupt-parent = <&intc>; 68 interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 69 }; 70 71 scmi { 72 compatible = "linaro,scmi-optee"; 73 #address-cells = <1>; 74 #size-cells = <0>; 75 linaro,optee-channel-id = <0>; 76 77 scmi_clk: protocol@14 { 78 reg = <0x14>; 79 #clock-cells = <1>; 80 }; 81 82 scmi_reset: protocol@16 { 83 reg = <0x16>; 84 #reset-cells = <1>; 85 }; 86 87 scmi_voltd: protocol@17 { 88 reg = <0x17>; 89 90 scmi_regu: regulators { 91 #address-cells = <1>; 92 #size-cells = <0>; 93 94 scmi_vddio1: regulator@0 { 95 reg = <VOLTD_SCMI_VDDIO1>; 96 regulator-name = "vddio1"; 97 }; 98 scmi_vddio2: regulator@1 { 99 reg = <VOLTD_SCMI_VDDIO2>; 100 regulator-name = "vddio2"; 101 }; 102 scmi_vddio3: regulator@2 { 103 reg = <VOLTD_SCMI_VDDIO3>; 104 regulator-name = "vddio3"; 105 }; 106 scmi_vddio4: regulator@3 { 107 reg = <VOLTD_SCMI_VDDIO4>; 108 regulator-name = "vddio4"; 109 }; 110 scmi_vdd33ucpd: regulator@5 { 111 reg = <VOLTD_SCMI_UCPD>; 112 regulator-name = "vdd33ucpd"; 113 }; 114 scmi_vdda18adc: regulator@7 { 115 reg = <VOLTD_SCMI_ADC>; 116 regulator-name = "vdda18adc"; 117 }; 118 }; 119 }; 120 }; 121 }; 122 123 intc: interrupt-controller@4ac00000 { 124 compatible = "arm,gic-400"; 125 #interrupt-cells = <3>; 126 interrupt-controller; 127 reg = <0x0 0x4ac10000 0x0 0x1000>, 128 <0x0 0x4ac20000 0x0 0x20000>, 129 <0x0 0x4ac40000 0x0 0x20000>, 130 <0x0 0x4ac60000 0x0 0x20000>; 131 #address-cells = <2>; 132 #size-cells = <2>; 133 ranges; 134 135 v2m0: v2m@48090000 { 136 compatible = "arm,gic-v2m-frame"; 137 reg = <0x0 0x48090000 0x0 0x1000>; 138 msi-controller; 139 }; 140 }; 141 142 psci { 143 compatible = "arm,psci-1.0"; 144 method = "smc"; 145 146 CPU_PD0: power-domain-cpu0 { 147 #power-domain-cells = <0>; 148 power-domains = <&CLUSTER_PD>; 149 }; 150 151 CLUSTER_PD: power-domain-cluster { 152 #power-domain-cells = <0>; 153 power-domains = <&RET_PD>; 154 }; 155 156 RET_PD: power-domain-retention { 157 #power-domain-cells = <0>; 158 }; 159 }; 160 161 timer { 162 compatible = "arm,armv8-timer"; 163 interrupt-parent = <&intc>; 164 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 165 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 166 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 167 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 168 arm,no-tick-in-suspend; 169 }; 170 171 soc@0 { 172 compatible = "simple-bus"; 173 #address-cells = <1>; 174 #size-cells = <1>; 175 interrupt-parent = <&intc>; 176 ranges = <0x0 0x0 0x0 0x80000000>; 177 178 hpdma: dma-controller@40400000 { 179 compatible = "st,stm32mp25-dma3"; 180 reg = <0x40400000 0x1000>; 181 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 197 clocks = <&scmi_clk CK_SCMI_HPDMA1>; 198 #dma-cells = <3>; 199 }; 200 201 hpdma2: dma-controller@40410000 { 202 compatible = "st,stm32mp25-dma3"; 203 reg = <0x40410000 0x1000>; 204 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 220 clocks = <&scmi_clk CK_SCMI_HPDMA2>; 221 #dma-cells = <3>; 222 }; 223 224 hpdma3: dma-controller@40420000 { 225 compatible = "st,stm32mp25-dma3"; 226 reg = <0x40420000 0x1000>; 227 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&scmi_clk CK_SCMI_HPDMA3>; 244 #dma-cells = <3>; 245 }; 246 247 ommanager: ommanager@40500000 { 248 compatible = "st,stm32mp25-omm"; 249 reg = <0x40500000 0x400>, <0x60000000 0x10000000>; 250 reg-names = "regs", "memory_map"; 251 ranges = <0 0 0x40430000 0x400>, 252 <1 0 0x40440000 0x400>; 253 clocks = <&rcc CK_BUS_OSPIIOM>, 254 <&scmi_clk CK_SCMI_OSPI1>, 255 <&scmi_clk CK_SCMI_OSPI2>; 256 clock-names = "omm", "ospi1", "ospi2"; 257 resets = <&rcc OSPIIOM_R>, 258 <&scmi_reset RST_SCMI_OSPI1>, 259 <&scmi_reset RST_SCMI_OSPI2>; 260 reset-names = "omm", "ospi1", "ospi2"; 261 access-controllers = <&rifsc 111>; 262 power-domains = <&CLUSTER_PD>; 263 #address-cells = <2>; 264 #size-cells = <1>; 265 st,syscfg-amcr = <&syscfg 0x2c00 0x7>; 266 status = "disabled"; 267 268 ospi1: spi@0 { 269 compatible = "st,stm32mp25-ospi"; 270 reg = <0 0 0x400>; 271 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 272 dmas = <&hpdma 2 0x62 0x3121>, 273 <&hpdma 2 0x42 0x3112>; 274 dma-names = "tx", "rx"; 275 clocks = <&scmi_clk CK_SCMI_OSPI1>; 276 resets = <&scmi_reset RST_SCMI_OSPI1>, 277 <&scmi_reset RST_SCMI_OSPI1DLL>; 278 access-controllers = <&rifsc 74>; 279 power-domains = <&CLUSTER_PD>; 280 st,syscfg-dlyb = <&syscfg 0x1000>; 281 status = "disabled"; 282 }; 283 284 ospi2: spi@1 { 285 compatible = "st,stm32mp25-ospi"; 286 reg = <1 0 0x400>; 287 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 288 dmas = <&hpdma 3 0x62 0x3121>, 289 <&hpdma 3 0x42 0x3112>; 290 dma-names = "tx", "rx"; 291 clocks = <&scmi_clk CK_SCMI_OSPI2>; 292 resets = <&scmi_reset RST_SCMI_OSPI2>, 293 <&scmi_reset RST_SCMI_OSPI2DLL>; 294 access-controllers = <&rifsc 75>; 295 power-domains = <&CLUSTER_PD>; 296 st,syscfg-dlyb = <&syscfg 0x1400>; 297 status = "disabled"; 298 }; 299 }; 300 301 rifsc: bus@42080000 { 302 compatible = "st,stm32mp25-rifsc", "simple-bus"; 303 reg = <0x42080000 0x1000>; 304 #address-cells = <1>; 305 #size-cells = <1>; 306 #access-controller-cells = <1>; 307 ranges; 308 309 timers2: timer@40000000 { 310 compatible = "st,stm32mp25-timers"; 311 reg = <0x40000000 0x400>; 312 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 313 interrupt-names = "global"; 314 clocks = <&rcc CK_KER_TIM2>; 315 clock-names = "int"; 316 #address-cells = <1>; 317 #size-cells = <0>; 318 access-controllers = <&rifsc 1>; 319 power-domains = <&CLUSTER_PD>; 320 status = "disabled"; 321 322 counter { 323 compatible = "st,stm32mp25-timer-counter"; 324 status = "disabled"; 325 }; 326 327 pwm { 328 compatible = "st,stm32mp25-pwm"; 329 #pwm-cells = <3>; 330 status = "disabled"; 331 }; 332 333 timer@1 { 334 compatible = "st,stm32mp25-timer-trigger"; 335 reg = <1>; 336 status = "disabled"; 337 }; 338 }; 339 340 timers3: timer@40010000 { 341 compatible = "st,stm32mp25-timers"; 342 reg = <0x40010000 0x400>; 343 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 344 interrupt-names = "global"; 345 clocks = <&rcc CK_KER_TIM3>; 346 clock-names = "int"; 347 #address-cells = <1>; 348 #size-cells = <0>; 349 access-controllers = <&rifsc 2>; 350 power-domains = <&CLUSTER_PD>; 351 status = "disabled"; 352 353 counter { 354 compatible = "st,stm32mp25-timer-counter"; 355 status = "disabled"; 356 }; 357 358 pwm { 359 compatible = "st,stm32mp25-pwm"; 360 #pwm-cells = <3>; 361 status = "disabled"; 362 }; 363 364 timer@2 { 365 compatible = "st,stm32mp25-timer-trigger"; 366 reg = <2>; 367 status = "disabled"; 368 }; 369 }; 370 371 timers4: timer@40020000 { 372 compatible = "st,stm32mp25-timers"; 373 reg = <0x40020000 0x400>; 374 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 375 interrupt-names = "global"; 376 clocks = <&rcc CK_KER_TIM4>; 377 clock-names = "int"; 378 #address-cells = <1>; 379 #size-cells = <0>; 380 access-controllers = <&rifsc 3>; 381 power-domains = <&CLUSTER_PD>; 382 status = "disabled"; 383 384 counter { 385 compatible = "st,stm32mp25-timer-counter"; 386 status = "disabled"; 387 }; 388 389 pwm { 390 compatible = "st,stm32mp25-pwm"; 391 #pwm-cells = <3>; 392 status = "disabled"; 393 }; 394 395 timer@3 { 396 compatible = "st,stm32mp25-timer-trigger"; 397 reg = <3>; 398 status = "disabled"; 399 }; 400 }; 401 402 timers5: timer@40030000 { 403 compatible = "st,stm32mp25-timers"; 404 reg = <0x40030000 0x400>; 405 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 406 interrupt-names = "global"; 407 clocks = <&rcc CK_KER_TIM5>; 408 clock-names = "int"; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 access-controllers = <&rifsc 4>; 412 power-domains = <&CLUSTER_PD>; 413 status = "disabled"; 414 415 counter { 416 compatible = "st,stm32mp25-timer-counter"; 417 status = "disabled"; 418 }; 419 420 pwm { 421 compatible = "st,stm32mp25-pwm"; 422 #pwm-cells = <3>; 423 status = "disabled"; 424 }; 425 426 timer@4 { 427 compatible = "st,stm32mp25-timer-trigger"; 428 reg = <4>; 429 status = "disabled"; 430 }; 431 }; 432 433 timers6: timer@40040000 { 434 compatible = "st,stm32mp25-timers"; 435 reg = <0x40040000 0x400>; 436 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 437 interrupt-names = "global"; 438 clocks = <&rcc CK_KER_TIM6>; 439 clock-names = "int"; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 access-controllers = <&rifsc 5>; 443 power-domains = <&CLUSTER_PD>; 444 status = "disabled"; 445 446 counter { 447 compatible = "st,stm32mp25-timer-counter"; 448 status = "disabled"; 449 }; 450 451 timer@5 { 452 compatible = "st,stm32mp25-timer-trigger"; 453 reg = <5>; 454 status = "disabled"; 455 }; 456 }; 457 458 timers7: timer@40050000 { 459 compatible = "st,stm32mp25-timers"; 460 reg = <0x40050000 0x400>; 461 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 462 interrupt-names = "global"; 463 clocks = <&rcc CK_KER_TIM7>; 464 clock-names = "int"; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 access-controllers = <&rifsc 6>; 468 power-domains = <&CLUSTER_PD>; 469 status = "disabled"; 470 471 counter { 472 compatible = "st,stm32mp25-timer-counter"; 473 status = "disabled"; 474 }; 475 476 timer@6 { 477 compatible = "st,stm32mp25-timer-trigger"; 478 reg = <6>; 479 status = "disabled"; 480 }; 481 }; 482 483 timers12: timer@40060000 { 484 compatible = "st,stm32mp25-timers"; 485 reg = <0x40060000 0x400>; 486 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 487 interrupt-names = "global"; 488 clocks = <&rcc CK_KER_TIM12>; 489 clock-names = "int"; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 access-controllers = <&rifsc 10>; 493 power-domains = <&CLUSTER_PD>; 494 status = "disabled"; 495 496 counter { 497 compatible = "st,stm32mp25-timer-counter"; 498 status = "disabled"; 499 }; 500 501 pwm { 502 compatible = "st,stm32mp25-pwm"; 503 #pwm-cells = <3>; 504 status = "disabled"; 505 }; 506 507 timer@11 { 508 compatible = "st,stm32mp25-timer-trigger"; 509 reg = <11>; 510 status = "disabled"; 511 }; 512 }; 513 514 timers13: timer@40070000 { 515 compatible = "st,stm32mp25-timers"; 516 reg = <0x40070000 0x400>; 517 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 518 interrupt-names = "global"; 519 clocks = <&rcc CK_KER_TIM13>; 520 clock-names = "int"; 521 #address-cells = <1>; 522 #size-cells = <0>; 523 access-controllers = <&rifsc 11>; 524 power-domains = <&CLUSTER_PD>; 525 status = "disabled"; 526 527 counter { 528 compatible = "st,stm32mp25-timer-counter"; 529 status = "disabled"; 530 }; 531 532 pwm { 533 compatible = "st,stm32mp25-pwm"; 534 #pwm-cells = <3>; 535 status = "disabled"; 536 }; 537 538 timer@12 { 539 compatible = "st,stm32mp25-timer-trigger"; 540 reg = <12>; 541 status = "disabled"; 542 }; 543 }; 544 545 timers14: timer@40080000 { 546 compatible = "st,stm32mp25-timers"; 547 reg = <0x40080000 0x400>; 548 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 549 interrupt-names = "global"; 550 clocks = <&rcc CK_KER_TIM14>; 551 clock-names = "int"; 552 #address-cells = <1>; 553 #size-cells = <0>; 554 access-controllers = <&rifsc 12>; 555 power-domains = <&CLUSTER_PD>; 556 status = "disabled"; 557 558 counter { 559 compatible = "st,stm32mp25-timer-counter"; 560 status = "disabled"; 561 }; 562 563 pwm { 564 compatible = "st,stm32mp25-pwm"; 565 #pwm-cells = <3>; 566 status = "disabled"; 567 }; 568 569 timer@13 { 570 compatible = "st,stm32mp25-timer-trigger"; 571 reg = <13>; 572 status = "disabled"; 573 }; 574 }; 575 576 lptimer1: timer@40090000 { 577 compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer"; 578 reg = <0x40090000 0x400>; 579 interrupts-extended = <&exti1 47 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&rcc CK_KER_LPTIM1>; 581 clock-names = "mux"; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 access-controllers = <&rifsc 17>; 585 power-domains = <&RET_PD>; 586 wakeup-source; 587 status = "disabled"; 588 589 counter { 590 compatible = "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-counter"; 591 status = "disabled"; 592 }; 593 594 pwm { 595 compatible = "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp"; 596 #pwm-cells = <3>; 597 status = "disabled"; 598 }; 599 600 timer { 601 compatible = "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer"; 602 status = "disabled"; 603 }; 604 605 trigger@0 { 606 compatible = "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trigger"; 607 reg = <0>; 608 status = "disabled"; 609 }; 610 }; 611 612 lptimer2: timer@400a0000 { 613 compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer"; 614 reg = <0x400a0000 0x400>; 615 interrupts-extended = <&exti1 48 IRQ_TYPE_LEVEL_HIGH>; 616 clocks = <&rcc CK_KER_LPTIM2>; 617 clock-names = "mux"; 618 #address-cells = <1>; 619 #size-cells = <0>; 620 access-controllers = <&rifsc 18>; 621 power-domains = <&RET_PD>; 622 wakeup-source; 623 status = "disabled"; 624 625 counter { 626 compatible = "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-counter"; 627 status = "disabled"; 628 }; 629 630 pwm { 631 compatible = "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp"; 632 #pwm-cells = <3>; 633 status = "disabled"; 634 }; 635 636 timer { 637 compatible = "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer"; 638 status = "disabled"; 639 }; 640 641 trigger@1 { 642 compatible = "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trigger"; 643 reg = <1>; 644 status = "disabled"; 645 }; 646 }; 647 648 i2s2: audio-controller@400b0000 { 649 compatible = "st,stm32mp25-i2s"; 650 reg = <0x400b0000 0x400>; 651 #sound-dai-cells = <0>; 652 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 653 clocks = <&rcc CK_BUS_SPI2>, <&rcc CK_KER_SPI2>; 654 clock-names = "pclk", "i2sclk"; 655 resets = <&rcc SPI2_R>; 656 dmas = <&hpdma 51 0x43 0x12>, 657 <&hpdma 52 0x43 0x21>; 658 dma-names = "rx", "tx"; 659 access-controllers = <&rifsc 23>; 660 status = "disabled"; 661 }; 662 663 spi2: spi@400b0000 { 664 #address-cells = <1>; 665 #size-cells = <0>; 666 compatible = "st,stm32mp25-spi"; 667 reg = <0x400b0000 0x400>; 668 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 669 clocks = <&rcc CK_KER_SPI2>; 670 resets = <&rcc SPI2_R>; 671 dmas = <&hpdma 51 0x20 0x3012>, 672 <&hpdma 52 0x20 0x3021>; 673 dma-names = "rx", "tx"; 674 access-controllers = <&rifsc 23>; 675 status = "disabled"; 676 }; 677 678 i2s3: audio-controller@400c0000 { 679 compatible = "st,stm32mp25-i2s"; 680 reg = <0x400c0000 0x400>; 681 #sound-dai-cells = <0>; 682 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 683 clocks = <&rcc CK_BUS_SPI3>, <&rcc CK_KER_SPI3>; 684 clock-names = "pclk", "i2sclk"; 685 resets = <&rcc SPI3_R>; 686 dmas = <&hpdma 53 0x43 0x12>, 687 <&hpdma 54 0x43 0x21>; 688 dma-names = "rx", "tx"; 689 access-controllers = <&rifsc 24>; 690 status = "disabled"; 691 }; 692 693 spi3: spi@400c0000 { 694 #address-cells = <1>; 695 #size-cells = <0>; 696 compatible = "st,stm32mp25-spi"; 697 reg = <0x400c0000 0x400>; 698 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 699 clocks = <&rcc CK_KER_SPI3>; 700 resets = <&rcc SPI3_R>; 701 dmas = <&hpdma 53 0x20 0x3012>, 702 <&hpdma 54 0x20 0x3021>; 703 dma-names = "rx", "tx"; 704 access-controllers = <&rifsc 24>; 705 status = "disabled"; 706 }; 707 708 spdifrx: audio-controller@400d0000 { 709 compatible = "st,stm32h7-spdifrx"; 710 #sound-dai-cells = <0>; 711 reg = <0x400d0000 0x400>; 712 clocks = <&rcc CK_KER_SPDIFRX>; 713 clock-names = "kclk"; 714 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 715 dmas = <&hpdma 71 0x43 0x212>, 716 <&hpdma 72 0x43 0x212>; 717 dma-names = "rx", "rx-ctrl"; 718 access-controllers = <&rifsc 30>; 719 status = "disabled"; 720 }; 721 722 usart2: serial@400e0000 { 723 compatible = "st,stm32h7-uart"; 724 reg = <0x400e0000 0x400>; 725 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 726 clocks = <&rcc CK_KER_USART2>; 727 dmas = <&hpdma 11 0x20 0x10012>, 728 <&hpdma 12 0x20 0x3021>; 729 dma-names = "rx", "tx"; 730 access-controllers = <&rifsc 32>; 731 status = "disabled"; 732 }; 733 734 usart3: serial@400f0000 { 735 compatible = "st,stm32h7-uart"; 736 reg = <0x400f0000 0x400>; 737 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&rcc CK_KER_USART3>; 739 dmas = <&hpdma 13 0x20 0x10012>, 740 <&hpdma 14 0x20 0x3021>; 741 dma-names = "rx", "tx"; 742 access-controllers = <&rifsc 33>; 743 status = "disabled"; 744 }; 745 746 uart4: serial@40100000 { 747 compatible = "st,stm32h7-uart"; 748 reg = <0x40100000 0x400>; 749 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 750 clocks = <&rcc CK_KER_UART4>; 751 dmas = <&hpdma 15 0x20 0x10012>, 752 <&hpdma 16 0x20 0x3021>; 753 dma-names = "rx", "tx"; 754 access-controllers = <&rifsc 34>; 755 status = "disabled"; 756 }; 757 758 uart5: serial@40110000 { 759 compatible = "st,stm32h7-uart"; 760 reg = <0x40110000 0x400>; 761 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 762 clocks = <&rcc CK_KER_UART5>; 763 dmas = <&hpdma 17 0x20 0x10012>, 764 <&hpdma 18 0x20 0x3021>; 765 dma-names = "rx", "tx"; 766 access-controllers = <&rifsc 35>; 767 status = "disabled"; 768 }; 769 770 i2c1: i2c@40120000 { 771 compatible = "st,stm32mp25-i2c"; 772 reg = <0x40120000 0x400>; 773 interrupt-names = "event"; 774 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 775 clocks = <&rcc CK_KER_I2C1>; 776 resets = <&rcc I2C1_R>; 777 #address-cells = <1>; 778 #size-cells = <0>; 779 dmas = <&hpdma 27 0x20 0x3012>, 780 <&hpdma 28 0x20 0x3021>; 781 dma-names = "rx", "tx"; 782 access-controllers = <&rifsc 41>; 783 status = "disabled"; 784 }; 785 786 i2c2: i2c@40130000 { 787 compatible = "st,stm32mp25-i2c"; 788 reg = <0x40130000 0x400>; 789 interrupt-names = "event"; 790 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 791 clocks = <&rcc CK_KER_I2C2>; 792 resets = <&rcc I2C2_R>; 793 #address-cells = <1>; 794 #size-cells = <0>; 795 dmas = <&hpdma 30 0x20 0x3012>, 796 <&hpdma 31 0x20 0x3021>; 797 dma-names = "rx", "tx"; 798 access-controllers = <&rifsc 42>; 799 status = "disabled"; 800 }; 801 802 i2c3: i2c@40140000 { 803 compatible = "st,stm32mp25-i2c"; 804 reg = <0x40140000 0x400>; 805 interrupt-names = "event"; 806 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 807 clocks = <&rcc CK_KER_I2C3>; 808 resets = <&rcc I2C3_R>; 809 #address-cells = <1>; 810 #size-cells = <0>; 811 dmas = <&hpdma 33 0x20 0x3012>, 812 <&hpdma 34 0x20 0x3021>; 813 dma-names = "rx", "tx"; 814 access-controllers = <&rifsc 43>; 815 status = "disabled"; 816 }; 817 818 i2c4: i2c@40150000 { 819 compatible = "st,stm32mp25-i2c"; 820 reg = <0x40150000 0x400>; 821 interrupt-names = "event"; 822 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 823 clocks = <&rcc CK_KER_I2C4>; 824 resets = <&rcc I2C4_R>; 825 #address-cells = <1>; 826 #size-cells = <0>; 827 dmas = <&hpdma 36 0x20 0x3012>, 828 <&hpdma 37 0x20 0x3021>; 829 dma-names = "rx", "tx"; 830 access-controllers = <&rifsc 44>; 831 status = "disabled"; 832 }; 833 834 i2c5: i2c@40160000 { 835 compatible = "st,stm32mp25-i2c"; 836 reg = <0x40160000 0x400>; 837 interrupt-names = "event"; 838 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 839 clocks = <&rcc CK_KER_I2C5>; 840 resets = <&rcc I2C5_R>; 841 #address-cells = <1>; 842 #size-cells = <0>; 843 dmas = <&hpdma 39 0x20 0x3012>, 844 <&hpdma 40 0x20 0x3021>; 845 dma-names = "rx", "tx"; 846 access-controllers = <&rifsc 45>; 847 status = "disabled"; 848 }; 849 850 i2c6: i2c@40170000 { 851 compatible = "st,stm32mp25-i2c"; 852 reg = <0x40170000 0x400>; 853 interrupt-names = "event"; 854 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 855 clocks = <&rcc CK_KER_I2C6>; 856 resets = <&rcc I2C6_R>; 857 #address-cells = <1>; 858 #size-cells = <0>; 859 dmas = <&hpdma 42 0x20 0x3012>, 860 <&hpdma 43 0x20 0x3021>; 861 dma-names = "rx", "tx"; 862 access-controllers = <&rifsc 46>; 863 status = "disabled"; 864 }; 865 866 i2c7: i2c@40180000 { 867 compatible = "st,stm32mp25-i2c"; 868 reg = <0x40180000 0x400>; 869 interrupt-names = "event"; 870 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; 871 clocks = <&rcc CK_KER_I2C7>; 872 resets = <&rcc I2C7_R>; 873 #address-cells = <1>; 874 #size-cells = <0>; 875 dmas = <&hpdma 45 0x20 0x3012>, 876 <&hpdma 46 0x20 0x3021>; 877 dma-names = "rx", "tx"; 878 access-controllers = <&rifsc 47>; 879 status = "disabled"; 880 }; 881 882 timers10: timer@401c0000 { 883 compatible = "st,stm32mp25-timers"; 884 reg = <0x401c0000 0x400>; 885 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 886 interrupt-names = "global"; 887 clocks = <&rcc CK_KER_TIM10>; 888 clock-names = "int"; 889 #address-cells = <1>; 890 #size-cells = <0>; 891 access-controllers = <&rifsc 8>; 892 power-domains = <&CLUSTER_PD>; 893 status = "disabled"; 894 895 counter { 896 compatible = "st,stm32mp25-timer-counter"; 897 status = "disabled"; 898 }; 899 900 pwm { 901 compatible = "st,stm32mp25-pwm"; 902 #pwm-cells = <3>; 903 status = "disabled"; 904 }; 905 906 timer@9 { 907 compatible = "st,stm32mp25-timer-trigger"; 908 reg = <9>; 909 status = "disabled"; 910 }; 911 }; 912 913 timers11: timer@401d0000 { 914 compatible = "st,stm32mp25-timers"; 915 reg = <0x401d0000 0x400>; 916 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 917 interrupt-names = "global"; 918 clocks = <&rcc CK_KER_TIM11>; 919 clock-names = "int"; 920 #address-cells = <1>; 921 #size-cells = <0>; 922 access-controllers = <&rifsc 9>; 923 power-domains = <&CLUSTER_PD>; 924 status = "disabled"; 925 926 counter { 927 compatible = "st,stm32mp25-timer-counter"; 928 status = "disabled"; 929 }; 930 931 pwm { 932 compatible = "st,stm32mp25-pwm"; 933 #pwm-cells = <3>; 934 status = "disabled"; 935 }; 936 937 timer@10 { 938 compatible = "st,stm32mp25-timer-trigger"; 939 reg = <10>; 940 status = "disabled"; 941 }; 942 }; 943 944 timers1: timer@40200000 { 945 compatible = "st,stm32mp25-timers"; 946 reg = <0x40200000 0x400>; 947 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 951 interrupt-names = "brk", "up", "trg-com", "cc"; 952 clocks = <&rcc CK_KER_TIM1>; 953 clock-names = "int"; 954 #address-cells = <1>; 955 #size-cells = <0>; 956 access-controllers = <&rifsc 0>; 957 power-domains = <&CLUSTER_PD>; 958 status = "disabled"; 959 960 counter { 961 compatible = "st,stm32mp25-timer-counter"; 962 status = "disabled"; 963 }; 964 965 pwm { 966 compatible = "st,stm32mp25-pwm"; 967 #pwm-cells = <3>; 968 status = "disabled"; 969 }; 970 971 timer@0 { 972 compatible = "st,stm32mp25-timer-trigger"; 973 reg = <0>; 974 status = "disabled"; 975 }; 976 }; 977 978 timers8: timer@40210000 { 979 compatible = "st,stm32mp25-timers"; 980 reg = <0x40210000 0x400>; 981 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 982 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 983 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 984 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 985 interrupt-names = "brk", "up", "trg-com", "cc"; 986 clocks = <&rcc CK_KER_TIM8>; 987 clock-names = "int"; 988 #address-cells = <1>; 989 #size-cells = <0>; 990 access-controllers = <&rifsc 7>; 991 power-domains = <&CLUSTER_PD>; 992 status = "disabled"; 993 994 counter { 995 compatible = "st,stm32mp25-timer-counter"; 996 status = "disabled"; 997 }; 998 999 pwm { 1000 compatible = "st,stm32mp25-pwm"; 1001 #pwm-cells = <3>; 1002 status = "disabled"; 1003 }; 1004 1005 timer@7 { 1006 compatible = "st,stm32mp25-timer-trigger"; 1007 reg = <7>; 1008 status = "disabled"; 1009 }; 1010 }; 1011 1012 usart6: serial@40220000 { 1013 compatible = "st,stm32h7-uart"; 1014 reg = <0x40220000 0x400>; 1015 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1016 clocks = <&rcc CK_KER_USART6>; 1017 dmas = <&hpdma 19 0x20 0x10012>, 1018 <&hpdma 20 0x20 0x3021>; 1019 dma-names = "rx", "tx"; 1020 access-controllers = <&rifsc 36>; 1021 status = "disabled"; 1022 }; 1023 1024 i2s1: audio-controller@40230000 { 1025 compatible = "st,stm32mp25-i2s"; 1026 reg = <0x40230000 0x400>; 1027 #sound-dai-cells = <0>; 1028 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1029 clocks = <&rcc CK_BUS_SPI1>, <&rcc CK_KER_SPI1>; 1030 clock-names = "pclk", "i2sclk"; 1031 resets = <&rcc SPI1_R>; 1032 dmas = <&hpdma 49 0x43 0x12>, 1033 <&hpdma 50 0x43 0x21>; 1034 dma-names = "rx", "tx"; 1035 access-controllers = <&rifsc 22>; 1036 status = "disabled"; 1037 }; 1038 1039 spi1: spi@40230000 { 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 compatible = "st,stm32mp25-spi"; 1043 reg = <0x40230000 0x400>; 1044 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1045 clocks = <&rcc CK_KER_SPI1>; 1046 resets = <&rcc SPI1_R>; 1047 dmas = <&hpdma 49 0x20 0x3012>, 1048 <&hpdma 50 0x20 0x3021>; 1049 dma-names = "rx", "tx"; 1050 access-controllers = <&rifsc 22>; 1051 status = "disabled"; 1052 }; 1053 1054 spi4: spi@40240000 { 1055 #address-cells = <1>; 1056 #size-cells = <0>; 1057 compatible = "st,stm32mp25-spi"; 1058 reg = <0x40240000 0x400>; 1059 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1060 clocks = <&rcc CK_KER_SPI4>; 1061 resets = <&rcc SPI4_R>; 1062 dmas = <&hpdma 55 0x20 0x3012>, 1063 <&hpdma 56 0x20 0x3021>; 1064 dma-names = "rx", "tx"; 1065 access-controllers = <&rifsc 25>; 1066 status = "disabled"; 1067 }; 1068 1069 timers15: timer@40250000 { 1070 compatible = "st,stm32mp25-timers"; 1071 reg = <0x40250000 0x400>; 1072 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 1073 interrupt-names = "global"; 1074 clocks = <&rcc CK_KER_TIM15>; 1075 clock-names = "int"; 1076 #address-cells = <1>; 1077 #size-cells = <0>; 1078 access-controllers = <&rifsc 13>; 1079 power-domains = <&CLUSTER_PD>; 1080 status = "disabled"; 1081 1082 counter { 1083 compatible = "st,stm32mp25-timer-counter"; 1084 status = "disabled"; 1085 }; 1086 1087 pwm { 1088 compatible = "st,stm32mp25-pwm"; 1089 #pwm-cells = <3>; 1090 status = "disabled"; 1091 }; 1092 1093 timer@14 { 1094 compatible = "st,stm32mp25-timer-trigger"; 1095 reg = <14>; 1096 status = "disabled"; 1097 }; 1098 }; 1099 1100 timers16: timer@40260000 { 1101 compatible = "st,stm32mp25-timers"; 1102 reg = <0x40260000 0x400>; 1103 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 1104 interrupt-names = "global"; 1105 clocks = <&rcc CK_KER_TIM16>; 1106 clock-names = "int"; 1107 #address-cells = <1>; 1108 #size-cells = <0>; 1109 access-controllers = <&rifsc 14>; 1110 power-domains = <&CLUSTER_PD>; 1111 status = "disabled"; 1112 1113 counter { 1114 compatible = "st,stm32mp25-timer-counter"; 1115 status = "disabled"; 1116 }; 1117 1118 pwm { 1119 compatible = "st,stm32mp25-pwm"; 1120 #pwm-cells = <3>; 1121 status = "disabled"; 1122 }; 1123 1124 timer@15 { 1125 compatible = "st,stm32mp25-timer-trigger"; 1126 reg = <15>; 1127 status = "disabled"; 1128 }; 1129 }; 1130 1131 timers17: timer@40270000 { 1132 compatible = "st,stm32mp25-timers"; 1133 reg = <0x40270000 0x400>; 1134 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 1135 interrupt-names = "global"; 1136 clocks = <&rcc CK_KER_TIM17>; 1137 clock-names = "int"; 1138 #address-cells = <1>; 1139 #size-cells = <0>; 1140 access-controllers = <&rifsc 15>; 1141 power-domains = <&CLUSTER_PD>; 1142 status = "disabled"; 1143 1144 counter { 1145 compatible = "st,stm32mp25-timer-counter"; 1146 status = "disabled"; 1147 }; 1148 1149 pwm { 1150 compatible = "st,stm32mp25-pwm"; 1151 #pwm-cells = <3>; 1152 status = "disabled"; 1153 }; 1154 1155 timer@16 { 1156 compatible = "st,stm32mp25-timer-trigger"; 1157 reg = <16>; 1158 status = "disabled"; 1159 }; 1160 }; 1161 1162 spi5: spi@40280000 { 1163 #address-cells = <1>; 1164 #size-cells = <0>; 1165 compatible = "st,stm32mp25-spi"; 1166 reg = <0x40280000 0x400>; 1167 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1168 clocks = <&rcc CK_KER_SPI5>; 1169 resets = <&rcc SPI5_R>; 1170 dmas = <&hpdma 57 0x20 0x3012>, 1171 <&hpdma 58 0x20 0x3021>; 1172 dma-names = "rx", "tx"; 1173 access-controllers = <&rifsc 26>; 1174 status = "disabled"; 1175 }; 1176 1177 sai1: sai@40290000 { 1178 compatible = "st,stm32mp25-sai"; 1179 reg = <0x40290000 0x4>, <0x4029a3f0 0x10>; 1180 ranges = <0 0x40290000 0x400>; 1181 #address-cells = <1>; 1182 #size-cells = <1>; 1183 clocks = <&rcc CK_BUS_SAI1>; 1184 clock-names = "pclk"; 1185 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1186 resets = <&rcc SAI1_R>; 1187 access-controllers = <&rifsc 49>; 1188 status = "disabled"; 1189 1190 sai1a: audio-controller@40290004 { 1191 compatible = "st,stm32-sai-sub-a"; 1192 reg = <0x4 0x20>; 1193 #sound-dai-cells = <0>; 1194 clocks = <&rcc CK_KER_SAI1>; 1195 clock-names = "sai_ck"; 1196 dmas = <&hpdma 73 0x43 0x21>; 1197 status = "disabled"; 1198 }; 1199 1200 sai1b: audio-controller@40290024 { 1201 compatible = "st,stm32-sai-sub-b"; 1202 reg = <0x24 0x20>; 1203 #sound-dai-cells = <0>; 1204 clocks = <&rcc CK_KER_SAI1>; 1205 clock-names = "sai_ck"; 1206 dmas = <&hpdma 74 0x43 0x12>; 1207 status = "disabled"; 1208 }; 1209 }; 1210 1211 sai2: sai@402a0000 { 1212 compatible = "st,stm32mp25-sai"; 1213 reg = <0x402a0000 0x4>, <0x402aa3f0 0x10>; 1214 ranges = <0 0x402a0000 0x400>; 1215 #address-cells = <1>; 1216 #size-cells = <1>; 1217 clocks = <&rcc CK_BUS_SAI2>; 1218 clock-names = "pclk"; 1219 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1220 resets = <&rcc SAI2_R>; 1221 access-controllers = <&rifsc 50>; 1222 status = "disabled"; 1223 1224 sai2a: audio-controller@402a0004 { 1225 compatible = "st,stm32-sai-sub-a"; 1226 reg = <0x4 0x20>; 1227 #sound-dai-cells = <0>; 1228 clocks = <&rcc CK_KER_SAI2>; 1229 clock-names = "sai_ck"; 1230 dmas = <&hpdma 75 0x43 0x21>; 1231 status = "disabled"; 1232 }; 1233 1234 sai2b: audio-controller@402a0024 { 1235 compatible = "st,stm32-sai-sub-b"; 1236 reg = <0x24 0x20>; 1237 #sound-dai-cells = <0>; 1238 clocks = <&rcc CK_KER_SAI2>; 1239 clock-names = "sai_ck"; 1240 dmas = <&hpdma 76 0x43 0x12>; 1241 status = "disabled"; 1242 }; 1243 }; 1244 1245 sai3: sai@402b0000 { 1246 compatible = "st,stm32mp25-sai"; 1247 reg = <0x402b0000 0x4>, <0x402ba3f0 0x10>; 1248 ranges = <0 0x402b0000 0x400>; 1249 #address-cells = <1>; 1250 #size-cells = <1>; 1251 clocks = <&rcc CK_BUS_SAI3>; 1252 clock-names = "pclk"; 1253 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 1254 resets = <&rcc SAI3_R>; 1255 access-controllers = <&rifsc 51>; 1256 status = "disabled"; 1257 1258 sai3a: audio-controller@402b0004 { 1259 compatible = "st,stm32-sai-sub-a"; 1260 reg = <0x4 0x20>; 1261 #sound-dai-cells = <0>; 1262 clocks = <&rcc CK_KER_SAI3>; 1263 clock-names = "sai_ck"; 1264 dmas = <&hpdma 77 0x43 0x21>; 1265 status = "disabled"; 1266 }; 1267 1268 sai3b: audio-controller@502b0024 { 1269 compatible = "st,stm32-sai-sub-b"; 1270 reg = <0x24 0x20>; 1271 #sound-dai-cells = <0>; 1272 clocks = <&rcc CK_KER_SAI3>; 1273 clock-names = "sai_ck"; 1274 dmas = <&hpdma 78 0x43 0x12>; 1275 status = "disabled"; 1276 }; 1277 }; 1278 1279 uart9: serial@402c0000 { 1280 compatible = "st,stm32h7-uart"; 1281 reg = <0x402c0000 0x400>; 1282 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1283 clocks = <&rcc CK_KER_UART9>; 1284 dmas = <&hpdma 25 0x20 0x10012>, 1285 <&hpdma 26 0x20 0x3021>; 1286 dma-names = "rx", "tx"; 1287 access-controllers = <&rifsc 39>; 1288 status = "disabled"; 1289 }; 1290 1291 timers20: timer@40320000 { 1292 compatible = "st,stm32mp25-timers"; 1293 reg = <0x40320000 0x400>; 1294 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1295 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1296 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1298 interrupt-names = "brk", "up", "trg-com", "cc"; 1299 clocks = <&rcc CK_KER_TIM20>; 1300 clock-names = "int"; 1301 #address-cells = <1>; 1302 #size-cells = <0>; 1303 access-controllers = <&rifsc 16>; 1304 power-domains = <&CLUSTER_PD>; 1305 status = "disabled"; 1306 1307 counter { 1308 compatible = "st,stm32mp25-timer-counter"; 1309 status = "disabled"; 1310 }; 1311 1312 pwm { 1313 compatible = "st,stm32mp25-pwm"; 1314 #pwm-cells = <3>; 1315 status = "disabled"; 1316 }; 1317 1318 timer@19 { 1319 compatible = "st,stm32mp25-timer-trigger"; 1320 reg = <19>; 1321 status = "disabled"; 1322 }; 1323 }; 1324 1325 usart1: serial@40330000 { 1326 compatible = "st,stm32h7-uart"; 1327 reg = <0x40330000 0x400>; 1328 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1329 clocks = <&rcc CK_KER_USART1>; 1330 dmas = <&hpdma 9 0x20 0x10012>, 1331 <&hpdma 10 0x20 0x3021>; 1332 dma-names = "rx", "tx"; 1333 access-controllers = <&rifsc 31>; 1334 status = "disabled"; 1335 }; 1336 1337 sai4: sai@40340000 { 1338 compatible = "st,stm32mp25-sai"; 1339 reg = <0x40340000 0x4>, <0x4034a3f0 0x10>; 1340 ranges = <0 0x40340000 0x400>; 1341 #address-cells = <1>; 1342 #size-cells = <1>; 1343 clocks = <&rcc CK_BUS_SAI4>; 1344 clock-names = "pclk"; 1345 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1346 resets = <&rcc SAI4_R>; 1347 access-controllers = <&rifsc 52>; 1348 status = "disabled"; 1349 1350 sai4a: audio-controller@40340004 { 1351 compatible = "st,stm32-sai-sub-a"; 1352 reg = <0x4 0x20>; 1353 #sound-dai-cells = <0>; 1354 clocks = <&rcc CK_KER_SAI4>; 1355 clock-names = "sai_ck"; 1356 dmas = <&hpdma 79 0x63 0x21>; 1357 status = "disabled"; 1358 }; 1359 1360 sai4b: audio-controller@40340024 { 1361 compatible = "st,stm32-sai-sub-b"; 1362 reg = <0x24 0x20>; 1363 #sound-dai-cells = <0>; 1364 clocks = <&rcc CK_KER_SAI4>; 1365 clock-names = "sai_ck"; 1366 dmas = <&hpdma 80 0x43 0x12>; 1367 status = "disabled"; 1368 }; 1369 }; 1370 1371 spi6: spi@40350000 { 1372 #address-cells = <1>; 1373 #size-cells = <0>; 1374 compatible = "st,stm32mp25-spi"; 1375 reg = <0x40350000 0x400>; 1376 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1377 clocks = <&rcc CK_KER_SPI6>; 1378 resets = <&rcc SPI6_R>; 1379 dmas = <&hpdma 59 0x20 0x3012>, 1380 <&hpdma 60 0x20 0x3021>; 1381 dma-names = "rx", "tx"; 1382 access-controllers = <&rifsc 27>; 1383 status = "disabled"; 1384 }; 1385 1386 spi7: spi@40360000 { 1387 #address-cells = <1>; 1388 #size-cells = <0>; 1389 compatible = "st,stm32mp25-spi"; 1390 reg = <0x40360000 0x400>; 1391 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1392 clocks = <&rcc CK_KER_SPI7>; 1393 resets = <&rcc SPI7_R>; 1394 dmas = <&hpdma 61 0x20 0x3012>, 1395 <&hpdma 62 0x20 0x3021>; 1396 dma-names = "rx", "tx"; 1397 access-controllers = <&rifsc 28>; 1398 status = "disabled"; 1399 }; 1400 1401 uart7: serial@40370000 { 1402 compatible = "st,stm32h7-uart"; 1403 reg = <0x40370000 0x400>; 1404 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1405 clocks = <&rcc CK_KER_UART7>; 1406 dmas = <&hpdma 21 0x20 0x10012>, 1407 <&hpdma 22 0x20 0x3021>; 1408 dma-names = "rx", "tx"; 1409 access-controllers = <&rifsc 37>; 1410 status = "disabled"; 1411 }; 1412 1413 uart8: serial@40380000 { 1414 compatible = "st,stm32h7-uart"; 1415 reg = <0x40380000 0x400>; 1416 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 1417 clocks = <&rcc CK_KER_UART8>; 1418 dmas = <&hpdma 23 0x20 0x10012>, 1419 <&hpdma 24 0x20 0x3021>; 1420 dma-names = "rx", "tx"; 1421 access-controllers = <&rifsc 38>; 1422 status = "disabled"; 1423 }; 1424 1425 rng: rng@42020000 { 1426 compatible = "st,stm32mp25-rng"; 1427 reg = <0x42020000 0x400>; 1428 clocks = <&clk_rcbsec>, <&rcc CK_BUS_RNG>; 1429 clock-names = "core", "bus"; 1430 resets = <&rcc RNG_R>; 1431 access-controllers = <&rifsc 92>; 1432 status = "disabled"; 1433 }; 1434 1435 spi8: spi@46020000 { 1436 #address-cells = <1>; 1437 #size-cells = <0>; 1438 compatible = "st,stm32mp25-spi"; 1439 reg = <0x46020000 0x400>; 1440 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1441 clocks = <&rcc CK_KER_SPI8>; 1442 resets = <&rcc SPI8_R>; 1443 dmas = <&hpdma 171 0x20 0x3012>, 1444 <&hpdma 172 0x20 0x3021>; 1445 dma-names = "rx", "tx"; 1446 access-controllers = <&rifsc 29>; 1447 status = "disabled"; 1448 }; 1449 1450 i2c8: i2c@46040000 { 1451 compatible = "st,stm32mp25-i2c"; 1452 reg = <0x46040000 0x400>; 1453 interrupt-names = "event"; 1454 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 1455 clocks = <&rcc CK_KER_I2C8>; 1456 resets = <&rcc I2C8_R>; 1457 #address-cells = <1>; 1458 #size-cells = <0>; 1459 dmas = <&hpdma 168 0x20 0x3012>, 1460 <&hpdma 169 0x20 0x3021>; 1461 dma-names = "rx", "tx"; 1462 access-controllers = <&rifsc 48>; 1463 status = "disabled"; 1464 }; 1465 1466 lptimer3: timer@46050000 { 1467 compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer"; 1468 reg = <0x46050000 0x400>; 1469 interrupts-extended = <&exti2 29 IRQ_TYPE_LEVEL_HIGH>; 1470 clocks = <&rcc CK_KER_LPTIM3>; 1471 clock-names = "mux"; 1472 #address-cells = <1>; 1473 #size-cells = <0>; 1474 access-controllers = <&rifsc 19>; 1475 wakeup-source; 1476 status = "disabled"; 1477 1478 counter { 1479 compatible = "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-counter"; 1480 status = "disabled"; 1481 }; 1482 1483 pwm { 1484 compatible = "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp"; 1485 #pwm-cells = <3>; 1486 status = "disabled"; 1487 }; 1488 1489 timer { 1490 compatible = "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer"; 1491 status = "disabled"; 1492 }; 1493 1494 trigger@2 { 1495 compatible = "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trigger"; 1496 reg = <2>; 1497 status = "disabled"; 1498 }; 1499 }; 1500 1501 lptimer4: timer@46060000 { 1502 compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer"; 1503 reg = <0x46060000 0x400>; 1504 interrupts-extended = <&exti2 30 IRQ_TYPE_LEVEL_HIGH>; 1505 clocks = <&rcc CK_KER_LPTIM4>; 1506 clock-names = "mux"; 1507 #address-cells = <1>; 1508 #size-cells = <0>; 1509 access-controllers = <&rifsc 20>; 1510 wakeup-source; 1511 status = "disabled"; 1512 1513 counter { 1514 compatible = "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-counter"; 1515 status = "disabled"; 1516 }; 1517 1518 pwm { 1519 compatible = "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp"; 1520 #pwm-cells = <3>; 1521 status = "disabled"; 1522 }; 1523 1524 timer { 1525 compatible = "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer"; 1526 status = "disabled"; 1527 }; 1528 1529 trigger@3 { 1530 compatible = "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trigger"; 1531 reg = <3>; 1532 status = "disabled"; 1533 }; 1534 }; 1535 1536 lptimer5: timer@46070000 { 1537 compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer"; 1538 reg = <0x46070000 0x400>; 1539 interrupts-extended = <&exti2 31 IRQ_TYPE_LEVEL_HIGH>; 1540 clocks = <&rcc CK_KER_LPTIM5>; 1541 clock-names = "mux"; 1542 #address-cells = <1>; 1543 #size-cells = <0>; 1544 access-controllers = <&rifsc 21>; 1545 wakeup-source; 1546 status = "disabled"; 1547 1548 counter { 1549 compatible = "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-counter"; 1550 status = "disabled"; 1551 }; 1552 1553 pwm { 1554 compatible = "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp"; 1555 #pwm-cells = <3>; 1556 status = "disabled"; 1557 }; 1558 1559 timer { 1560 compatible = "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer"; 1561 status = "disabled"; 1562 }; 1563 1564 trigger@4 { 1565 compatible = "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trigger"; 1566 reg = <4>; 1567 status = "disabled"; 1568 }; 1569 }; 1570 1571 ltdc: display-controller@48010000 { 1572 compatible = "st,stm32mp251-ltdc"; 1573 reg = <0x48010000 0x400>; 1574 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1575 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1576 clocks = <&rcc CK_KER_LTDC>, <&rcc CK_BUS_LTDC>; 1577 clock-names = "lcd", "bus"; 1578 resets = <&rcc LTDC_R>; 1579 access-controllers = <&rifsc 80>; 1580 status = "disabled"; 1581 }; 1582 1583 csi: csi@48020000 { 1584 compatible = "st,stm32mp25-csi"; 1585 reg = <0x48020000 0x2000>; 1586 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 1587 resets = <&rcc CSI_R>; 1588 clocks = <&rcc CK_KER_CSI>, <&rcc CK_KER_CSITXESC>, 1589 <&rcc CK_KER_CSIPHY>; 1590 clock-names = "pclk", "txesc", "csi2phy"; 1591 access-controllers = <&rifsc 86>; 1592 status = "disabled"; 1593 }; 1594 1595 dcmipp: dcmipp@48030000 { 1596 compatible = "st,stm32mp25-dcmipp"; 1597 reg = <0x48030000 0x1000>; 1598 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 1599 resets = <&rcc DCMIPP_R>; 1600 clocks = <&rcc CK_BUS_DCMIPP>, <&rcc CK_KER_CSI>; 1601 clock-names = "kclk", "mclk"; 1602 access-controllers = <&rifsc 87>; 1603 status = "disabled"; 1604 }; 1605 1606 combophy: phy@480c0000 { 1607 compatible = "st,stm32mp25-combophy"; 1608 reg = <0x480c0000 0x1000>; 1609 #phy-cells = <1>; 1610 clocks = <&rcc CK_BUS_USB3PCIEPHY>, <&rcc CK_KER_USB3PCIEPHY>; 1611 clock-names = "apb", "ker"; 1612 resets = <&rcc USB3PCIEPHY_R>; 1613 reset-names = "phy"; 1614 access-controllers = <&rifsc 67>; 1615 power-domains = <&CLUSTER_PD>; 1616 wakeup-source; 1617 interrupts-extended = <&exti1 45 IRQ_TYPE_EDGE_FALLING>; 1618 status = "disabled"; 1619 }; 1620 1621 sdmmc1: mmc@48220000 { 1622 compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; 1623 arm,primecell-periphid = <0x00353180>; 1624 reg = <0x48220000 0x400>, <0x44230400 0x8>; 1625 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1626 clocks = <&rcc CK_KER_SDMMC1 >; 1627 clock-names = "apb_pclk"; 1628 resets = <&rcc SDMMC1_R>; 1629 cap-sd-highspeed; 1630 cap-mmc-highspeed; 1631 max-frequency = <120000000>; 1632 access-controllers = <&rifsc 76>; 1633 status = "disabled"; 1634 }; 1635 1636 ethernet1: ethernet@482c0000 { 1637 compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20"; 1638 reg = <0x482c0000 0x4000>; 1639 reg-names = "stmmaceth"; 1640 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 1641 interrupt-names = "macirq"; 1642 clock-names = "stmmaceth", 1643 "mac-clk-tx", 1644 "mac-clk-rx", 1645 "ptp_ref", 1646 "ethstp", 1647 "eth-ck"; 1648 clocks = <&rcc CK_ETH1_MAC>, 1649 <&rcc CK_ETH1_TX>, 1650 <&rcc CK_ETH1_RX>, 1651 <&rcc CK_KER_ETH1PTP>, 1652 <&rcc CK_ETH1_STP>, 1653 <&rcc CK_KER_ETH1>; 1654 snps,axi-config = <&stmmac_axi_config_1>; 1655 snps,mixed-burst; 1656 snps,mtl-rx-config = <&mtl_rx_setup_1>; 1657 snps,mtl-tx-config = <&mtl_tx_setup_1>; 1658 snps,pbl = <2>; 1659 snps,tso; 1660 st,syscon = <&syscfg 0x3000>; 1661 access-controllers = <&rifsc 60>; 1662 status = "disabled"; 1663 1664 mtl_rx_setup_1: rx-queues-config { 1665 snps,rx-queues-to-use = <2>; 1666 queue0 {}; 1667 queue1 {}; 1668 }; 1669 1670 mtl_tx_setup_1: tx-queues-config { 1671 snps,tx-queues-to-use = <4>; 1672 queue0 {}; 1673 queue1 {}; 1674 queue2 {}; 1675 queue3 {}; 1676 }; 1677 1678 stmmac_axi_config_1: stmmac-axi-config { 1679 snps,blen = <0 0 0 0 16 8 4>; 1680 snps,rd_osr_lmt = <0x7>; 1681 snps,wr_osr_lmt = <0x7>; 1682 }; 1683 }; 1684 1685 pcie_ep: pcie-ep@48400000 { 1686 compatible = "st,stm32mp25-pcie-ep"; 1687 reg = <0x48400000 0x100000>, 1688 <0x48500000 0x100000>, 1689 <0x48700000 0x80000>, 1690 <0x10000000 0x10000000>; 1691 reg-names = "dbi", "dbi2", "atu", "addr_space"; 1692 clocks = <&rcc CK_BUS_PCIE>; 1693 resets = <&rcc PCIE_R>; 1694 phys = <&combophy PHY_TYPE_PCIE>; 1695 access-controllers = <&rifsc 68>; 1696 power-domains = <&CLUSTER_PD>; 1697 status = "disabled"; 1698 }; 1699 1700 pcie_rc: pcie@48400000 { 1701 compatible = "st,stm32mp25-pcie-rc"; 1702 device_type = "pci"; 1703 reg = <0x48400000 0x400000>, 1704 <0x10000000 0x10000>; 1705 reg-names = "dbi", "config"; 1706 #interrupt-cells = <1>; 1707 interrupt-map-mask = <0 0 0 7>; 1708 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 1709 <0 0 0 2 &intc 0 0 GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1710 <0 0 0 3 &intc 0 0 GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 1711 <0 0 0 4 &intc 0 0 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 1712 #address-cells = <3>; 1713 #size-cells = <2>; 1714 ranges = <0x01000000 0x0 0x00000000 0x10010000 0x0 0x10000>, 1715 <0x02000000 0x0 0x10020000 0x10020000 0x0 0x7fe0000>, 1716 <0x42000000 0x0 0x18000000 0x18000000 0x0 0x8000000>; 1717 dma-ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x80000000>; 1718 clocks = <&rcc CK_BUS_PCIE>; 1719 resets = <&rcc PCIE_R>; 1720 msi-parent = <&v2m0>; 1721 access-controllers = <&rifsc 68>; 1722 power-domains = <&CLUSTER_PD>; 1723 status = "disabled"; 1724 1725 pcie@0,0 { 1726 device_type = "pci"; 1727 reg = <0x0 0x0 0x0 0x0 0x0>; 1728 phys = <&combophy PHY_TYPE_PCIE>; 1729 #address-cells = <3>; 1730 #size-cells = <2>; 1731 ranges; 1732 }; 1733 }; 1734 }; 1735 1736 bsec: efuse@44000000 { 1737 compatible = "st,stm32mp25-bsec"; 1738 reg = <0x44000000 0x1000>; 1739 #address-cells = <1>; 1740 #size-cells = <1>; 1741 1742 part_number_otp@24 { 1743 reg = <0x24 0x4>; 1744 }; 1745 1746 package_otp@1e8 { 1747 reg = <0x1e8 0x1>; 1748 bits = <0 3>; 1749 }; 1750 }; 1751 1752 hdp: pinctrl@44090000 { 1753 compatible = "st,stm32mp251-hdp"; 1754 reg = <0x44090000 0x400>; 1755 clocks = <&rcc CK_BUS_HDP>; 1756 status = "disabled"; 1757 }; 1758 1759 rcc: clock-controller@44200000 { 1760 compatible = "st,stm32mp25-rcc"; 1761 reg = <0x44200000 0x10000>; 1762 #clock-cells = <1>; 1763 #reset-cells = <1>; 1764 clocks = <&scmi_clk CK_SCMI_HSE>, 1765 <&scmi_clk CK_SCMI_HSI>, 1766 <&scmi_clk CK_SCMI_MSI>, 1767 <&scmi_clk CK_SCMI_LSE>, 1768 <&scmi_clk CK_SCMI_LSI>, 1769 <&scmi_clk CK_SCMI_HSE_DIV2>, 1770 <&scmi_clk CK_SCMI_ICN_HS_MCU>, 1771 <&scmi_clk CK_SCMI_ICN_LS_MCU>, 1772 <&scmi_clk CK_SCMI_ICN_SDMMC>, 1773 <&scmi_clk CK_SCMI_ICN_DDR>, 1774 <&scmi_clk CK_SCMI_ICN_DISPLAY>, 1775 <&scmi_clk CK_SCMI_ICN_HSL>, 1776 <&scmi_clk CK_SCMI_ICN_NIC>, 1777 <&scmi_clk CK_SCMI_ICN_VID>, 1778 <&scmi_clk CK_SCMI_FLEXGEN_07>, 1779 <&scmi_clk CK_SCMI_FLEXGEN_08>, 1780 <&scmi_clk CK_SCMI_FLEXGEN_09>, 1781 <&scmi_clk CK_SCMI_FLEXGEN_10>, 1782 <&scmi_clk CK_SCMI_FLEXGEN_11>, 1783 <&scmi_clk CK_SCMI_FLEXGEN_12>, 1784 <&scmi_clk CK_SCMI_FLEXGEN_13>, 1785 <&scmi_clk CK_SCMI_FLEXGEN_14>, 1786 <&scmi_clk CK_SCMI_FLEXGEN_15>, 1787 <&scmi_clk CK_SCMI_FLEXGEN_16>, 1788 <&scmi_clk CK_SCMI_FLEXGEN_17>, 1789 <&scmi_clk CK_SCMI_FLEXGEN_18>, 1790 <&scmi_clk CK_SCMI_FLEXGEN_19>, 1791 <&scmi_clk CK_SCMI_FLEXGEN_20>, 1792 <&scmi_clk CK_SCMI_FLEXGEN_21>, 1793 <&scmi_clk CK_SCMI_FLEXGEN_22>, 1794 <&scmi_clk CK_SCMI_FLEXGEN_23>, 1795 <&scmi_clk CK_SCMI_FLEXGEN_24>, 1796 <&scmi_clk CK_SCMI_FLEXGEN_25>, 1797 <&scmi_clk CK_SCMI_FLEXGEN_26>, 1798 <&scmi_clk CK_SCMI_FLEXGEN_27>, 1799 <&scmi_clk CK_SCMI_FLEXGEN_28>, 1800 <&scmi_clk CK_SCMI_FLEXGEN_29>, 1801 <&scmi_clk CK_SCMI_FLEXGEN_30>, 1802 <&scmi_clk CK_SCMI_FLEXGEN_31>, 1803 <&scmi_clk CK_SCMI_FLEXGEN_32>, 1804 <&scmi_clk CK_SCMI_FLEXGEN_33>, 1805 <&scmi_clk CK_SCMI_FLEXGEN_34>, 1806 <&scmi_clk CK_SCMI_FLEXGEN_35>, 1807 <&scmi_clk CK_SCMI_FLEXGEN_36>, 1808 <&scmi_clk CK_SCMI_FLEXGEN_37>, 1809 <&scmi_clk CK_SCMI_FLEXGEN_38>, 1810 <&scmi_clk CK_SCMI_FLEXGEN_39>, 1811 <&scmi_clk CK_SCMI_FLEXGEN_40>, 1812 <&scmi_clk CK_SCMI_FLEXGEN_41>, 1813 <&scmi_clk CK_SCMI_FLEXGEN_42>, 1814 <&scmi_clk CK_SCMI_FLEXGEN_43>, 1815 <&scmi_clk CK_SCMI_FLEXGEN_44>, 1816 <&scmi_clk CK_SCMI_FLEXGEN_45>, 1817 <&scmi_clk CK_SCMI_FLEXGEN_46>, 1818 <&scmi_clk CK_SCMI_FLEXGEN_47>, 1819 <&scmi_clk CK_SCMI_FLEXGEN_48>, 1820 <&scmi_clk CK_SCMI_FLEXGEN_49>, 1821 <&scmi_clk CK_SCMI_FLEXGEN_50>, 1822 <&scmi_clk CK_SCMI_FLEXGEN_51>, 1823 <&scmi_clk CK_SCMI_FLEXGEN_52>, 1824 <&scmi_clk CK_SCMI_FLEXGEN_53>, 1825 <&scmi_clk CK_SCMI_FLEXGEN_54>, 1826 <&scmi_clk CK_SCMI_FLEXGEN_55>, 1827 <&scmi_clk CK_SCMI_FLEXGEN_56>, 1828 <&scmi_clk CK_SCMI_FLEXGEN_57>, 1829 <&scmi_clk CK_SCMI_FLEXGEN_58>, 1830 <&scmi_clk CK_SCMI_FLEXGEN_59>, 1831 <&scmi_clk CK_SCMI_FLEXGEN_60>, 1832 <&scmi_clk CK_SCMI_FLEXGEN_61>, 1833 <&scmi_clk CK_SCMI_FLEXGEN_62>, 1834 <&scmi_clk CK_SCMI_FLEXGEN_63>, 1835 <&scmi_clk CK_SCMI_ICN_APB1>, 1836 <&scmi_clk CK_SCMI_ICN_APB2>, 1837 <&scmi_clk CK_SCMI_ICN_APB3>, 1838 <&scmi_clk CK_SCMI_ICN_APB4>, 1839 <&scmi_clk CK_SCMI_ICN_APBDBG>, 1840 <&scmi_clk CK_SCMI_TIMG1>, 1841 <&scmi_clk CK_SCMI_TIMG2>, 1842 <&scmi_clk CK_SCMI_PLL3>, 1843 <&clk_dsi_txbyte>; 1844 access-controllers = <&rifsc 156>; 1845 }; 1846 1847 exti1: interrupt-controller@44220000 { 1848 compatible = "st,stm32mp1-exti", "syscon"; 1849 interrupt-controller; 1850 #interrupt-cells = <2>; 1851 reg = <0x44220000 0x400>; 1852 interrupts-extended = 1853 <&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 1854 <&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 1855 <&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 1856 <&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 1857 <&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 1858 <&intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 1859 <&intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 1860 <&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 1861 <&intc GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 1862 <&intc GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 1863 <&intc GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 1864 <&intc GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1865 <&intc GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1866 <&intc GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1867 <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1868 <&intc GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1869 <&intc GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 1870 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 1871 <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1872 <&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1873 <0>, /* EXTI_20 */ 1874 <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1875 <&intc GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1876 <&intc GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1877 <&intc GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1878 <&intc GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1879 <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1880 <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1881 <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1882 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1883 <&intc GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 1884 <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1885 <&intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1886 <&intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1887 <&intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1888 <0>, 1889 <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1890 <&intc GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1891 <&intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1892 <&intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 1893 <&intc GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 1894 <&intc GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 1895 <&intc GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1896 <&intc GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1897 <&intc GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1898 <&intc GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 1899 <&intc GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1900 <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 1901 <&intc GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 1902 <&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1903 <&intc GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 1904 <0>, 1905 <0>, 1906 <0>, 1907 <0>, 1908 <0>, 1909 <0>, 1910 <0>, 1911 <0>, 1912 <&intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1913 <0>, /* EXTI_60 */ 1914 <&intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1915 <0>, 1916 <0>, 1917 <&intc GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1918 <0>, 1919 <0>, 1920 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1921 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1922 <0>, 1923 <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ 1924 <0>, 1925 <&intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 1926 <&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 1927 <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1928 <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1929 <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 1930 <&intc GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1931 <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1932 <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1933 <0>, /* EXTI_80 */ 1934 <0>, 1935 <0>, 1936 <&intc GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 1937 <&intc GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 1938 }; 1939 1940 syscfg: syscon@44230000 { 1941 compatible = "st,stm32mp25-syscfg", "syscon"; 1942 reg = <0x44230000 0x10000>; 1943 #clock-cells = <0>; 1944 }; 1945 1946 pinctrl: pinctrl@44240000 { 1947 #address-cells = <1>; 1948 #size-cells = <1>; 1949 compatible = "st,stm32mp257-pinctrl"; 1950 ranges = <0 0x44240000 0xa0400>; 1951 interrupt-parent = <&exti1>; 1952 st,syscfg = <&exti1 0x60 0xff>; 1953 pins-are-numbered; 1954 1955 gpioa: gpio@44240000 { 1956 gpio-controller; 1957 #gpio-cells = <2>; 1958 interrupt-controller; 1959 #interrupt-cells = <2>; 1960 reg = <0x0 0x400>; 1961 clocks = <&scmi_clk CK_SCMI_GPIOA>; 1962 st,bank-name = "GPIOA"; 1963 status = "disabled"; 1964 }; 1965 1966 gpiob: gpio@44250000 { 1967 gpio-controller; 1968 #gpio-cells = <2>; 1969 interrupt-controller; 1970 #interrupt-cells = <2>; 1971 reg = <0x10000 0x400>; 1972 clocks = <&scmi_clk CK_SCMI_GPIOB>; 1973 st,bank-name = "GPIOB"; 1974 status = "disabled"; 1975 }; 1976 1977 gpioc: gpio@44260000 { 1978 gpio-controller; 1979 #gpio-cells = <2>; 1980 interrupt-controller; 1981 #interrupt-cells = <2>; 1982 reg = <0x20000 0x400>; 1983 clocks = <&scmi_clk CK_SCMI_GPIOC>; 1984 st,bank-name = "GPIOC"; 1985 status = "disabled"; 1986 }; 1987 1988 gpiod: gpio@44270000 { 1989 gpio-controller; 1990 #gpio-cells = <2>; 1991 interrupt-controller; 1992 #interrupt-cells = <2>; 1993 reg = <0x30000 0x400>; 1994 clocks = <&scmi_clk CK_SCMI_GPIOD>; 1995 st,bank-name = "GPIOD"; 1996 status = "disabled"; 1997 }; 1998 1999 gpioe: gpio@44280000 { 2000 gpio-controller; 2001 #gpio-cells = <2>; 2002 interrupt-controller; 2003 #interrupt-cells = <2>; 2004 reg = <0x40000 0x400>; 2005 clocks = <&scmi_clk CK_SCMI_GPIOE>; 2006 st,bank-name = "GPIOE"; 2007 status = "disabled"; 2008 }; 2009 2010 gpiof: gpio@44290000 { 2011 gpio-controller; 2012 #gpio-cells = <2>; 2013 interrupt-controller; 2014 #interrupt-cells = <2>; 2015 reg = <0x50000 0x400>; 2016 clocks = <&scmi_clk CK_SCMI_GPIOF>; 2017 st,bank-name = "GPIOF"; 2018 status = "disabled"; 2019 }; 2020 2021 gpiog: gpio@442a0000 { 2022 gpio-controller; 2023 #gpio-cells = <2>; 2024 interrupt-controller; 2025 #interrupt-cells = <2>; 2026 reg = <0x60000 0x400>; 2027 clocks = <&scmi_clk CK_SCMI_GPIOG>; 2028 st,bank-name = "GPIOG"; 2029 status = "disabled"; 2030 }; 2031 2032 gpioh: gpio@442b0000 { 2033 gpio-controller; 2034 #gpio-cells = <2>; 2035 interrupt-controller; 2036 #interrupt-cells = <2>; 2037 reg = <0x70000 0x400>; 2038 clocks = <&scmi_clk CK_SCMI_GPIOH>; 2039 st,bank-name = "GPIOH"; 2040 status = "disabled"; 2041 }; 2042 2043 gpioi: gpio@442c0000 { 2044 gpio-controller; 2045 #gpio-cells = <2>; 2046 interrupt-controller; 2047 #interrupt-cells = <2>; 2048 reg = <0x80000 0x400>; 2049 clocks = <&scmi_clk CK_SCMI_GPIOI>; 2050 st,bank-name = "GPIOI"; 2051 status = "disabled"; 2052 }; 2053 2054 gpioj: gpio@442d0000 { 2055 gpio-controller; 2056 #gpio-cells = <2>; 2057 interrupt-controller; 2058 #interrupt-cells = <2>; 2059 reg = <0x90000 0x400>; 2060 clocks = <&scmi_clk CK_SCMI_GPIOJ>; 2061 st,bank-name = "GPIOJ"; 2062 status = "disabled"; 2063 }; 2064 2065 gpiok: gpio@442e0000 { 2066 gpio-controller; 2067 #gpio-cells = <2>; 2068 interrupt-controller; 2069 #interrupt-cells = <2>; 2070 reg = <0xa0000 0x400>; 2071 clocks = <&scmi_clk CK_SCMI_GPIOK>; 2072 st,bank-name = "GPIOK"; 2073 status = "disabled"; 2074 }; 2075 }; 2076 2077 rtc: rtc@46000000 { 2078 compatible = "st,stm32mp25-rtc"; 2079 reg = <0x46000000 0x400>; 2080 clocks = <&scmi_clk CK_SCMI_RTC>, 2081 <&scmi_clk CK_SCMI_RTCCK>; 2082 clock-names = "pclk", "rtc_ck"; 2083 interrupts-extended = <&exti2 17 IRQ_TYPE_LEVEL_HIGH>; 2084 status = "disabled"; 2085 }; 2086 2087 pinctrl_z: pinctrl@46200000 { 2088 #address-cells = <1>; 2089 #size-cells = <1>; 2090 compatible = "st,stm32mp257-z-pinctrl"; 2091 ranges = <0 0x46200000 0x400>; 2092 interrupt-parent = <&exti1>; 2093 st,syscfg = <&exti1 0x60 0xff>; 2094 pins-are-numbered; 2095 2096 gpioz: gpio@46200000 { 2097 gpio-controller; 2098 #gpio-cells = <2>; 2099 interrupt-controller; 2100 #interrupt-cells = <2>; 2101 reg = <0 0x400>; 2102 clocks = <&scmi_clk CK_SCMI_GPIOZ>; 2103 st,bank-name = "GPIOZ"; 2104 st,bank-ioport = <11>; 2105 status = "disabled"; 2106 }; 2107 }; 2108 2109 exti2: interrupt-controller@46230000 { 2110 compatible = "st,stm32mp1-exti", "syscon"; 2111 interrupt-controller; 2112 #interrupt-cells = <2>; 2113 reg = <0x46230000 0x400>; 2114 interrupts-extended = 2115 <&intc GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 2116 <&intc GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 2117 <&intc GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 2118 <&intc GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 2119 <&intc GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 2120 <&intc GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 2121 <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 2122 <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 2123 <&intc GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 2124 <&intc GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 2125 <&intc GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 2126 <&intc GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 2127 <&intc GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 2128 <&intc GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 2129 <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 2130 <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 2131 <&intc GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 2132 <&intc GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 2133 <0>, 2134 <0>, 2135 <0>, /* EXTI_20 */ 2136 <&intc GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 2137 <&intc GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 2138 <0>, 2139 <0>, 2140 <&intc GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 2141 <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 2142 <&intc GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 2143 <0>, 2144 <&intc GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 2145 <&intc GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 2146 <&intc GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 2147 <0>, 2148 <&intc GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2149 <&intc GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 2150 <0>, 2151 <0>, 2152 <&intc GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 2153 <0>, 2154 <0>, 2155 <&intc GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 2156 <0>, 2157 <0>, 2158 <&intc GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 2159 <0>, 2160 <0>, 2161 <&intc GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 2162 <0>, 2163 <&intc GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 2164 <&intc GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2165 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 2166 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 2167 <&intc GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 2168 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2169 <0>, 2170 <0>, 2171 <0>, 2172 <0>, 2173 <0>, 2174 <0>, 2175 <0>, /* EXTI_60 */ 2176 <&intc GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 2177 <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 2178 <0>, 2179 <&intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 2180 <&intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 2181 <&intc GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 2182 <&intc GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2183 <0>, 2184 <0>, 2185 <&intc GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ 2186 }; 2187 }; 2188}; 2189