1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7 8/ { 9 #address-cells = <2>; 10 #size-cells = <2>; 11 12 cpus { 13 #address-cells = <1>; 14 #size-cells = <0>; 15 16 cpu0: cpu@0 { 17 compatible = "arm,cortex-a35"; 18 device_type = "cpu"; 19 reg = <0>; 20 enable-method = "psci"; 21 }; 22 }; 23 24 arm-pmu { 25 compatible = "arm,cortex-a35-pmu"; 26 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 27 interrupt-affinity = <&cpu0>; 28 interrupt-parent = <&intc>; 29 }; 30 31 clocks { 32 ck_flexgen_08: ck-flexgen-08 { 33 #clock-cells = <0>; 34 compatible = "fixed-clock"; 35 clock-frequency = <100000000>; 36 }; 37 38 ck_flexgen_51: ck-flexgen-51 { 39 #clock-cells = <0>; 40 compatible = "fixed-clock"; 41 clock-frequency = <200000000>; 42 }; 43 44 ck_icn_ls_mcu: ck-icn-ls-mcu { 45 #clock-cells = <0>; 46 compatible = "fixed-clock"; 47 clock-frequency = <200000000>; 48 }; 49 }; 50 51 firmware { 52 optee { 53 compatible = "linaro,optee-tz"; 54 method = "smc"; 55 }; 56 57 scmi { 58 compatible = "linaro,scmi-optee"; 59 #address-cells = <1>; 60 #size-cells = <0>; 61 linaro,optee-channel-id = <0>; 62 63 scmi_clk: protocol@14 { 64 reg = <0x14>; 65 #clock-cells = <1>; 66 }; 67 68 scmi_reset: protocol@16 { 69 reg = <0x16>; 70 #reset-cells = <1>; 71 }; 72 }; 73 }; 74 75 intc: interrupt-controller@4ac00000 { 76 compatible = "arm,cortex-a7-gic"; 77 #interrupt-cells = <3>; 78 #address-cells = <1>; 79 interrupt-controller; 80 reg = <0x0 0x4ac10000 0x0 0x1000>, 81 <0x0 0x4ac20000 0x0 0x2000>, 82 <0x0 0x4ac40000 0x0 0x2000>, 83 <0x0 0x4ac60000 0x0 0x2000>; 84 }; 85 86 psci { 87 compatible = "arm,psci-1.0"; 88 method = "smc"; 89 }; 90 91 timer { 92 compatible = "arm,armv8-timer"; 93 interrupt-parent = <&intc>; 94 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 95 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 96 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 97 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 98 always-on; 99 }; 100 101 soc@0 { 102 compatible = "simple-bus"; 103 #address-cells = <1>; 104 #size-cells = <1>; 105 interrupt-parent = <&intc>; 106 ranges = <0x0 0x0 0x0 0x80000000>; 107 108 rifsc: rifsc-bus@42080000 { 109 compatible = "simple-bus"; 110 reg = <0x42080000 0x1000>; 111 #address-cells = <1>; 112 #size-cells = <1>; 113 ranges; 114 115 usart2: serial@400e0000 { 116 compatible = "st,stm32h7-uart"; 117 reg = <0x400e0000 0x400>; 118 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 119 clocks = <&ck_flexgen_08>; 120 status = "disabled"; 121 }; 122 }; 123 124 syscfg: syscon@44230000 { 125 compatible = "st,stm32mp25-syscfg", "syscon"; 126 reg = <0x44230000 0x10000>; 127 }; 128 129 pinctrl: pinctrl@44240000 { 130 #address-cells = <1>; 131 #size-cells = <1>; 132 compatible = "st,stm32mp257-pinctrl"; 133 ranges = <0 0x44240000 0xa0400>; 134 pins-are-numbered; 135 136 gpioa: gpio@44240000 { 137 gpio-controller; 138 #gpio-cells = <2>; 139 interrupt-controller; 140 #interrupt-cells = <2>; 141 reg = <0x0 0x400>; 142 clocks = <&ck_icn_ls_mcu>; 143 st,bank-name = "GPIOA"; 144 status = "disabled"; 145 }; 146 147 gpiob: gpio@44250000 { 148 gpio-controller; 149 #gpio-cells = <2>; 150 interrupt-controller; 151 #interrupt-cells = <2>; 152 reg = <0x10000 0x400>; 153 clocks = <&ck_icn_ls_mcu>; 154 st,bank-name = "GPIOB"; 155 status = "disabled"; 156 }; 157 158 gpioc: gpio@44260000 { 159 gpio-controller; 160 #gpio-cells = <2>; 161 interrupt-controller; 162 #interrupt-cells = <2>; 163 reg = <0x20000 0x400>; 164 clocks = <&ck_icn_ls_mcu>; 165 st,bank-name = "GPIOC"; 166 status = "disabled"; 167 }; 168 169 gpiod: gpio@44270000 { 170 gpio-controller; 171 #gpio-cells = <2>; 172 interrupt-controller; 173 #interrupt-cells = <2>; 174 reg = <0x30000 0x400>; 175 clocks = <&ck_icn_ls_mcu>; 176 st,bank-name = "GPIOD"; 177 status = "disabled"; 178 }; 179 180 gpioe: gpio@44280000 { 181 gpio-controller; 182 #gpio-cells = <2>; 183 interrupt-controller; 184 #interrupt-cells = <2>; 185 reg = <0x40000 0x400>; 186 clocks = <&ck_icn_ls_mcu>; 187 st,bank-name = "GPIOE"; 188 status = "disabled"; 189 }; 190 191 gpiof: gpio@44290000 { 192 gpio-controller; 193 #gpio-cells = <2>; 194 interrupt-controller; 195 #interrupt-cells = <2>; 196 reg = <0x50000 0x400>; 197 clocks = <&ck_icn_ls_mcu>; 198 st,bank-name = "GPIOF"; 199 status = "disabled"; 200 }; 201 202 gpiog: gpio@442a0000 { 203 gpio-controller; 204 #gpio-cells = <2>; 205 interrupt-controller; 206 #interrupt-cells = <2>; 207 reg = <0x60000 0x400>; 208 clocks = <&ck_icn_ls_mcu>; 209 st,bank-name = "GPIOG"; 210 status = "disabled"; 211 }; 212 213 gpioh: gpio@442b0000 { 214 gpio-controller; 215 #gpio-cells = <2>; 216 interrupt-controller; 217 #interrupt-cells = <2>; 218 reg = <0x70000 0x400>; 219 clocks = <&ck_icn_ls_mcu>; 220 st,bank-name = "GPIOH"; 221 status = "disabled"; 222 }; 223 224 gpioi: gpio@442c0000 { 225 gpio-controller; 226 #gpio-cells = <2>; 227 interrupt-controller; 228 #interrupt-cells = <2>; 229 reg = <0x80000 0x400>; 230 clocks = <&ck_icn_ls_mcu>; 231 st,bank-name = "GPIOI"; 232 status = "disabled"; 233 }; 234 235 gpioj: gpio@442d0000 { 236 gpio-controller; 237 #gpio-cells = <2>; 238 interrupt-controller; 239 #interrupt-cells = <2>; 240 reg = <0x90000 0x400>; 241 clocks = <&ck_icn_ls_mcu>; 242 st,bank-name = "GPIOJ"; 243 status = "disabled"; 244 }; 245 246 gpiok: gpio@442e0000 { 247 gpio-controller; 248 #gpio-cells = <2>; 249 interrupt-controller; 250 #interrupt-cells = <2>; 251 reg = <0xa0000 0x400>; 252 clocks = <&ck_icn_ls_mcu>; 253 st,bank-name = "GPIOK"; 254 status = "disabled"; 255 }; 256 }; 257 258 pinctrl_z: pinctrl@46200000 { 259 #address-cells = <1>; 260 #size-cells = <1>; 261 compatible = "st,stm32mp257-z-pinctrl"; 262 ranges = <0 0x46200000 0x400>; 263 pins-are-numbered; 264 265 gpioz: gpio@46200000 { 266 gpio-controller; 267 #gpio-cells = <2>; 268 interrupt-controller; 269 #interrupt-cells = <2>; 270 reg = <0 0x400>; 271 clocks = <&ck_icn_ls_mcu>; 272 st,bank-name = "GPIOZ"; 273 st,bank-ioport = <11>; 274 status = "disabled"; 275 }; 276 277 }; 278 }; 279}; 280