1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/clock/st,stm32mp25-rcc.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/reset/st,stm32mp25-rcc.h> 9#include <dt-bindings/regulator/st,stm32mp25-regulator.h> 10#include <dt-bindings/phy/phy.h> 11 12/ { 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu0: cpu@0 { 21 compatible = "arm,cortex-a35"; 22 device_type = "cpu"; 23 reg = <0>; 24 enable-method = "psci"; 25 power-domains = <&CPU_PD0>; 26 power-domain-names = "psci"; 27 }; 28 }; 29 30 arm-pmu { 31 compatible = "arm,cortex-a35-pmu"; 32 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 33 interrupt-affinity = <&cpu0>; 34 interrupt-parent = <&intc>; 35 }; 36 37 arm_wdt: watchdog { 38 compatible = "arm,smc-wdt"; 39 arm,smc-id = <0xb200005a>; 40 status = "disabled"; 41 }; 42 43 clocks { 44 clk_dsi_txbyte: txbyteclk { 45 #clock-cells = <0>; 46 compatible = "fixed-clock"; 47 clock-frequency = <0>; 48 }; 49 50 clk_rcbsec: clk-rcbsec { 51 #clock-cells = <0>; 52 compatible = "fixed-clock"; 53 clock-frequency = <64000000>; 54 }; 55 }; 56 57 firmware { 58 optee: optee { 59 compatible = "linaro,optee-tz"; 60 method = "smc"; 61 interrupt-parent = <&intc>; 62 interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 63 }; 64 65 scmi { 66 compatible = "linaro,scmi-optee"; 67 #address-cells = <1>; 68 #size-cells = <0>; 69 linaro,optee-channel-id = <0>; 70 71 scmi_clk: protocol@14 { 72 reg = <0x14>; 73 #clock-cells = <1>; 74 }; 75 76 scmi_reset: protocol@16 { 77 reg = <0x16>; 78 #reset-cells = <1>; 79 }; 80 81 scmi_voltd: protocol@17 { 82 reg = <0x17>; 83 84 scmi_regu: regulators { 85 #address-cells = <1>; 86 #size-cells = <0>; 87 88 scmi_vddio1: regulator@0 { 89 reg = <VOLTD_SCMI_VDDIO1>; 90 regulator-name = "vddio1"; 91 }; 92 scmi_vddio2: regulator@1 { 93 reg = <VOLTD_SCMI_VDDIO2>; 94 regulator-name = "vddio2"; 95 }; 96 scmi_vddio3: regulator@2 { 97 reg = <VOLTD_SCMI_VDDIO3>; 98 regulator-name = "vddio3"; 99 }; 100 scmi_vddio4: regulator@3 { 101 reg = <VOLTD_SCMI_VDDIO4>; 102 regulator-name = "vddio4"; 103 }; 104 scmi_vdd33ucpd: regulator@5 { 105 reg = <VOLTD_SCMI_UCPD>; 106 regulator-name = "vdd33ucpd"; 107 }; 108 scmi_vdda18adc: regulator@7 { 109 reg = <VOLTD_SCMI_ADC>; 110 regulator-name = "vdda18adc"; 111 }; 112 }; 113 }; 114 }; 115 }; 116 117 intc: interrupt-controller@4ac00000 { 118 compatible = "arm,gic-400"; 119 #interrupt-cells = <3>; 120 interrupt-controller; 121 reg = <0x0 0x4ac10000 0x0 0x1000>, 122 <0x0 0x4ac20000 0x0 0x20000>, 123 <0x0 0x4ac40000 0x0 0x20000>, 124 <0x0 0x4ac60000 0x0 0x20000>; 125 }; 126 127 psci { 128 compatible = "arm,psci-1.0"; 129 method = "smc"; 130 131 CPU_PD0: power-domain-cpu0 { 132 #power-domain-cells = <0>; 133 power-domains = <&CLUSTER_PD>; 134 }; 135 136 CLUSTER_PD: power-domain-cluster { 137 #power-domain-cells = <0>; 138 power-domains = <&RET_PD>; 139 }; 140 141 RET_PD: power-domain-retention { 142 #power-domain-cells = <0>; 143 }; 144 }; 145 146 timer { 147 compatible = "arm,armv8-timer"; 148 interrupt-parent = <&intc>; 149 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 150 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 151 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 152 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 153 always-on; 154 }; 155 156 soc@0 { 157 compatible = "simple-bus"; 158 #address-cells = <1>; 159 #size-cells = <1>; 160 interrupt-parent = <&intc>; 161 ranges = <0x0 0x0 0x0 0x80000000>; 162 163 hpdma: dma-controller@40400000 { 164 compatible = "st,stm32mp25-dma3"; 165 reg = <0x40400000 0x1000>; 166 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 182 clocks = <&scmi_clk CK_SCMI_HPDMA1>; 183 #dma-cells = <3>; 184 }; 185 186 hpdma2: dma-controller@40410000 { 187 compatible = "st,stm32mp25-dma3"; 188 reg = <0x40410000 0x1000>; 189 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&scmi_clk CK_SCMI_HPDMA2>; 206 #dma-cells = <3>; 207 }; 208 209 hpdma3: dma-controller@40420000 { 210 compatible = "st,stm32mp25-dma3"; 211 reg = <0x40420000 0x1000>; 212 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&scmi_clk CK_SCMI_HPDMA3>; 229 #dma-cells = <3>; 230 }; 231 232 ommanager: ommanager@40500000 { 233 compatible = "st,stm32mp25-omm"; 234 reg = <0x40500000 0x400>, <0x60000000 0x10000000>; 235 reg-names = "regs", "memory_map"; 236 ranges = <0 0 0x40430000 0x400>, 237 <1 0 0x40440000 0x400>; 238 clocks = <&rcc CK_BUS_OSPIIOM>, 239 <&scmi_clk CK_SCMI_OSPI1>, 240 <&scmi_clk CK_SCMI_OSPI2>; 241 clock-names = "omm", "ospi1", "ospi2"; 242 resets = <&rcc OSPIIOM_R>, 243 <&scmi_reset RST_SCMI_OSPI1>, 244 <&scmi_reset RST_SCMI_OSPI2>; 245 reset-names = "omm", "ospi1", "ospi2"; 246 access-controllers = <&rifsc 111>; 247 power-domains = <&CLUSTER_PD>; 248 #address-cells = <2>; 249 #size-cells = <1>; 250 st,syscfg-amcr = <&syscfg 0x2c00 0x7>; 251 status = "disabled"; 252 253 ospi1: spi@0 { 254 compatible = "st,stm32mp25-ospi"; 255 reg = <0 0 0x400>; 256 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 257 dmas = <&hpdma 2 0x62 0x3121>, 258 <&hpdma 2 0x42 0x3112>; 259 dma-names = "tx", "rx"; 260 clocks = <&scmi_clk CK_SCMI_OSPI1>; 261 resets = <&scmi_reset RST_SCMI_OSPI1>, 262 <&scmi_reset RST_SCMI_OSPI1DLL>; 263 access-controllers = <&rifsc 74>; 264 power-domains = <&CLUSTER_PD>; 265 st,syscfg-dlyb = <&syscfg 0x1000>; 266 status = "disabled"; 267 }; 268 269 ospi2: spi@1 { 270 compatible = "st,stm32mp25-ospi"; 271 reg = <1 0 0x400>; 272 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 273 dmas = <&hpdma 3 0x62 0x3121>, 274 <&hpdma 3 0x42 0x3112>; 275 dma-names = "tx", "rx"; 276 clocks = <&scmi_clk CK_SCMI_OSPI2>; 277 resets = <&scmi_reset RST_SCMI_OSPI2>, 278 <&scmi_reset RST_SCMI_OSPI2DLL>; 279 access-controllers = <&rifsc 75>; 280 power-domains = <&CLUSTER_PD>; 281 st,syscfg-dlyb = <&syscfg 0x1400>; 282 status = "disabled"; 283 }; 284 }; 285 286 rifsc: bus@42080000 { 287 compatible = "st,stm32mp25-rifsc", "simple-bus"; 288 reg = <0x42080000 0x1000>; 289 #address-cells = <1>; 290 #size-cells = <1>; 291 #access-controller-cells = <1>; 292 ranges; 293 294 lptimer1: timer@40090000 { 295 compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer"; 296 reg = <0x40090000 0x400>; 297 interrupts-extended = <&exti1 47 IRQ_TYPE_LEVEL_HIGH>; 298 clocks = <&rcc CK_KER_LPTIM1>; 299 clock-names = "mux"; 300 #address-cells = <1>; 301 #size-cells = <0>; 302 access-controllers = <&rifsc 17>; 303 power-domains = <&RET_PD>; 304 wakeup-source; 305 status = "disabled"; 306 307 counter { 308 compatible = "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-counter"; 309 status = "disabled"; 310 }; 311 312 pwm { 313 compatible = "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp"; 314 #pwm-cells = <3>; 315 status = "disabled"; 316 }; 317 318 timer { 319 compatible = "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer"; 320 status = "disabled"; 321 }; 322 323 trigger@0 { 324 compatible = "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trigger"; 325 reg = <0>; 326 status = "disabled"; 327 }; 328 }; 329 330 lptimer2: timer@400a0000 { 331 compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer"; 332 reg = <0x400a0000 0x400>; 333 interrupts-extended = <&exti1 48 IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&rcc CK_KER_LPTIM2>; 335 clock-names = "mux"; 336 #address-cells = <1>; 337 #size-cells = <0>; 338 access-controllers = <&rifsc 18>; 339 power-domains = <&RET_PD>; 340 wakeup-source; 341 status = "disabled"; 342 343 counter { 344 compatible = "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-counter"; 345 status = "disabled"; 346 }; 347 348 pwm { 349 compatible = "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp"; 350 #pwm-cells = <3>; 351 status = "disabled"; 352 }; 353 354 timer { 355 compatible = "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer"; 356 status = "disabled"; 357 }; 358 359 trigger@1 { 360 compatible = "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trigger"; 361 reg = <1>; 362 status = "disabled"; 363 }; 364 }; 365 366 i2s2: audio-controller@400b0000 { 367 compatible = "st,stm32mp25-i2s"; 368 reg = <0x400b0000 0x400>; 369 #sound-dai-cells = <0>; 370 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&rcc CK_BUS_SPI2>, <&rcc CK_KER_SPI2>; 372 clock-names = "pclk", "i2sclk"; 373 resets = <&rcc SPI2_R>; 374 dmas = <&hpdma 51 0x43 0x12>, 375 <&hpdma 52 0x43 0x21>; 376 dma-names = "rx", "tx"; 377 access-controllers = <&rifsc 23>; 378 status = "disabled"; 379 }; 380 381 spi2: spi@400b0000 { 382 #address-cells = <1>; 383 #size-cells = <0>; 384 compatible = "st,stm32mp25-spi"; 385 reg = <0x400b0000 0x400>; 386 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&rcc CK_KER_SPI2>; 388 resets = <&rcc SPI2_R>; 389 dmas = <&hpdma 51 0x20 0x3012>, 390 <&hpdma 52 0x20 0x3021>; 391 dma-names = "rx", "tx"; 392 access-controllers = <&rifsc 23>; 393 status = "disabled"; 394 }; 395 396 i2s3: audio-controller@400c0000 { 397 compatible = "st,stm32mp25-i2s"; 398 reg = <0x400c0000 0x400>; 399 #sound-dai-cells = <0>; 400 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&rcc CK_BUS_SPI3>, <&rcc CK_KER_SPI3>; 402 clock-names = "pclk", "i2sclk"; 403 resets = <&rcc SPI3_R>; 404 dmas = <&hpdma 53 0x43 0x12>, 405 <&hpdma 54 0x43 0x21>; 406 dma-names = "rx", "tx"; 407 access-controllers = <&rifsc 24>; 408 status = "disabled"; 409 }; 410 411 spi3: spi@400c0000 { 412 #address-cells = <1>; 413 #size-cells = <0>; 414 compatible = "st,stm32mp25-spi"; 415 reg = <0x400c0000 0x400>; 416 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 417 clocks = <&rcc CK_KER_SPI3>; 418 resets = <&rcc SPI3_R>; 419 dmas = <&hpdma 53 0x20 0x3012>, 420 <&hpdma 54 0x20 0x3021>; 421 dma-names = "rx", "tx"; 422 access-controllers = <&rifsc 24>; 423 status = "disabled"; 424 }; 425 426 spdifrx: audio-controller@400d0000 { 427 compatible = "st,stm32h7-spdifrx"; 428 #sound-dai-cells = <0>; 429 reg = <0x400d0000 0x400>; 430 clocks = <&rcc CK_KER_SPDIFRX>; 431 clock-names = "kclk"; 432 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 433 dmas = <&hpdma 71 0x43 0x212>, 434 <&hpdma 72 0x43 0x212>; 435 dma-names = "rx", "rx-ctrl"; 436 access-controllers = <&rifsc 30>; 437 status = "disabled"; 438 }; 439 440 usart2: serial@400e0000 { 441 compatible = "st,stm32h7-uart"; 442 reg = <0x400e0000 0x400>; 443 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&rcc CK_KER_USART2>; 445 dmas = <&hpdma 11 0x20 0x10012>, 446 <&hpdma 12 0x20 0x3021>; 447 dma-names = "rx", "tx"; 448 access-controllers = <&rifsc 32>; 449 status = "disabled"; 450 }; 451 452 usart3: serial@400f0000 { 453 compatible = "st,stm32h7-uart"; 454 reg = <0x400f0000 0x400>; 455 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&rcc CK_KER_USART3>; 457 dmas = <&hpdma 13 0x20 0x10012>, 458 <&hpdma 14 0x20 0x3021>; 459 dma-names = "rx", "tx"; 460 access-controllers = <&rifsc 33>; 461 status = "disabled"; 462 }; 463 464 uart4: serial@40100000 { 465 compatible = "st,stm32h7-uart"; 466 reg = <0x40100000 0x400>; 467 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 468 clocks = <&rcc CK_KER_UART4>; 469 dmas = <&hpdma 15 0x20 0x10012>, 470 <&hpdma 16 0x20 0x3021>; 471 dma-names = "rx", "tx"; 472 access-controllers = <&rifsc 34>; 473 status = "disabled"; 474 }; 475 476 uart5: serial@40110000 { 477 compatible = "st,stm32h7-uart"; 478 reg = <0x40110000 0x400>; 479 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&rcc CK_KER_UART5>; 481 dmas = <&hpdma 17 0x20 0x10012>, 482 <&hpdma 18 0x20 0x3021>; 483 dma-names = "rx", "tx"; 484 access-controllers = <&rifsc 35>; 485 status = "disabled"; 486 }; 487 488 i2c1: i2c@40120000 { 489 compatible = "st,stm32mp25-i2c"; 490 reg = <0x40120000 0x400>; 491 interrupt-names = "event"; 492 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 493 clocks = <&rcc CK_KER_I2C1>; 494 resets = <&rcc I2C1_R>; 495 #address-cells = <1>; 496 #size-cells = <0>; 497 dmas = <&hpdma 27 0x20 0x3012>, 498 <&hpdma 28 0x20 0x3021>; 499 dma-names = "rx", "tx"; 500 access-controllers = <&rifsc 41>; 501 status = "disabled"; 502 }; 503 504 i2c2: i2c@40130000 { 505 compatible = "st,stm32mp25-i2c"; 506 reg = <0x40130000 0x400>; 507 interrupt-names = "event"; 508 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&rcc CK_KER_I2C2>; 510 resets = <&rcc I2C2_R>; 511 #address-cells = <1>; 512 #size-cells = <0>; 513 dmas = <&hpdma 30 0x20 0x3012>, 514 <&hpdma 31 0x20 0x3021>; 515 dma-names = "rx", "tx"; 516 access-controllers = <&rifsc 42>; 517 status = "disabled"; 518 }; 519 520 i2c3: i2c@40140000 { 521 compatible = "st,stm32mp25-i2c"; 522 reg = <0x40140000 0x400>; 523 interrupt-names = "event"; 524 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 525 clocks = <&rcc CK_KER_I2C3>; 526 resets = <&rcc I2C3_R>; 527 #address-cells = <1>; 528 #size-cells = <0>; 529 dmas = <&hpdma 33 0x20 0x3012>, 530 <&hpdma 34 0x20 0x3021>; 531 dma-names = "rx", "tx"; 532 access-controllers = <&rifsc 43>; 533 status = "disabled"; 534 }; 535 536 i2c4: i2c@40150000 { 537 compatible = "st,stm32mp25-i2c"; 538 reg = <0x40150000 0x400>; 539 interrupt-names = "event"; 540 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&rcc CK_KER_I2C4>; 542 resets = <&rcc I2C4_R>; 543 #address-cells = <1>; 544 #size-cells = <0>; 545 dmas = <&hpdma 36 0x20 0x3012>, 546 <&hpdma 37 0x20 0x3021>; 547 dma-names = "rx", "tx"; 548 access-controllers = <&rifsc 44>; 549 status = "disabled"; 550 }; 551 552 i2c5: i2c@40160000 { 553 compatible = "st,stm32mp25-i2c"; 554 reg = <0x40160000 0x400>; 555 interrupt-names = "event"; 556 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 557 clocks = <&rcc CK_KER_I2C5>; 558 resets = <&rcc I2C5_R>; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 dmas = <&hpdma 39 0x20 0x3012>, 562 <&hpdma 40 0x20 0x3021>; 563 dma-names = "rx", "tx"; 564 access-controllers = <&rifsc 45>; 565 status = "disabled"; 566 }; 567 568 i2c6: i2c@40170000 { 569 compatible = "st,stm32mp25-i2c"; 570 reg = <0x40170000 0x400>; 571 interrupt-names = "event"; 572 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&rcc CK_KER_I2C6>; 574 resets = <&rcc I2C6_R>; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 dmas = <&hpdma 42 0x20 0x3012>, 578 <&hpdma 43 0x20 0x3021>; 579 dma-names = "rx", "tx"; 580 access-controllers = <&rifsc 46>; 581 status = "disabled"; 582 }; 583 584 i2c7: i2c@40180000 { 585 compatible = "st,stm32mp25-i2c"; 586 reg = <0x40180000 0x400>; 587 interrupt-names = "event"; 588 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; 589 clocks = <&rcc CK_KER_I2C7>; 590 resets = <&rcc I2C7_R>; 591 #address-cells = <1>; 592 #size-cells = <0>; 593 dmas = <&hpdma 45 0x20 0x3012>, 594 <&hpdma 46 0x20 0x3021>; 595 dma-names = "rx", "tx"; 596 access-controllers = <&rifsc 47>; 597 status = "disabled"; 598 }; 599 600 usart6: serial@40220000 { 601 compatible = "st,stm32h7-uart"; 602 reg = <0x40220000 0x400>; 603 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 604 clocks = <&rcc CK_KER_USART6>; 605 dmas = <&hpdma 19 0x20 0x10012>, 606 <&hpdma 20 0x20 0x3021>; 607 dma-names = "rx", "tx"; 608 access-controllers = <&rifsc 36>; 609 status = "disabled"; 610 }; 611 612 i2s1: audio-controller@40230000 { 613 compatible = "st,stm32mp25-i2s"; 614 reg = <0x40230000 0x400>; 615 #sound-dai-cells = <0>; 616 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 617 clocks = <&rcc CK_BUS_SPI1>, <&rcc CK_KER_SPI1>; 618 clock-names = "pclk", "i2sclk"; 619 resets = <&rcc SPI1_R>; 620 dmas = <&hpdma 49 0x43 0x12>, 621 <&hpdma 50 0x43 0x21>; 622 dma-names = "rx", "tx"; 623 access-controllers = <&rifsc 22>; 624 status = "disabled"; 625 }; 626 627 spi1: spi@40230000 { 628 #address-cells = <1>; 629 #size-cells = <0>; 630 compatible = "st,stm32mp25-spi"; 631 reg = <0x40230000 0x400>; 632 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 633 clocks = <&rcc CK_KER_SPI1>; 634 resets = <&rcc SPI1_R>; 635 dmas = <&hpdma 49 0x20 0x3012>, 636 <&hpdma 50 0x20 0x3021>; 637 dma-names = "rx", "tx"; 638 access-controllers = <&rifsc 22>; 639 status = "disabled"; 640 }; 641 642 spi4: spi@40240000 { 643 #address-cells = <1>; 644 #size-cells = <0>; 645 compatible = "st,stm32mp25-spi"; 646 reg = <0x40240000 0x400>; 647 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 648 clocks = <&rcc CK_KER_SPI4>; 649 resets = <&rcc SPI4_R>; 650 dmas = <&hpdma 55 0x20 0x3012>, 651 <&hpdma 56 0x20 0x3021>; 652 dma-names = "rx", "tx"; 653 access-controllers = <&rifsc 25>; 654 status = "disabled"; 655 }; 656 657 spi5: spi@40280000 { 658 #address-cells = <1>; 659 #size-cells = <0>; 660 compatible = "st,stm32mp25-spi"; 661 reg = <0x40280000 0x400>; 662 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 663 clocks = <&rcc CK_KER_SPI5>; 664 resets = <&rcc SPI5_R>; 665 dmas = <&hpdma 57 0x20 0x3012>, 666 <&hpdma 58 0x20 0x3021>; 667 dma-names = "rx", "tx"; 668 access-controllers = <&rifsc 26>; 669 status = "disabled"; 670 }; 671 672 sai1: sai@40290000 { 673 compatible = "st,stm32mp25-sai"; 674 reg = <0x40290000 0x4>, <0x4029a3f0 0x10>; 675 ranges = <0 0x40290000 0x400>; 676 #address-cells = <1>; 677 #size-cells = <1>; 678 clocks = <&rcc CK_BUS_SAI1>; 679 clock-names = "pclk"; 680 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 681 resets = <&rcc SAI1_R>; 682 access-controllers = <&rifsc 49>; 683 status = "disabled"; 684 685 sai1a: audio-controller@40290004 { 686 compatible = "st,stm32-sai-sub-a"; 687 reg = <0x4 0x20>; 688 #sound-dai-cells = <0>; 689 clocks = <&rcc CK_KER_SAI1>; 690 clock-names = "sai_ck"; 691 dmas = <&hpdma 73 0x43 0x21>; 692 status = "disabled"; 693 }; 694 695 sai1b: audio-controller@40290024 { 696 compatible = "st,stm32-sai-sub-b"; 697 reg = <0x24 0x20>; 698 #sound-dai-cells = <0>; 699 clocks = <&rcc CK_KER_SAI1>; 700 clock-names = "sai_ck"; 701 dmas = <&hpdma 74 0x43 0x12>; 702 status = "disabled"; 703 }; 704 }; 705 706 sai2: sai@402a0000 { 707 compatible = "st,stm32mp25-sai"; 708 reg = <0x402a0000 0x4>, <0x402aa3f0 0x10>; 709 ranges = <0 0x402a0000 0x400>; 710 #address-cells = <1>; 711 #size-cells = <1>; 712 clocks = <&rcc CK_BUS_SAI2>; 713 clock-names = "pclk"; 714 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 715 resets = <&rcc SAI2_R>; 716 access-controllers = <&rifsc 50>; 717 status = "disabled"; 718 719 sai2a: audio-controller@402a0004 { 720 compatible = "st,stm32-sai-sub-a"; 721 reg = <0x4 0x20>; 722 #sound-dai-cells = <0>; 723 clocks = <&rcc CK_KER_SAI2>; 724 clock-names = "sai_ck"; 725 dmas = <&hpdma 75 0x43 0x21>; 726 status = "disabled"; 727 }; 728 729 sai2b: audio-controller@402a0024 { 730 compatible = "st,stm32-sai-sub-b"; 731 reg = <0x24 0x20>; 732 #sound-dai-cells = <0>; 733 clocks = <&rcc CK_KER_SAI2>; 734 clock-names = "sai_ck"; 735 dmas = <&hpdma 76 0x43 0x12>; 736 status = "disabled"; 737 }; 738 }; 739 740 sai3: sai@402b0000 { 741 compatible = "st,stm32mp25-sai"; 742 reg = <0x402b0000 0x4>, <0x402ba3f0 0x10>; 743 ranges = <0 0x402b0000 0x400>; 744 #address-cells = <1>; 745 #size-cells = <1>; 746 clocks = <&rcc CK_BUS_SAI3>; 747 clock-names = "pclk"; 748 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 749 resets = <&rcc SAI3_R>; 750 access-controllers = <&rifsc 51>; 751 status = "disabled"; 752 753 sai3a: audio-controller@402b0004 { 754 compatible = "st,stm32-sai-sub-a"; 755 reg = <0x4 0x20>; 756 #sound-dai-cells = <0>; 757 clocks = <&rcc CK_KER_SAI3>; 758 clock-names = "sai_ck"; 759 dmas = <&hpdma 77 0x43 0x21>; 760 status = "disabled"; 761 }; 762 763 sai3b: audio-controller@502b0024 { 764 compatible = "st,stm32-sai-sub-b"; 765 reg = <0x24 0x20>; 766 #sound-dai-cells = <0>; 767 clocks = <&rcc CK_KER_SAI3>; 768 clock-names = "sai_ck"; 769 dmas = <&hpdma 78 0x43 0x12>; 770 status = "disabled"; 771 }; 772 }; 773 774 uart9: serial@402c0000 { 775 compatible = "st,stm32h7-uart"; 776 reg = <0x402c0000 0x400>; 777 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 778 clocks = <&rcc CK_KER_UART9>; 779 dmas = <&hpdma 25 0x20 0x10012>, 780 <&hpdma 26 0x20 0x3021>; 781 dma-names = "rx", "tx"; 782 access-controllers = <&rifsc 39>; 783 status = "disabled"; 784 }; 785 786 usart1: serial@40330000 { 787 compatible = "st,stm32h7-uart"; 788 reg = <0x40330000 0x400>; 789 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 790 clocks = <&rcc CK_KER_USART1>; 791 dmas = <&hpdma 9 0x20 0x10012>, 792 <&hpdma 10 0x20 0x3021>; 793 dma-names = "rx", "tx"; 794 access-controllers = <&rifsc 31>; 795 status = "disabled"; 796 }; 797 798 sai4: sai@40340000 { 799 compatible = "st,stm32mp25-sai"; 800 reg = <0x40340000 0x4>, <0x4034a3f0 0x10>; 801 ranges = <0 0x40340000 0x400>; 802 #address-cells = <1>; 803 #size-cells = <1>; 804 clocks = <&rcc CK_BUS_SAI4>; 805 clock-names = "pclk"; 806 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 807 resets = <&rcc SAI4_R>; 808 access-controllers = <&rifsc 52>; 809 status = "disabled"; 810 811 sai4a: audio-controller@40340004 { 812 compatible = "st,stm32-sai-sub-a"; 813 reg = <0x4 0x20>; 814 #sound-dai-cells = <0>; 815 clocks = <&rcc CK_KER_SAI4>; 816 clock-names = "sai_ck"; 817 dmas = <&hpdma 79 0x63 0x21>; 818 status = "disabled"; 819 }; 820 821 sai4b: audio-controller@40340024 { 822 compatible = "st,stm32-sai-sub-b"; 823 reg = <0x24 0x20>; 824 #sound-dai-cells = <0>; 825 clocks = <&rcc CK_KER_SAI4>; 826 clock-names = "sai_ck"; 827 dmas = <&hpdma 80 0x43 0x12>; 828 status = "disabled"; 829 }; 830 }; 831 832 spi6: spi@40350000 { 833 #address-cells = <1>; 834 #size-cells = <0>; 835 compatible = "st,stm32mp25-spi"; 836 reg = <0x40350000 0x400>; 837 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 838 clocks = <&rcc CK_KER_SPI6>; 839 resets = <&rcc SPI6_R>; 840 dmas = <&hpdma 59 0x20 0x3012>, 841 <&hpdma 60 0x20 0x3021>; 842 dma-names = "rx", "tx"; 843 access-controllers = <&rifsc 27>; 844 status = "disabled"; 845 }; 846 847 spi7: spi@40360000 { 848 #address-cells = <1>; 849 #size-cells = <0>; 850 compatible = "st,stm32mp25-spi"; 851 reg = <0x40360000 0x400>; 852 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 853 clocks = <&rcc CK_KER_SPI7>; 854 resets = <&rcc SPI7_R>; 855 dmas = <&hpdma 61 0x20 0x3012>, 856 <&hpdma 62 0x20 0x3021>; 857 dma-names = "rx", "tx"; 858 access-controllers = <&rifsc 28>; 859 status = "disabled"; 860 }; 861 862 uart7: serial@40370000 { 863 compatible = "st,stm32h7-uart"; 864 reg = <0x40370000 0x400>; 865 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 866 clocks = <&rcc CK_KER_UART7>; 867 dmas = <&hpdma 21 0x20 0x10012>, 868 <&hpdma 22 0x20 0x3021>; 869 dma-names = "rx", "tx"; 870 access-controllers = <&rifsc 37>; 871 status = "disabled"; 872 }; 873 874 uart8: serial@40380000 { 875 compatible = "st,stm32h7-uart"; 876 reg = <0x40380000 0x400>; 877 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 878 clocks = <&rcc CK_KER_UART8>; 879 dmas = <&hpdma 23 0x20 0x10012>, 880 <&hpdma 24 0x20 0x3021>; 881 dma-names = "rx", "tx"; 882 access-controllers = <&rifsc 38>; 883 status = "disabled"; 884 }; 885 886 rng: rng@42020000 { 887 compatible = "st,stm32mp25-rng"; 888 reg = <0x42020000 0x400>; 889 clocks = <&clk_rcbsec>, <&rcc CK_BUS_RNG>; 890 clock-names = "core", "bus"; 891 resets = <&rcc RNG_R>; 892 access-controllers = <&rifsc 92>; 893 status = "disabled"; 894 }; 895 896 spi8: spi@46020000 { 897 #address-cells = <1>; 898 #size-cells = <0>; 899 compatible = "st,stm32mp25-spi"; 900 reg = <0x46020000 0x400>; 901 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 902 clocks = <&rcc CK_KER_SPI8>; 903 resets = <&rcc SPI8_R>; 904 dmas = <&hpdma 171 0x20 0x3012>, 905 <&hpdma 172 0x20 0x3021>; 906 dma-names = "rx", "tx"; 907 access-controllers = <&rifsc 29>; 908 status = "disabled"; 909 }; 910 911 i2c8: i2c@46040000 { 912 compatible = "st,stm32mp25-i2c"; 913 reg = <0x46040000 0x400>; 914 interrupt-names = "event"; 915 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 916 clocks = <&rcc CK_KER_I2C8>; 917 resets = <&rcc I2C8_R>; 918 #address-cells = <1>; 919 #size-cells = <0>; 920 dmas = <&hpdma 168 0x20 0x3012>, 921 <&hpdma 169 0x20 0x3021>; 922 dma-names = "rx", "tx"; 923 access-controllers = <&rifsc 48>; 924 status = "disabled"; 925 }; 926 927 lptimer3: timer@46050000 { 928 compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer"; 929 reg = <0x46050000 0x400>; 930 interrupts-extended = <&exti2 29 IRQ_TYPE_LEVEL_HIGH>; 931 clocks = <&rcc CK_KER_LPTIM3>; 932 clock-names = "mux"; 933 #address-cells = <1>; 934 #size-cells = <0>; 935 access-controllers = <&rifsc 19>; 936 wakeup-source; 937 status = "disabled"; 938 939 counter { 940 compatible = "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-counter"; 941 status = "disabled"; 942 }; 943 944 pwm { 945 compatible = "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp"; 946 #pwm-cells = <3>; 947 status = "disabled"; 948 }; 949 950 timer { 951 compatible = "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer"; 952 status = "disabled"; 953 }; 954 955 trigger@2 { 956 compatible = "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trigger"; 957 reg = <2>; 958 status = "disabled"; 959 }; 960 }; 961 962 lptimer4: timer@46060000 { 963 compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer"; 964 reg = <0x46060000 0x400>; 965 interrupts-extended = <&exti2 30 IRQ_TYPE_LEVEL_HIGH>; 966 clocks = <&rcc CK_KER_LPTIM4>; 967 clock-names = "mux"; 968 #address-cells = <1>; 969 #size-cells = <0>; 970 access-controllers = <&rifsc 20>; 971 wakeup-source; 972 status = "disabled"; 973 974 counter { 975 compatible = "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-counter"; 976 status = "disabled"; 977 }; 978 979 pwm { 980 compatible = "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp"; 981 #pwm-cells = <3>; 982 status = "disabled"; 983 }; 984 985 timer { 986 compatible = "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer"; 987 status = "disabled"; 988 }; 989 990 trigger@3 { 991 compatible = "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trigger"; 992 reg = <3>; 993 status = "disabled"; 994 }; 995 }; 996 997 lptimer5: timer@46070000 { 998 compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer"; 999 reg = <0x46070000 0x400>; 1000 interrupts-extended = <&exti2 31 IRQ_TYPE_LEVEL_HIGH>; 1001 clocks = <&rcc CK_KER_LPTIM5>; 1002 clock-names = "mux"; 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 access-controllers = <&rifsc 21>; 1006 wakeup-source; 1007 status = "disabled"; 1008 1009 counter { 1010 compatible = "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-counter"; 1011 status = "disabled"; 1012 }; 1013 1014 pwm { 1015 compatible = "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp"; 1016 #pwm-cells = <3>; 1017 status = "disabled"; 1018 }; 1019 1020 timer { 1021 compatible = "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer"; 1022 status = "disabled"; 1023 }; 1024 1025 trigger@4 { 1026 compatible = "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trigger"; 1027 reg = <4>; 1028 status = "disabled"; 1029 }; 1030 }; 1031 1032 csi: csi@48020000 { 1033 compatible = "st,stm32mp25-csi"; 1034 reg = <0x48020000 0x2000>; 1035 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 1036 resets = <&rcc CSI_R>; 1037 clocks = <&rcc CK_KER_CSI>, <&rcc CK_KER_CSITXESC>, 1038 <&rcc CK_KER_CSIPHY>; 1039 clock-names = "pclk", "txesc", "csi2phy"; 1040 access-controllers = <&rifsc 86>; 1041 status = "disabled"; 1042 }; 1043 1044 dcmipp: dcmipp@48030000 { 1045 compatible = "st,stm32mp25-dcmipp"; 1046 reg = <0x48030000 0x1000>; 1047 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 1048 resets = <&rcc DCMIPP_R>; 1049 clocks = <&rcc CK_BUS_DCMIPP>, <&rcc CK_KER_CSI>; 1050 clock-names = "kclk", "mclk"; 1051 access-controllers = <&rifsc 87>; 1052 status = "disabled"; 1053 }; 1054 1055 combophy: phy@480c0000 { 1056 compatible = "st,stm32mp25-combophy"; 1057 reg = <0x480c0000 0x1000>; 1058 #phy-cells = <1>; 1059 clocks = <&rcc CK_BUS_USB3PCIEPHY>, <&rcc CK_KER_USB3PCIEPHY>; 1060 clock-names = "apb", "ker"; 1061 resets = <&rcc USB3PCIEPHY_R>; 1062 reset-names = "phy"; 1063 access-controllers = <&rifsc 67>; 1064 power-domains = <&CLUSTER_PD>; 1065 wakeup-source; 1066 interrupts-extended = <&exti1 45 IRQ_TYPE_EDGE_FALLING>; 1067 status = "disabled"; 1068 }; 1069 1070 sdmmc1: mmc@48220000 { 1071 compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; 1072 arm,primecell-periphid = <0x00353180>; 1073 reg = <0x48220000 0x400>, <0x44230400 0x8>; 1074 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1075 clocks = <&rcc CK_KER_SDMMC1 >; 1076 clock-names = "apb_pclk"; 1077 resets = <&rcc SDMMC1_R>; 1078 cap-sd-highspeed; 1079 cap-mmc-highspeed; 1080 max-frequency = <120000000>; 1081 access-controllers = <&rifsc 76>; 1082 status = "disabled"; 1083 }; 1084 1085 ethernet1: ethernet@482c0000 { 1086 compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20"; 1087 reg = <0x482c0000 0x4000>; 1088 reg-names = "stmmaceth"; 1089 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 1090 interrupt-names = "macirq"; 1091 clock-names = "stmmaceth", 1092 "mac-clk-tx", 1093 "mac-clk-rx", 1094 "ptp_ref", 1095 "ethstp", 1096 "eth-ck"; 1097 clocks = <&rcc CK_ETH1_MAC>, 1098 <&rcc CK_ETH1_TX>, 1099 <&rcc CK_ETH1_RX>, 1100 <&rcc CK_KER_ETH1PTP>, 1101 <&rcc CK_ETH1_STP>, 1102 <&rcc CK_KER_ETH1>; 1103 snps,axi-config = <&stmmac_axi_config_1>; 1104 snps,mixed-burst; 1105 snps,mtl-rx-config = <&mtl_rx_setup_1>; 1106 snps,mtl-tx-config = <&mtl_tx_setup_1>; 1107 snps,pbl = <2>; 1108 snps,tso; 1109 st,syscon = <&syscfg 0x3000>; 1110 access-controllers = <&rifsc 60>; 1111 status = "disabled"; 1112 1113 mtl_rx_setup_1: rx-queues-config { 1114 snps,rx-queues-to-use = <2>; 1115 queue0 {}; 1116 queue1 {}; 1117 }; 1118 1119 mtl_tx_setup_1: tx-queues-config { 1120 snps,tx-queues-to-use = <4>; 1121 queue0 {}; 1122 queue1 {}; 1123 queue2 {}; 1124 queue3 {}; 1125 }; 1126 1127 stmmac_axi_config_1: stmmac-axi-config { 1128 snps,blen = <0 0 0 0 16 8 4>; 1129 snps,rd_osr_lmt = <0x7>; 1130 snps,wr_osr_lmt = <0x7>; 1131 }; 1132 }; 1133 }; 1134 1135 bsec: efuse@44000000 { 1136 compatible = "st,stm32mp25-bsec"; 1137 reg = <0x44000000 0x1000>; 1138 #address-cells = <1>; 1139 #size-cells = <1>; 1140 1141 part_number_otp@24 { 1142 reg = <0x24 0x4>; 1143 }; 1144 1145 package_otp@1e8 { 1146 reg = <0x1e8 0x1>; 1147 bits = <0 3>; 1148 }; 1149 }; 1150 1151 rcc: clock-controller@44200000 { 1152 compatible = "st,stm32mp25-rcc"; 1153 reg = <0x44200000 0x10000>; 1154 #clock-cells = <1>; 1155 #reset-cells = <1>; 1156 clocks = <&scmi_clk CK_SCMI_HSE>, 1157 <&scmi_clk CK_SCMI_HSI>, 1158 <&scmi_clk CK_SCMI_MSI>, 1159 <&scmi_clk CK_SCMI_LSE>, 1160 <&scmi_clk CK_SCMI_LSI>, 1161 <&scmi_clk CK_SCMI_HSE_DIV2>, 1162 <&scmi_clk CK_SCMI_ICN_HS_MCU>, 1163 <&scmi_clk CK_SCMI_ICN_LS_MCU>, 1164 <&scmi_clk CK_SCMI_ICN_SDMMC>, 1165 <&scmi_clk CK_SCMI_ICN_DDR>, 1166 <&scmi_clk CK_SCMI_ICN_DISPLAY>, 1167 <&scmi_clk CK_SCMI_ICN_HSL>, 1168 <&scmi_clk CK_SCMI_ICN_NIC>, 1169 <&scmi_clk CK_SCMI_ICN_VID>, 1170 <&scmi_clk CK_SCMI_FLEXGEN_07>, 1171 <&scmi_clk CK_SCMI_FLEXGEN_08>, 1172 <&scmi_clk CK_SCMI_FLEXGEN_09>, 1173 <&scmi_clk CK_SCMI_FLEXGEN_10>, 1174 <&scmi_clk CK_SCMI_FLEXGEN_11>, 1175 <&scmi_clk CK_SCMI_FLEXGEN_12>, 1176 <&scmi_clk CK_SCMI_FLEXGEN_13>, 1177 <&scmi_clk CK_SCMI_FLEXGEN_14>, 1178 <&scmi_clk CK_SCMI_FLEXGEN_15>, 1179 <&scmi_clk CK_SCMI_FLEXGEN_16>, 1180 <&scmi_clk CK_SCMI_FLEXGEN_17>, 1181 <&scmi_clk CK_SCMI_FLEXGEN_18>, 1182 <&scmi_clk CK_SCMI_FLEXGEN_19>, 1183 <&scmi_clk CK_SCMI_FLEXGEN_20>, 1184 <&scmi_clk CK_SCMI_FLEXGEN_21>, 1185 <&scmi_clk CK_SCMI_FLEXGEN_22>, 1186 <&scmi_clk CK_SCMI_FLEXGEN_23>, 1187 <&scmi_clk CK_SCMI_FLEXGEN_24>, 1188 <&scmi_clk CK_SCMI_FLEXGEN_25>, 1189 <&scmi_clk CK_SCMI_FLEXGEN_26>, 1190 <&scmi_clk CK_SCMI_FLEXGEN_27>, 1191 <&scmi_clk CK_SCMI_FLEXGEN_28>, 1192 <&scmi_clk CK_SCMI_FLEXGEN_29>, 1193 <&scmi_clk CK_SCMI_FLEXGEN_30>, 1194 <&scmi_clk CK_SCMI_FLEXGEN_31>, 1195 <&scmi_clk CK_SCMI_FLEXGEN_32>, 1196 <&scmi_clk CK_SCMI_FLEXGEN_33>, 1197 <&scmi_clk CK_SCMI_FLEXGEN_34>, 1198 <&scmi_clk CK_SCMI_FLEXGEN_35>, 1199 <&scmi_clk CK_SCMI_FLEXGEN_36>, 1200 <&scmi_clk CK_SCMI_FLEXGEN_37>, 1201 <&scmi_clk CK_SCMI_FLEXGEN_38>, 1202 <&scmi_clk CK_SCMI_FLEXGEN_39>, 1203 <&scmi_clk CK_SCMI_FLEXGEN_40>, 1204 <&scmi_clk CK_SCMI_FLEXGEN_41>, 1205 <&scmi_clk CK_SCMI_FLEXGEN_42>, 1206 <&scmi_clk CK_SCMI_FLEXGEN_43>, 1207 <&scmi_clk CK_SCMI_FLEXGEN_44>, 1208 <&scmi_clk CK_SCMI_FLEXGEN_45>, 1209 <&scmi_clk CK_SCMI_FLEXGEN_46>, 1210 <&scmi_clk CK_SCMI_FLEXGEN_47>, 1211 <&scmi_clk CK_SCMI_FLEXGEN_48>, 1212 <&scmi_clk CK_SCMI_FLEXGEN_49>, 1213 <&scmi_clk CK_SCMI_FLEXGEN_50>, 1214 <&scmi_clk CK_SCMI_FLEXGEN_51>, 1215 <&scmi_clk CK_SCMI_FLEXGEN_52>, 1216 <&scmi_clk CK_SCMI_FLEXGEN_53>, 1217 <&scmi_clk CK_SCMI_FLEXGEN_54>, 1218 <&scmi_clk CK_SCMI_FLEXGEN_55>, 1219 <&scmi_clk CK_SCMI_FLEXGEN_56>, 1220 <&scmi_clk CK_SCMI_FLEXGEN_57>, 1221 <&scmi_clk CK_SCMI_FLEXGEN_58>, 1222 <&scmi_clk CK_SCMI_FLEXGEN_59>, 1223 <&scmi_clk CK_SCMI_FLEXGEN_60>, 1224 <&scmi_clk CK_SCMI_FLEXGEN_61>, 1225 <&scmi_clk CK_SCMI_FLEXGEN_62>, 1226 <&scmi_clk CK_SCMI_FLEXGEN_63>, 1227 <&scmi_clk CK_SCMI_ICN_APB1>, 1228 <&scmi_clk CK_SCMI_ICN_APB2>, 1229 <&scmi_clk CK_SCMI_ICN_APB3>, 1230 <&scmi_clk CK_SCMI_ICN_APB4>, 1231 <&scmi_clk CK_SCMI_ICN_APBDBG>, 1232 <&scmi_clk CK_SCMI_TIMG1>, 1233 <&scmi_clk CK_SCMI_TIMG2>, 1234 <&scmi_clk CK_SCMI_PLL3>, 1235 <&clk_dsi_txbyte>; 1236 access-controllers = <&rifsc 156>; 1237 }; 1238 1239 exti1: interrupt-controller@44220000 { 1240 compatible = "st,stm32mp1-exti", "syscon"; 1241 interrupt-controller; 1242 #interrupt-cells = <2>; 1243 reg = <0x44220000 0x400>; 1244 interrupts-extended = 1245 <&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 1246 <&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 1247 <&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 1248 <&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 1249 <&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 1250 <&intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 1251 <&intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 1252 <&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 1253 <&intc GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 1254 <&intc GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 1255 <&intc GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 1256 <&intc GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1257 <&intc GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1258 <&intc GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1259 <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1260 <&intc GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1261 <&intc GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 1262 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 1263 <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1264 <&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1265 <0>, /* EXTI_20 */ 1266 <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1267 <&intc GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1268 <&intc GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1269 <&intc GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1270 <&intc GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1271 <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1272 <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1273 <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1274 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1275 <&intc GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 1276 <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1277 <&intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1278 <&intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1279 <&intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1280 <0>, 1281 <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1282 <&intc GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1283 <&intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1284 <&intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 1285 <&intc GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 1286 <&intc GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 1287 <&intc GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1288 <&intc GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1289 <&intc GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1290 <&intc GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 1291 <&intc GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1292 <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 1293 <&intc GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 1294 <&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1295 <&intc GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 1296 <0>, 1297 <0>, 1298 <0>, 1299 <0>, 1300 <0>, 1301 <0>, 1302 <0>, 1303 <0>, 1304 <&intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1305 <0>, /* EXTI_60 */ 1306 <&intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1307 <0>, 1308 <0>, 1309 <&intc GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1310 <0>, 1311 <0>, 1312 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1313 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1314 <0>, 1315 <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ 1316 <0>, 1317 <&intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 1318 <&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 1319 <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1320 <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1321 <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 1322 <&intc GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1323 <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1324 <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1325 <0>, /* EXTI_80 */ 1326 <0>, 1327 <0>, 1328 <&intc GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 1329 <&intc GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 1330 }; 1331 1332 syscfg: syscon@44230000 { 1333 compatible = "st,stm32mp25-syscfg", "syscon"; 1334 reg = <0x44230000 0x10000>; 1335 }; 1336 1337 pinctrl: pinctrl@44240000 { 1338 #address-cells = <1>; 1339 #size-cells = <1>; 1340 compatible = "st,stm32mp257-pinctrl"; 1341 ranges = <0 0x44240000 0xa0400>; 1342 interrupt-parent = <&exti1>; 1343 st,syscfg = <&exti1 0x60 0xff>; 1344 pins-are-numbered; 1345 1346 gpioa: gpio@44240000 { 1347 gpio-controller; 1348 #gpio-cells = <2>; 1349 interrupt-controller; 1350 #interrupt-cells = <2>; 1351 reg = <0x0 0x400>; 1352 clocks = <&scmi_clk CK_SCMI_GPIOA>; 1353 st,bank-name = "GPIOA"; 1354 status = "disabled"; 1355 }; 1356 1357 gpiob: gpio@44250000 { 1358 gpio-controller; 1359 #gpio-cells = <2>; 1360 interrupt-controller; 1361 #interrupt-cells = <2>; 1362 reg = <0x10000 0x400>; 1363 clocks = <&scmi_clk CK_SCMI_GPIOB>; 1364 st,bank-name = "GPIOB"; 1365 status = "disabled"; 1366 }; 1367 1368 gpioc: gpio@44260000 { 1369 gpio-controller; 1370 #gpio-cells = <2>; 1371 interrupt-controller; 1372 #interrupt-cells = <2>; 1373 reg = <0x20000 0x400>; 1374 clocks = <&scmi_clk CK_SCMI_GPIOC>; 1375 st,bank-name = "GPIOC"; 1376 status = "disabled"; 1377 }; 1378 1379 gpiod: gpio@44270000 { 1380 gpio-controller; 1381 #gpio-cells = <2>; 1382 interrupt-controller; 1383 #interrupt-cells = <2>; 1384 reg = <0x30000 0x400>; 1385 clocks = <&scmi_clk CK_SCMI_GPIOD>; 1386 st,bank-name = "GPIOD"; 1387 status = "disabled"; 1388 }; 1389 1390 gpioe: gpio@44280000 { 1391 gpio-controller; 1392 #gpio-cells = <2>; 1393 interrupt-controller; 1394 #interrupt-cells = <2>; 1395 reg = <0x40000 0x400>; 1396 clocks = <&scmi_clk CK_SCMI_GPIOE>; 1397 st,bank-name = "GPIOE"; 1398 status = "disabled"; 1399 }; 1400 1401 gpiof: gpio@44290000 { 1402 gpio-controller; 1403 #gpio-cells = <2>; 1404 interrupt-controller; 1405 #interrupt-cells = <2>; 1406 reg = <0x50000 0x400>; 1407 clocks = <&scmi_clk CK_SCMI_GPIOF>; 1408 st,bank-name = "GPIOF"; 1409 status = "disabled"; 1410 }; 1411 1412 gpiog: gpio@442a0000 { 1413 gpio-controller; 1414 #gpio-cells = <2>; 1415 interrupt-controller; 1416 #interrupt-cells = <2>; 1417 reg = <0x60000 0x400>; 1418 clocks = <&scmi_clk CK_SCMI_GPIOG>; 1419 st,bank-name = "GPIOG"; 1420 status = "disabled"; 1421 }; 1422 1423 gpioh: gpio@442b0000 { 1424 gpio-controller; 1425 #gpio-cells = <2>; 1426 interrupt-controller; 1427 #interrupt-cells = <2>; 1428 reg = <0x70000 0x400>; 1429 clocks = <&scmi_clk CK_SCMI_GPIOH>; 1430 st,bank-name = "GPIOH"; 1431 status = "disabled"; 1432 }; 1433 1434 gpioi: gpio@442c0000 { 1435 gpio-controller; 1436 #gpio-cells = <2>; 1437 interrupt-controller; 1438 #interrupt-cells = <2>; 1439 reg = <0x80000 0x400>; 1440 clocks = <&scmi_clk CK_SCMI_GPIOI>; 1441 st,bank-name = "GPIOI"; 1442 status = "disabled"; 1443 }; 1444 1445 gpioj: gpio@442d0000 { 1446 gpio-controller; 1447 #gpio-cells = <2>; 1448 interrupt-controller; 1449 #interrupt-cells = <2>; 1450 reg = <0x90000 0x400>; 1451 clocks = <&scmi_clk CK_SCMI_GPIOJ>; 1452 st,bank-name = "GPIOJ"; 1453 status = "disabled"; 1454 }; 1455 1456 gpiok: gpio@442e0000 { 1457 gpio-controller; 1458 #gpio-cells = <2>; 1459 interrupt-controller; 1460 #interrupt-cells = <2>; 1461 reg = <0xa0000 0x400>; 1462 clocks = <&scmi_clk CK_SCMI_GPIOK>; 1463 st,bank-name = "GPIOK"; 1464 status = "disabled"; 1465 }; 1466 }; 1467 1468 rtc: rtc@46000000 { 1469 compatible = "st,stm32mp25-rtc"; 1470 reg = <0x46000000 0x400>; 1471 clocks = <&scmi_clk CK_SCMI_RTC>, 1472 <&scmi_clk CK_SCMI_RTCCK>; 1473 clock-names = "pclk", "rtc_ck"; 1474 interrupts-extended = <&exti2 17 IRQ_TYPE_LEVEL_HIGH>; 1475 status = "disabled"; 1476 }; 1477 1478 pinctrl_z: pinctrl@46200000 { 1479 #address-cells = <1>; 1480 #size-cells = <1>; 1481 compatible = "st,stm32mp257-z-pinctrl"; 1482 ranges = <0 0x46200000 0x400>; 1483 interrupt-parent = <&exti1>; 1484 st,syscfg = <&exti1 0x60 0xff>; 1485 pins-are-numbered; 1486 1487 gpioz: gpio@46200000 { 1488 gpio-controller; 1489 #gpio-cells = <2>; 1490 interrupt-controller; 1491 #interrupt-cells = <2>; 1492 reg = <0 0x400>; 1493 clocks = <&scmi_clk CK_SCMI_GPIOZ>; 1494 st,bank-name = "GPIOZ"; 1495 st,bank-ioport = <11>; 1496 status = "disabled"; 1497 }; 1498 1499 }; 1500 1501 exti2: interrupt-controller@46230000 { 1502 compatible = "st,stm32mp1-exti", "syscon"; 1503 interrupt-controller; 1504 #interrupt-cells = <2>; 1505 reg = <0x46230000 0x400>; 1506 interrupts-extended = 1507 <&intc GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 1508 <&intc GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1509 <&intc GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1510 <&intc GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1511 <&intc GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1512 <&intc GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1513 <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1514 <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1515 <&intc GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1516 <&intc GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1517 <&intc GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 1518 <&intc GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1519 <&intc GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1520 <&intc GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1521 <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1522 <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1523 <&intc GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1524 <&intc GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1525 <0>, 1526 <0>, 1527 <0>, /* EXTI_20 */ 1528 <&intc GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1529 <&intc GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1530 <0>, 1531 <0>, 1532 <&intc GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1533 <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1534 <&intc GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 1535 <0>, 1536 <&intc GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1537 <&intc GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 1538 <&intc GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1539 <0>, 1540 <&intc GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1541 <&intc GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 1542 <0>, 1543 <0>, 1544 <&intc GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 1545 <0>, 1546 <0>, 1547 <&intc GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 1548 <0>, 1549 <0>, 1550 <&intc GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1551 <0>, 1552 <0>, 1553 <&intc GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1554 <0>, 1555 <&intc GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 1556 <&intc GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1557 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 1558 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1559 <&intc GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 1560 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1561 <0>, 1562 <0>, 1563 <0>, 1564 <0>, 1565 <0>, 1566 <0>, 1567 <0>, /* EXTI_60 */ 1568 <&intc GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 1569 <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1570 <0>, 1571 <&intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1572 <&intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1573 <&intc GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1574 <&intc GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1575 <0>, 1576 <0>, 1577 <&intc GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ 1578 }; 1579 }; 1580}; 1581