xref: /linux/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi (revision 55a42f78ffd386e01a5404419f8c5ded7db70a21) 
1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/pinctrl/stm32-pinfunc.h>
7
8&pinctrl {
9	eth1_mdio_pins_a: eth1-mdio-0 {
10		pins1 {
11			pinmux = <STM32_PINMUX('F', 0, AF10)>; /* ETH_MDC */
12			bias-disable;
13			drive-push-pull;
14			slew-rate = <2>;
15		};
16		pins2 {
17			pinmux = <STM32_PINMUX('F', 2, AF10)>; /* ETH_MDIO */
18			bias-disable;
19			drive-push-pull;
20			slew-rate = <0>;
21		};
22	};
23
24	eth1_mdio_sleep_pins_a: eth1-mdio-sleep-0 {
25		pins1 {
26			pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* ETH_MDC */
27				 <STM32_PINMUX('F', 2, ANALOG)>; /* ETH_MDIO */
28		};
29	};
30
31	eth1_rgmii_pins_a: eth1-rgmii-0 {
32		pins1 {
33			pinmux = <STM32_PINMUX('A', 15, AF10)>, /* ETH_RGMII_TXD0 */
34				 <STM32_PINMUX('C', 1, AF10)>, /* ETH_RGMII_TXD1 */
35				 <STM32_PINMUX('H', 10, AF10)>, /* ETH_RGMII_TXD2 */
36				 <STM32_PINMUX('H', 11, AF10)>, /* ETH_RGMII_TXD3 */
37				 <STM32_PINMUX('A', 13, AF10)>; /* ETH_RGMII_TX_CTL */
38			bias-disable;
39			drive-push-pull;
40			slew-rate = <3>;
41		};
42		pins2 {
43			pinmux = <STM32_PINMUX('H', 9, AF10)>, /* ETH_RGMII_CLK125 */
44				 <STM32_PINMUX('C', 0, AF12)>; /* ETH_RGMII_GTX_CLK */
45			bias-disable;
46			drive-push-pull;
47			slew-rate = <3>;
48		};
49		pins3 {
50			pinmux = <STM32_PINMUX('F', 1, AF10)>, /* ETH_RGMII_RXD0 */
51				 <STM32_PINMUX('C', 2, AF10)>, /* ETH_RGMII_RXD1 */
52				 <STM32_PINMUX('H', 12, AF10)>, /* ETH_RGMII_RXD2 */
53				 <STM32_PINMUX('H', 13, AF10)>, /* ETH_RGMII_RXD3 */
54				 <STM32_PINMUX('A', 11, AF10)>; /* ETH_RGMII_RX_CTL */
55			bias-disable;
56		};
57		pins4 {
58			pinmux = <STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */
59			bias-disable;
60		};
61	};
62
63	eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 {
64		pins {
65			pinmux = <STM32_PINMUX('A', 15, ANALOG)>, /* ETH_RGMII_TXD0 */
66				 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_TXD1 */
67				 <STM32_PINMUX('H', 10, ANALOG)>, /* ETH_RGMII_TXD2 */
68				 <STM32_PINMUX('H', 11, ANALOG)>, /* ETH_RGMII_TXD3 */
69				 <STM32_PINMUX('A', 13, ANALOG)>, /* ETH_RGMII_TX_CTL */
70				 <STM32_PINMUX('H', 9, ANALOG)>, /* ETH_RGMII_CLK125 */
71				 <STM32_PINMUX('C', 0, ANALOG)>, /* ETH_RGMII_GTX_CLK */
72				 <STM32_PINMUX('F', 1, ANALOG)>, /* ETH_RGMII_RXD0 */
73				 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_RXD1 */
74				 <STM32_PINMUX('H', 12, ANALOG)>, /* ETH_RGMII_RXD2 */
75				 <STM32_PINMUX('H', 13, ANALOG)>, /* ETH_RGMII_RXD3 */
76				 <STM32_PINMUX('A', 11, ANALOG)>, /* ETH_RGMII_RX_CTL */
77				 <STM32_PINMUX('A', 14, ANALOG)>; /* ETH_RGMII_RX_CLK */
78		};
79	};
80
81	eth1_rgmii_pins_b: eth1-rgmii-1 {
82		pins1 {
83			pinmux = <STM32_PINMUX('A', 15, AF10)>, /* ETH_RGMII_TXD0 */
84				 <STM32_PINMUX('C', 1, AF10)>, /* ETH_RGMII_TXD1 */
85				 <STM32_PINMUX('H', 10, AF10)>, /* ETH_RGMII_TXD2 */
86				 <STM32_PINMUX('H', 11, AF10)>, /* ETH_RGMII_TXD3 */
87				 <STM32_PINMUX('A', 13, AF10)>; /* ETH_RGMII_TX_CTL */
88			bias-disable;
89			drive-push-pull;
90			slew-rate = <3>;
91		};
92		pins2 {
93			pinmux = <STM32_PINMUX('H', 9, AF10)>, /* ETH_RGMII_CLK125 */
94				 <STM32_PINMUX('C', 0, AF12)>, /* ETH_RGMII_GTX_CLK */
95				 <STM32_PINMUX('A', 9, AF10)>, /* ETH_MDC */
96				 <STM32_PINMUX('A', 10, AF10)>; /* ETH_MDIO */
97			bias-disable;
98			drive-push-pull;
99			slew-rate = <3>;
100		};
101		pins3 {
102			pinmux = <STM32_PINMUX('F', 1, AF10)>, /* ETH_RGMII_RXD0 */
103				 <STM32_PINMUX('C', 2, AF10)>, /* ETH_RGMII_RXD1 */
104				 <STM32_PINMUX('H', 12, AF10)>, /* ETH_RGMII_RXD2 */
105				 <STM32_PINMUX('H', 13, AF10)>, /* ETH_RGMII_RXD3 */
106				 <STM32_PINMUX('A', 11, AF10)>; /* ETH_RGMII_RX_CTL */
107			bias-disable;
108		};
109		pins4 {
110			pinmux = <STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */
111			bias-disable;
112		};
113	};
114
115	eth1_rgmii_sleep_pins_b: eth1-rgmii-sleep-1 {
116		pins {
117			pinmux = <STM32_PINMUX('A', 15, ANALOG)>, /* ETH_RGMII_TXD0 */
118				 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_TXD1 */
119				 <STM32_PINMUX('H', 10, ANALOG)>, /* ETH_RGMII_TXD2 */
120				 <STM32_PINMUX('H', 11, ANALOG)>, /* ETH_RGMII_TXD3 */
121				 <STM32_PINMUX('A', 13, ANALOG)>, /* ETH_RGMII_TX_CTL */
122				 <STM32_PINMUX('H', 9, ANALOG)>, /* ETH_RGMII_CLK125 */
123				 <STM32_PINMUX('C', 0, ANALOG)>, /* ETH_RGMII_GTX_CLK */
124				 <STM32_PINMUX('A', 9, ANALOG)>, /* ETH_MDC */
125				 <STM32_PINMUX('A', 10, ANALOG)>, /* ETH_MDIO */
126				 <STM32_PINMUX('F', 1, ANALOG)>, /* ETH_RGMII_RXD0 */
127				 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_RXD1 */
128				 <STM32_PINMUX('H', 12, ANALOG)>, /* ETH_RGMII_RXD2 */
129				 <STM32_PINMUX('H', 13, ANALOG)>, /* ETH_RGMII_RXD3 */
130				 <STM32_PINMUX('A', 11, ANALOG)>, /* ETH_RGMII_RX_CTL */
131				 <STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */
132		};
133	};
134
135	eth2_rgmii_pins_a: eth2-rgmii-0 {
136		pins1 {
137			pinmux = <STM32_PINMUX('C', 7, AF10)>, /* ETH_RGMII_TXD0 */
138				 <STM32_PINMUX('C', 8, AF10)>, /* ETH_RGMII_TXD1 */
139				 <STM32_PINMUX('C', 9, AF10)>, /* ETH_RGMII_TXD2 */
140				 <STM32_PINMUX('C', 10, AF10)>, /* ETH_RGMII_TXD3 */
141				 <STM32_PINMUX('C', 4, AF10)>; /* ETH_RGMII_TX_CTL */
142			bias-disable;
143			drive-push-pull;
144			slew-rate = <3>;
145		};
146		pins2 {
147			pinmux = <STM32_PINMUX('F', 8, AF10)>, /* ETH_RGMII_CLK125 */
148				 <STM32_PINMUX('F', 7, AF10)>, /* ETH_RGMII_GTX_CLK */
149				 <STM32_PINMUX('C', 6, AF10)>; /* ETH_MDC */
150			bias-disable;
151			drive-push-pull;
152			slew-rate = <3>;
153		};
154		pins3 {
155			pinmux = <STM32_PINMUX('C', 5, AF10)>; /* ETH_MDIO */
156			bias-disable;
157			drive-push-pull;
158			slew-rate = <0>;
159		};
160		pins4 {
161			pinmux = <STM32_PINMUX('G', 0, AF10)>, /* ETH_RGMII_RXD0 */
162				 <STM32_PINMUX('C', 12, AF10)>, /* ETH_RGMII_RXD1 */
163				 <STM32_PINMUX('F', 9, AF10)>, /* ETH_RGMII_RXD2 */
164				 <STM32_PINMUX('C', 11, AF10)>, /* ETH_RGMII_RXD3 */
165				 <STM32_PINMUX('C', 3, AF10)>; /* ETH_RGMII_RX_CTL */
166			bias-disable;
167		};
168		pins5 {
169			pinmux = <STM32_PINMUX('F', 6, AF10)>; /* ETH_RGMII_RX_CLK */
170			bias-disable;
171		};
172	};
173
174	eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 {
175		pins {
176			pinmux = <STM32_PINMUX('C', 7, ANALOG)>, /* ETH_RGMII_TXD0 */
177				 <STM32_PINMUX('C', 8, ANALOG)>, /* ETH_RGMII_TXD1 */
178				 <STM32_PINMUX('C', 9, ANALOG)>, /* ETH_RGMII_TXD2 */
179				 <STM32_PINMUX('C', 10, ANALOG)>, /* ETH_RGMII_TXD3 */
180				 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_TX_CTL */
181				 <STM32_PINMUX('F', 8, ANALOG)>, /* ETH_RGMII_CLK125 */
182				 <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RGMII_GTX_CLK */
183				 <STM32_PINMUX('C', 6, ANALOG)>, /* ETH_MDC */
184				 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_MDIO */
185				 <STM32_PINMUX('G', 0, ANALOG)>, /* ETH_RGMII_RXD0 */
186				 <STM32_PINMUX('C', 12, ANALOG)>, /* ETH_RGMII_RXD1 */
187				 <STM32_PINMUX('F', 9, ANALOG)>, /* ETH_RGMII_RXD2 */
188				 <STM32_PINMUX('C', 11, ANALOG)>, /* ETH_RGMII_RXD3 */
189				 <STM32_PINMUX('C', 3, ANALOG)>, /* ETH_RGMII_RX_CTL */
190				 <STM32_PINMUX('F', 6, ANALOG)>; /* ETH_RGMII_RX_CLK */
191		};
192	};
193
194	i2c2_pins_a: i2c2-0 {
195		pins {
196			pinmux = <STM32_PINMUX('B', 5, AF9)>, /* I2C2_SCL */
197				 <STM32_PINMUX('B', 4, AF9)>; /* I2C2_SDA */
198			bias-disable;
199			drive-open-drain;
200			slew-rate = <0>;
201		};
202	};
203
204	i2c2_sleep_pins_a: i2c2-sleep-0 {
205		pins {
206			pinmux = <STM32_PINMUX('B', 5, ANALOG)>, /* I2C2_SCL */
207				 <STM32_PINMUX('B', 4, ANALOG)>; /* I2C2_SDA */
208		};
209	};
210
211	ospi_port1_clk_pins_a: ospi-port1-clk-0 {
212		pins {
213			pinmux = <STM32_PINMUX('D', 0, AF10)>; /* OSPI1_CLK */
214			bias-disable;
215			drive-push-pull;
216			slew-rate = <2>;
217		};
218	};
219
220	ospi_port1_clk_sleep_pins_a: ospi-port1-clk-sleep-0 {
221		pins {
222			pinmux = <STM32_PINMUX('D', 0, ANALOG)>; /* OSPI1_CLK */
223		};
224	};
225
226	ospi_port1_cs0_pins_a: ospi-port1-cs0-0 {
227		pins {
228			pinmux = <STM32_PINMUX('D', 3, AF10)>; /* OSPI_NCS0 */
229			bias-pull-up;
230			drive-push-pull;
231			slew-rate = <0>;
232		};
233	};
234
235	ospi_port1_cs0_sleep_pins_a: ospi-port1-cs0-sleep-0 {
236		pins {
237			pinmux = <STM32_PINMUX('D', 3, ANALOG)>; /* OSPI_NCS0 */
238		};
239	};
240
241	ospi_port1_io03_pins_a: ospi-port1-io03-0 {
242		pins {
243			pinmux = <STM32_PINMUX('D', 4, AF10)>, /* OSPI_IO0 */
244				 <STM32_PINMUX('D', 5, AF10)>, /* OSPI_IO1 */
245				 <STM32_PINMUX('D', 6, AF10)>, /* OSPI_IO2 */
246				 <STM32_PINMUX('D', 7, AF10)>; /* OSPI_IO3 */
247			bias-disable;
248			drive-push-pull;
249			slew-rate = <0>;
250		};
251	};
252
253	ospi_port1_io03_sleep_pins_a: ospi-port1-io03-sleep-0 {
254		pins {
255			pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* OSPI_IO0 */
256				 <STM32_PINMUX('D', 5, ANALOG)>, /* OSPI_IO1 */
257				 <STM32_PINMUX('D', 6, ANALOG)>, /* OSPI_IO2 */
258				 <STM32_PINMUX('D', 7, ANALOG)>; /* OSPI_IO3 */
259		};
260	};
261
262	pcie_pins_a: pcie-0 {
263		pins {
264			pinmux = <STM32_PINMUX('J', 0, AF4)>;
265			bias-disable;
266		};
267	};
268
269	pcie_init_pins_a: pcie-init-0 {
270		pins {
271			pinmux = <STM32_PINMUX('J', 0, GPIO)>;
272			output-low;
273		};
274	};
275
276	pcie_sleep_pins_a: pcie-sleep-0 {
277		pins {
278			pinmux = <STM32_PINMUX('J', 0, ANALOG)>;
279		};
280	};
281
282	pwm3_pins_a: pwm3-0 {
283		pins {
284			pinmux = <STM32_PINMUX('B', 15, AF7)>; /* TIM3_CH2 */
285			bias-pull-down;
286			drive-push-pull;
287			slew-rate = <0>;
288		};
289	};
290
291	pwm3_sleep_pins_a: pwm3-sleep-0 {
292		pins {
293			pinmux = <STM32_PINMUX('B', 15, ANALOG)>; /* TIM3_CH2 */
294		};
295	};
296
297	pwm8_pins_a: pwm8-0 {
298		pins {
299			pinmux = <STM32_PINMUX('J', 5, AF8)>, /* TIM8_CH1 */
300				 <STM32_PINMUX('J', 4, AF8)>; /* TIM8_CH4 */
301			bias-pull-down;
302			drive-push-pull;
303			slew-rate = <0>;
304		};
305	};
306
307	pwm8_sleep_pins_a: pwm8-sleep-0 {
308		pins {
309			pinmux = <STM32_PINMUX('J', 5, ANALOG)>, /* TIM8_CH1 */
310				 <STM32_PINMUX('J', 4, ANALOG)>; /* TIM8_CH4 */
311		};
312	};
313
314	pwm12_pins_a: pwm12-0 {
315		pins {
316			pinmux = <STM32_PINMUX('B', 11, AF9)>; /* TIM12_CH2 */
317			bias-pull-down;
318			drive-push-pull;
319			slew-rate = <0>;
320		};
321	};
322
323	pwm12_sleep_pins_a: pwm12-sleep-0 {
324		pins {
325			pinmux = <STM32_PINMUX('B', 11, ANALOG)>; /* TIM12_CH2 */
326		};
327	};
328
329	sdmmc1_b4_pins_a: sdmmc1-b4-0 {
330		pins1 {
331			pinmux = <STM32_PINMUX('E', 4, AF10)>, /* SDMMC1_D0 */
332				 <STM32_PINMUX('E', 5, AF10)>, /* SDMMC1_D1 */
333				 <STM32_PINMUX('E', 0, AF10)>, /* SDMMC1_D2 */
334				 <STM32_PINMUX('E', 1, AF10)>, /* SDMMC1_D3 */
335				 <STM32_PINMUX('E', 2, AF10)>; /* SDMMC1_CMD */
336			slew-rate = <2>;
337			drive-push-pull;
338			bias-disable;
339		};
340		pins2 {
341			pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC1_CK */
342			slew-rate = <3>;
343			drive-push-pull;
344			bias-disable;
345		};
346	};
347
348	sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
349		pins1 {
350			pinmux = <STM32_PINMUX('E', 4, AF10)>, /* SDMMC1_D0 */
351				 <STM32_PINMUX('E', 5, AF10)>, /* SDMMC1_D1 */
352				 <STM32_PINMUX('E', 0, AF10)>, /* SDMMC1_D2 */
353				 <STM32_PINMUX('E', 1, AF10)>; /* SDMMC1_D3 */
354			slew-rate = <2>;
355			drive-push-pull;
356			bias-disable;
357		};
358		pins2 {
359			pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC1_CK */
360			slew-rate = <3>;
361			drive-push-pull;
362			bias-disable;
363		};
364		pins3 {
365			pinmux = <STM32_PINMUX('E', 2, AF10)>; /* SDMMC1_CMD */
366			slew-rate = <2>;
367			drive-open-drain;
368			bias-disable;
369		};
370	};
371
372	sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
373		pins {
374			pinmux = <STM32_PINMUX('E', 4, ANALOG)>, /* SDMMC1_D0 */
375				 <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC1_D1 */
376				 <STM32_PINMUX('E', 0, ANALOG)>, /* SDMMC1_D2 */
377				 <STM32_PINMUX('E', 1, ANALOG)>, /* SDMMC1_D3 */
378				 <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC1_CK */
379				 <STM32_PINMUX('E', 2, ANALOG)>; /* SDMMC1_CMD */
380		};
381	};
382
383	spi3_pins_a: spi3-0 {
384		pins1 {
385			pinmux = <STM32_PINMUX('B', 7, AF1)>, /* SPI3_SCK */
386				 <STM32_PINMUX('B', 8, AF1)>; /* SPI3_MOSI */
387			drive-push-pull;
388			bias-disable;
389			slew-rate = <1>;
390		};
391		pins2 {
392			pinmux = <STM32_PINMUX('B', 10, AF1)>; /* SPI3_MISO */
393			bias-disable;
394		};
395	};
396
397	spi3_sleep_pins_a: spi3-sleep-0 {
398		pins1 {
399			pinmux = <STM32_PINMUX('B', 7, ANALOG)>, /* SPI3_SCK */
400				 <STM32_PINMUX('B', 8, ANALOG)>, /* SPI3_MOSI */
401				 <STM32_PINMUX('B', 10, ANALOG)>; /* SPI3_MISO */
402		};
403	};
404
405	tim10_counter_pins_a: tim10-counter-0 {
406		pins {
407			pinmux = <STM32_PINMUX('B', 9, AF9)>; /* TIM10_CH1 */
408			bias-disable;
409		};
410	};
411
412	tim10_counter_sleep_pins_a: tim10-counter-sleep-0 {
413		pins {
414			pinmux = <STM32_PINMUX('B', 9, ANALOG)>; /* TIM10_CH1 */
415			bias-disable;
416		};
417	};
418
419	usart2_pins_a: usart2-0 {
420		pins1 {
421			pinmux = <STM32_PINMUX('A', 4, AF6)>; /* USART2_TX */
422			bias-disable;
423			drive-push-pull;
424			slew-rate = <0>;
425		};
426		pins2 {
427			pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */
428			bias-disable;
429		};
430	};
431
432	usart2_idle_pins_a: usart2-idle-0 {
433		pins1 {
434			pinmux = <STM32_PINMUX('A', 4, ANALOG)>; /* USART2_TX */
435		};
436		pins2 {
437			pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */
438			bias-disable;
439		};
440	};
441
442	usart2_sleep_pins_a: usart2-sleep-0 {
443		pins {
444			pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* USART2_TX */
445				 <STM32_PINMUX('A', 8, ANALOG)>; /* USART2_RX */
446		};
447	};
448
449	usart6_pins_a: usart6-0 {
450		pins1 {
451			pinmux = <STM32_PINMUX('F', 13, AF3)>, /* USART6_TX */
452				 <STM32_PINMUX('G', 5, AF3)>;  /* USART6_RTS */
453			bias-disable;
454			drive-push-pull;
455			slew-rate = <0>;
456		};
457		pins2 {
458			pinmux = <STM32_PINMUX('F', 14, AF3)>, /* USART6_RX */
459				 <STM32_PINMUX('F', 15, AF3)>; /* USART6_CTS_NSS */
460			bias-pull-up;
461		};
462	};
463
464	usart6_idle_pins_a: usart6-idle-0 {
465		pins1 {
466			pinmux = <STM32_PINMUX('F', 13, ANALOG)>, /* USART6_TX */
467				 <STM32_PINMUX('F', 15, ANALOG)>; /* USART6_CTS_NSS */
468		};
469		pins2 {
470			pinmux = <STM32_PINMUX('G', 5, AF3)>; /* USART6_RTS */
471			bias-disable;
472			drive-push-pull;
473			slew-rate = <0>;
474		};
475		pins3 {
476			pinmux = <STM32_PINMUX('F', 14, AF3)>; /* USART6_RX */
477			bias-pull-up;
478		};
479	};
480
481	usart6_sleep_pins_a: usart6-sleep-0 {
482		pins {
483			pinmux = <STM32_PINMUX('F', 13, ANALOG)>, /* USART6_TX */
484				 <STM32_PINMUX('G', 5, ANALOG)>,  /* USART6_RTS */
485				 <STM32_PINMUX('F', 15, ANALOG)>, /* USART6_CTS_NSS */
486				 <STM32_PINMUX('F', 14, ANALOG)>; /* USART6_RX */
487		};
488	};
489};
490
491&pinctrl_z {
492	i2c8_pins_a: i2c8-0 {
493		pins {
494			pinmux = <STM32_PINMUX('Z', 4, AF8)>, /* I2C8_SCL */
495				 <STM32_PINMUX('Z', 3, AF8)>; /* I2C8_SDA */
496			bias-disable;
497			drive-open-drain;
498			slew-rate = <0>;
499		};
500	};
501
502	i2c8_sleep_pins_a: i2c8-sleep-0 {
503		pins {
504			pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C8_SCL */
505				 <STM32_PINMUX('Z', 3, ANALOG)>; /* I2C8_SDA */
506		};
507	};
508};
509
510&pinctrl_z {
511	spi8_pins_a: spi8-0 {
512		pins1 {
513			pinmux = <STM32_PINMUX('Z', 2, AF3)>, /* SPI8_SCK */
514				 <STM32_PINMUX('Z', 0, AF3)>; /* SPI8_MOSI */
515			drive-push-pull;
516			bias-disable;
517			slew-rate = <1>;
518		};
519		pins2 {
520			pinmux = <STM32_PINMUX('Z', 1, AF3)>; /* SPI8_MISO */
521			bias-disable;
522		};
523	};
524
525	spi8_sleep_pins_a: spi8-sleep-0 {
526		pins1 {
527			pinmux = <STM32_PINMUX('Z', 2, ANALOG)>, /* SPI8_SCK */
528				 <STM32_PINMUX('Z', 0, ANALOG)>, /* SPI8_MOSI */
529				 <STM32_PINMUX('Z', 1, ANALOG)>; /* SPI8_MISO */
530		};
531	};
532};
533