xref: /linux/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi (revision 23ca32e4ead48f68e37000f2552b973ef1439acb) 
1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/pinctrl/stm32-pinfunc.h>
7
8&pinctrl {
9	eth2_rgmii_pins_a: eth2-rgmii-0 {
10		pins1 {
11			pinmux = <STM32_PINMUX('C', 7, AF10)>, /* ETH_RGMII_TXD0 */
12				 <STM32_PINMUX('C', 8, AF10)>, /* ETH_RGMII_TXD1 */
13				 <STM32_PINMUX('C', 9, AF10)>, /* ETH_RGMII_TXD2 */
14				 <STM32_PINMUX('C', 10, AF10)>, /* ETH_RGMII_TXD3 */
15				 <STM32_PINMUX('C', 4, AF10)>; /* ETH_RGMII_TX_CTL */
16			bias-disable;
17			drive-push-pull;
18			slew-rate = <3>;
19		};
20		pins2 {
21			pinmux = <STM32_PINMUX('F', 8, AF10)>, /* ETH_RGMII_CLK125 */
22				 <STM32_PINMUX('F', 7, AF10)>, /* ETH_RGMII_GTX_CLK */
23				 <STM32_PINMUX('C', 6, AF10)>; /* ETH_MDC */
24			bias-disable;
25			drive-push-pull;
26			slew-rate = <3>;
27		};
28		pins3 {
29			pinmux = <STM32_PINMUX('C', 5, AF10)>; /* ETH_MDIO */
30			bias-disable;
31			drive-push-pull;
32			slew-rate = <0>;
33		};
34		pins4 {
35			pinmux = <STM32_PINMUX('G', 0, AF10)>, /* ETH_RGMII_RXD0 */
36				 <STM32_PINMUX('C', 12, AF10)>, /* ETH_RGMII_RXD1 */
37				 <STM32_PINMUX('F', 9, AF10)>, /* ETH_RGMII_RXD2 */
38				 <STM32_PINMUX('C', 11, AF10)>, /* ETH_RGMII_RXD3 */
39				 <STM32_PINMUX('C', 3, AF10)>; /* ETH_RGMII_RX_CTL */
40			bias-disable;
41		};
42		pins5 {
43			pinmux = <STM32_PINMUX('F', 6, AF10)>; /* ETH_RGMII_RX_CLK */
44			bias-disable;
45		};
46	};
47
48	eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 {
49		pins {
50			pinmux = <STM32_PINMUX('C', 7, ANALOG)>, /* ETH_RGMII_TXD0 */
51				 <STM32_PINMUX('C', 8, ANALOG)>, /* ETH_RGMII_TXD1 */
52				 <STM32_PINMUX('C', 9, ANALOG)>, /* ETH_RGMII_TXD2 */
53				 <STM32_PINMUX('C', 10, ANALOG)>, /* ETH_RGMII_TXD3 */
54				 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_TX_CTL */
55				 <STM32_PINMUX('F', 8, ANALOG)>, /* ETH_RGMII_CLK125 */
56				 <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RGMII_GTX_CLK */
57				 <STM32_PINMUX('C', 6, ANALOG)>, /* ETH_MDC */
58				 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_MDIO */
59				 <STM32_PINMUX('G', 0, ANALOG)>, /* ETH_RGMII_RXD0 */
60				 <STM32_PINMUX('C', 12, ANALOG)>, /* ETH_RGMII_RXD1 */
61				 <STM32_PINMUX('F', 9, ANALOG)>, /* ETH_RGMII_RXD2 */
62				 <STM32_PINMUX('C', 11, ANALOG)>, /* ETH_RGMII_RXD3 */
63				 <STM32_PINMUX('C', 3, ANALOG)>, /* ETH_RGMII_RX_CTL */
64				 <STM32_PINMUX('F', 6, ANALOG)>; /* ETH_RGMII_RX_CLK */
65		};
66	};
67
68	i2c2_pins_a: i2c2-0 {
69		pins {
70			pinmux = <STM32_PINMUX('B', 5, AF9)>, /* I2C2_SCL */
71				 <STM32_PINMUX('B', 4, AF9)>; /* I2C2_SDA */
72			bias-disable;
73			drive-open-drain;
74			slew-rate = <0>;
75		};
76	};
77
78	i2c2_sleep_pins_a: i2c2-sleep-0 {
79		pins {
80			pinmux = <STM32_PINMUX('B', 5, ANALOG)>, /* I2C2_SCL */
81				 <STM32_PINMUX('B', 4, ANALOG)>; /* I2C2_SDA */
82		};
83	};
84
85	ospi_port1_clk_pins_a: ospi-port1-clk-0 {
86		pins {
87			pinmux = <STM32_PINMUX('D', 0, AF10)>; /* OSPI1_CLK */
88			bias-disable;
89			drive-push-pull;
90			slew-rate = <2>;
91		};
92	};
93
94	ospi_port1_clk_sleep_pins_a: ospi-port1-clk-sleep-0 {
95		pins {
96			pinmux = <STM32_PINMUX('D', 0, ANALOG)>; /* OSPI1_CLK */
97		};
98	};
99
100	ospi_port1_cs0_pins_a: ospi-port1-cs0-0 {
101		pins {
102			pinmux = <STM32_PINMUX('D', 3, AF10)>; /* OSPI_NCS0 */
103			bias-pull-up;
104			drive-push-pull;
105			slew-rate = <0>;
106		};
107	};
108
109	ospi_port1_cs0_sleep_pins_a: ospi-port1-cs0-sleep-0 {
110		pins {
111			pinmux = <STM32_PINMUX('D', 3, ANALOG)>; /* OSPI_NCS0 */
112		};
113	};
114
115	ospi_port1_io03_pins_a: ospi-port1-io03-0 {
116		pins {
117			pinmux = <STM32_PINMUX('D', 4, AF10)>, /* OSPI_IO0 */
118				 <STM32_PINMUX('D', 5, AF10)>, /* OSPI_IO1 */
119				 <STM32_PINMUX('D', 6, AF10)>, /* OSPI_IO2 */
120				 <STM32_PINMUX('D', 7, AF10)>; /* OSPI_IO3 */
121			bias-disable;
122			drive-push-pull;
123			slew-rate = <0>;
124		};
125	};
126
127	ospi_port1_io03_sleep_pins_a: ospi-port1-io03-sleep-0 {
128		pins {
129			pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* OSPI_IO0 */
130				 <STM32_PINMUX('D', 5, ANALOG)>, /* OSPI_IO1 */
131				 <STM32_PINMUX('D', 6, ANALOG)>, /* OSPI_IO2 */
132				 <STM32_PINMUX('D', 7, ANALOG)>; /* OSPI_IO3 */
133		};
134	};
135
136	sdmmc1_b4_pins_a: sdmmc1-b4-0 {
137		pins1 {
138			pinmux = <STM32_PINMUX('E', 4, AF10)>, /* SDMMC1_D0 */
139				 <STM32_PINMUX('E', 5, AF10)>, /* SDMMC1_D1 */
140				 <STM32_PINMUX('E', 0, AF10)>, /* SDMMC1_D2 */
141				 <STM32_PINMUX('E', 1, AF10)>, /* SDMMC1_D3 */
142				 <STM32_PINMUX('E', 2, AF10)>; /* SDMMC1_CMD */
143			slew-rate = <2>;
144			drive-push-pull;
145			bias-disable;
146		};
147		pins2 {
148			pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC1_CK */
149			slew-rate = <3>;
150			drive-push-pull;
151			bias-disable;
152		};
153	};
154
155	sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
156		pins1 {
157			pinmux = <STM32_PINMUX('E', 4, AF10)>, /* SDMMC1_D0 */
158				 <STM32_PINMUX('E', 5, AF10)>, /* SDMMC1_D1 */
159				 <STM32_PINMUX('E', 0, AF10)>, /* SDMMC1_D2 */
160				 <STM32_PINMUX('E', 1, AF10)>; /* SDMMC1_D3 */
161			slew-rate = <2>;
162			drive-push-pull;
163			bias-disable;
164		};
165		pins2 {
166			pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC1_CK */
167			slew-rate = <3>;
168			drive-push-pull;
169			bias-disable;
170		};
171		pins3 {
172			pinmux = <STM32_PINMUX('E', 2, AF10)>; /* SDMMC1_CMD */
173			slew-rate = <2>;
174			drive-open-drain;
175			bias-disable;
176		};
177	};
178
179	sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
180		pins {
181			pinmux = <STM32_PINMUX('E', 4, ANALOG)>, /* SDMMC1_D0 */
182				 <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC1_D1 */
183				 <STM32_PINMUX('E', 0, ANALOG)>, /* SDMMC1_D2 */
184				 <STM32_PINMUX('E', 1, ANALOG)>, /* SDMMC1_D3 */
185				 <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC1_CK */
186				 <STM32_PINMUX('E', 2, ANALOG)>; /* SDMMC1_CMD */
187		};
188	};
189
190	spi3_pins_a: spi3-0 {
191		pins1 {
192			pinmux = <STM32_PINMUX('B', 7, AF1)>, /* SPI3_SCK */
193				 <STM32_PINMUX('B', 8, AF1)>; /* SPI3_MOSI */
194			drive-push-pull;
195			bias-disable;
196			slew-rate = <1>;
197		};
198		pins2 {
199			pinmux = <STM32_PINMUX('B', 10, AF1)>; /* SPI3_MISO */
200			bias-disable;
201		};
202	};
203
204	spi3_sleep_pins_a: spi3-sleep-0 {
205		pins1 {
206			pinmux = <STM32_PINMUX('B', 7, ANALOG)>, /* SPI3_SCK */
207				 <STM32_PINMUX('B', 8, ANALOG)>, /* SPI3_MOSI */
208				 <STM32_PINMUX('B', 10, ANALOG)>; /* SPI3_MISO */
209		};
210	};
211
212	usart2_pins_a: usart2-0 {
213		pins1 {
214			pinmux = <STM32_PINMUX('A', 4, AF6)>; /* USART2_TX */
215			bias-disable;
216			drive-push-pull;
217			slew-rate = <0>;
218		};
219		pins2 {
220			pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */
221			bias-disable;
222		};
223	};
224
225	usart2_idle_pins_a: usart2-idle-0 {
226		pins1 {
227			pinmux = <STM32_PINMUX('A', 4, ANALOG)>; /* USART2_TX */
228		};
229		pins2 {
230			pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */
231			bias-disable;
232		};
233	};
234
235	usart2_sleep_pins_a: usart2-sleep-0 {
236		pins {
237			pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* USART2_TX */
238				 <STM32_PINMUX('A', 8, ANALOG)>; /* USART2_RX */
239		};
240	};
241
242	usart6_pins_a: usart6-0 {
243		pins1 {
244			pinmux = <STM32_PINMUX('F', 13, AF3)>, /* USART6_TX */
245				 <STM32_PINMUX('G', 5, AF3)>;  /* USART6_RTS */
246			bias-disable;
247			drive-push-pull;
248			slew-rate = <0>;
249		};
250		pins2 {
251			pinmux = <STM32_PINMUX('F', 14, AF3)>, /* USART6_RX */
252				 <STM32_PINMUX('F', 15, AF3)>; /* USART6_CTS_NSS */
253			bias-pull-up;
254		};
255	};
256
257	usart6_idle_pins_a: usart6-idle-0 {
258		pins1 {
259			pinmux = <STM32_PINMUX('F', 13, ANALOG)>, /* USART6_TX */
260				 <STM32_PINMUX('F', 15, ANALOG)>; /* USART6_CTS_NSS */
261		};
262		pins2 {
263			pinmux = <STM32_PINMUX('G', 5, AF3)>; /* USART6_RTS */
264			bias-disable;
265			drive-push-pull;
266			slew-rate = <0>;
267		};
268		pins3 {
269			pinmux = <STM32_PINMUX('F', 14, AF3)>; /* USART6_RX */
270			bias-pull-up;
271		};
272	};
273
274	usart6_sleep_pins_a: usart6-sleep-0 {
275		pins {
276			pinmux = <STM32_PINMUX('F', 13, ANALOG)>, /* USART6_TX */
277				 <STM32_PINMUX('G', 5, ANALOG)>,  /* USART6_RTS */
278				 <STM32_PINMUX('F', 15, ANALOG)>, /* USART6_CTS_NSS */
279				 <STM32_PINMUX('F', 14, ANALOG)>; /* USART6_RX */
280		};
281	};
282};
283
284&pinctrl_z {
285	i2c8_pins_a: i2c8-0 {
286		pins {
287			pinmux = <STM32_PINMUX('Z', 4, AF8)>, /* I2C8_SCL */
288				 <STM32_PINMUX('Z', 3, AF8)>; /* I2C8_SDA */
289			bias-disable;
290			drive-open-drain;
291			slew-rate = <0>;
292		};
293	};
294
295	i2c8_sleep_pins_a: i2c8-sleep-0 {
296		pins {
297			pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C8_SCL */
298				 <STM32_PINMUX('Z', 3, ANALOG)>; /* I2C8_SDA */
299		};
300	};
301};
302
303&pinctrl_z {
304	spi8_pins_a: spi8-0 {
305		pins1 {
306			pinmux = <STM32_PINMUX('Z', 2, AF3)>, /* SPI8_SCK */
307				 <STM32_PINMUX('Z', 0, AF3)>; /* SPI8_MOSI */
308			drive-push-pull;
309			bias-disable;
310			slew-rate = <1>;
311		};
312		pins2 {
313			pinmux = <STM32_PINMUX('Z', 1, AF3)>; /* SPI8_MISO */
314			bias-disable;
315		};
316	};
317
318	spi8_sleep_pins_a: spi8-sleep-0 {
319		pins1 {
320			pinmux = <STM32_PINMUX('Z', 2, ANALOG)>, /* SPI8_SCK */
321				 <STM32_PINMUX('Z', 0, ANALOG)>, /* SPI8_MOSI */
322				 <STM32_PINMUX('Z', 1, ANALOG)>; /* SPI8_MISO */
323		};
324	};
325};
326