1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2025 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/clock/st,stm32mp25-rcc.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/regulator/st,stm32mp25-regulator.h> 9#include <dt-bindings/reset/st,stm32mp25-rcc.h> 10 11/ { 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a35"; 21 reg = <0>; 22 device_type = "cpu"; 23 enable-method = "psci"; 24 power-domains = <&cpu0_pd>; 25 power-domain-names = "psci"; 26 }; 27 }; 28 29 arm-pmu { 30 compatible = "arm,cortex-a35-pmu"; 31 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 32 interrupt-affinity = <&cpu0>; 33 interrupt-parent = <&intc>; 34 }; 35 36 arm_wdt: watchdog { 37 compatible = "arm,smc-wdt"; 38 arm,smc-id = <0xb200005a>; 39 status = "disabled"; 40 }; 41 42 clk_dsi_txbyte: clock-0 { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <0>; 46 }; 47 48 clk_flexgen_27_fixed: clk-54000000 { 49 #clock-cells = <0>; 50 compatible = "fixed-clock"; 51 clock-frequency = <54000000>; 52 }; 53 54 clk_rcbsec: clk-64000000 { 55 compatible = "fixed-clock"; 56 #clock-cells = <0>; 57 clock-frequency = <64000000>; 58 }; 59 60 firmware { 61 optee: optee { 62 compatible = "linaro,optee-tz"; 63 method = "smc"; 64 interrupt-parent = <&intc>; 65 interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 66 }; 67 68 scmi { 69 compatible = "linaro,scmi-optee"; 70 #address-cells = <1>; 71 #size-cells = <0>; 72 linaro,optee-channel-id = <0>; 73 74 scmi_clk: protocol@14 { 75 reg = <0x14>; 76 #clock-cells = <1>; 77 }; 78 79 scmi_reset: protocol@16 { 80 reg = <0x16>; 81 #reset-cells = <1>; 82 }; 83 84 scmi_voltd: protocol@17 { 85 reg = <0x17>; 86 87 scmi_regu: regulators { 88 #address-cells = <1>; 89 #size-cells = <0>; 90 91 scmi_vddio1: regulator@0 { 92 reg = <VOLTD_SCMI_VDDIO1>; 93 regulator-name = "vddio1"; 94 }; 95 scmi_vddio2: regulator@1 { 96 reg = <VOLTD_SCMI_VDDIO2>; 97 regulator-name = "vddio2"; 98 }; 99 scmi_vddio3: regulator@2 { 100 reg = <VOLTD_SCMI_VDDIO3>; 101 regulator-name = "vddio3"; 102 }; 103 scmi_vddio4: regulator@3 { 104 reg = <VOLTD_SCMI_VDDIO4>; 105 regulator-name = "vddio4"; 106 }; 107 scmi_vdd33ucpd: regulator@5 { 108 reg = <VOLTD_SCMI_UCPD>; 109 regulator-name = "vdd33ucpd"; 110 }; 111 scmi_vdda18adc: regulator@7 { 112 reg = <VOLTD_SCMI_ADC>; 113 regulator-name = "vdda18adc"; 114 }; 115 }; 116 }; 117 }; 118 }; 119 120 psci { 121 compatible = "arm,psci-1.0"; 122 method = "smc"; 123 124 cpu0_pd: power-domain-cpu0 { 125 #power-domain-cells = <0>; 126 power-domains = <&cluster_pd>; 127 }; 128 129 cluster_pd: power-domain-cluster { 130 #power-domain-cells = <0>; 131 power-domains = <&ret_pd>; 132 }; 133 134 ret_pd: power-domain-retention { 135 #power-domain-cells = <0>; 136 }; 137 }; 138 139 timer { 140 compatible = "arm,armv8-timer"; 141 interrupt-parent = <&intc>; 142 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 143 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 144 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 145 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 146 always-on; 147 }; 148 149 soc@0 { 150 compatible = "simple-bus"; 151 ranges = <0x0 0x0 0x0 0x80000000>; 152 interrupt-parent = <&intc>; 153 #address-cells = <1>; 154 #size-cells = <1>; 155 156 hpdma: dma-controller@40400000 { 157 compatible = "st,stm32mp25-dma3"; 158 reg = <0x40400000 0x1000>; 159 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 175 clocks = <&scmi_clk CK_SCMI_HPDMA1>; 176 #dma-cells = <3>; 177 }; 178 179 hpdma2: dma-controller@40410000 { 180 compatible = "st,stm32mp25-dma3"; 181 reg = <0x40410000 0x1000>; 182 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 198 clocks = <&scmi_clk CK_SCMI_HPDMA2>; 199 #dma-cells = <3>; 200 }; 201 202 hpdma3: dma-controller@40420000 { 203 compatible = "st,stm32mp25-dma3"; 204 reg = <0x40420000 0x1000>; 205 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 221 clocks = <&scmi_clk CK_SCMI_HPDMA3>; 222 #dma-cells = <3>; 223 }; 224 225 rifsc: bus@42080000 { 226 compatible = "st,stm32mp25-rifsc", "simple-bus"; 227 reg = <0x42080000 0x1000>; 228 ranges; 229 #address-cells = <1>; 230 #size-cells = <1>; 231 #access-controller-cells = <1>; 232 233 i2s2: audio-controller@400b0000 { 234 compatible = "st,stm32mp25-i2s"; 235 reg = <0x400b0000 0x400>; 236 #sound-dai-cells = <0>; 237 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&rcc CK_BUS_SPI2>, <&rcc CK_KER_SPI2>; 239 clock-names = "pclk", "i2sclk"; 240 resets = <&rcc SPI2_R>; 241 dmas = <&hpdma 51 0x43 0x12>, 242 <&hpdma 52 0x43 0x21>; 243 dma-names = "rx", "tx"; 244 access-controllers = <&rifsc 23>; 245 status = "disabled"; 246 }; 247 248 spi2: spi@400b0000 { 249 compatible = "st,stm32mp25-spi"; 250 reg = <0x400b0000 0x400>; 251 #address-cells = <1>; 252 #size-cells = <0>; 253 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 254 clocks = <&rcc CK_KER_SPI2>; 255 resets = <&rcc SPI2_R>; 256 dmas = <&hpdma 51 0x20 0x3012>, 257 <&hpdma 52 0x20 0x3021>; 258 dma-names = "rx", "tx"; 259 access-controllers = <&rifsc 23>; 260 power-domains = <&cluster_pd>; 261 status = "disabled"; 262 }; 263 264 i2s3: audio-controller@400c0000 { 265 compatible = "st,stm32mp25-i2s"; 266 reg = <0x400c0000 0x400>; 267 #sound-dai-cells = <0>; 268 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 269 clocks = <&rcc CK_BUS_SPI3>, <&rcc CK_KER_SPI3>; 270 clock-names = "pclk", "i2sclk"; 271 resets = <&rcc SPI3_R>; 272 dmas = <&hpdma 53 0x43 0x12>, 273 <&hpdma 54 0x43 0x21>; 274 dma-names = "rx", "tx"; 275 access-controllers = <&rifsc 24>; 276 status = "disabled"; 277 }; 278 279 spi3: spi@400c0000 { 280 compatible = "st,stm32mp25-spi"; 281 reg = <0x400c0000 0x400>; 282 #address-cells = <1>; 283 #size-cells = <0>; 284 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&rcc CK_KER_SPI3>; 286 resets = <&rcc SPI3_R>; 287 dmas = <&hpdma 53 0x20 0x3012>, 288 <&hpdma 54 0x20 0x3021>; 289 dma-names = "rx", "tx"; 290 access-controllers = <&rifsc 24>; 291 power-domains = <&cluster_pd>; 292 status = "disabled"; 293 }; 294 295 spdifrx: audio-controller@400d0000 { 296 compatible = "st,stm32h7-spdifrx"; 297 reg = <0x400d0000 0x400>; 298 #sound-dai-cells = <0>; 299 clocks = <&rcc CK_KER_SPDIFRX>; 300 clock-names = "kclk"; 301 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 302 dmas = <&hpdma 71 0x43 0x212>, 303 <&hpdma 72 0x43 0x212>; 304 dma-names = "rx", "rx-ctrl"; 305 access-controllers = <&rifsc 30>; 306 status = "disabled"; 307 }; 308 309 usart2: serial@400e0000 { 310 compatible = "st,stm32h7-uart"; 311 reg = <0x400e0000 0x400>; 312 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&rcc CK_KER_USART2>; 314 dmas = <&hpdma 11 0x20 0x10012>, 315 <&hpdma 12 0x20 0x3021>; 316 dma-names = "rx", "tx"; 317 access-controllers = <&rifsc 32>; 318 status = "disabled"; 319 }; 320 321 usart3: serial@400f0000 { 322 compatible = "st,stm32h7-uart"; 323 reg = <0x400f0000 0x400>; 324 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 325 clocks = <&rcc CK_KER_USART3>; 326 dmas = <&hpdma 13 0x20 0x10012>, 327 <&hpdma 14 0x20 0x3021>; 328 dma-names = "rx", "tx"; 329 access-controllers = <&rifsc 33>; 330 status = "disabled"; 331 }; 332 333 uart4: serial@40100000 { 334 compatible = "st,stm32h7-uart"; 335 reg = <0x40100000 0x400>; 336 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 337 clocks = <&rcc CK_KER_UART4>; 338 dmas = <&hpdma 15 0x20 0x10012>, 339 <&hpdma 16 0x20 0x3021>; 340 dma-names = "rx", "tx"; 341 access-controllers = <&rifsc 34>; 342 status = "disabled"; 343 }; 344 345 uart5: serial@40110000 { 346 compatible = "st,stm32h7-uart"; 347 reg = <0x40110000 0x400>; 348 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&rcc CK_KER_UART5>; 350 dmas = <&hpdma 17 0x20 0x10012>, 351 <&hpdma 18 0x20 0x3021>; 352 dma-names = "rx", "tx"; 353 access-controllers = <&rifsc 35>; 354 status = "disabled"; 355 }; 356 357 i2c1: i2c@40120000 { 358 compatible = "st,stm32mp25-i2c"; 359 reg = <0x40120000 0x400>; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 interrupt-names = "event"; 363 interrupts-extended = <&exti1 21 IRQ_TYPE_LEVEL_HIGH>; 364 clocks = <&rcc CK_KER_I2C1>; 365 resets = <&rcc I2C1_R>; 366 dmas = <&hpdma 27 0x20 0x3012>, 367 <&hpdma 28 0x20 0x3021>; 368 dma-names = "rx", "tx"; 369 access-controllers = <&rifsc 41>; 370 power-domains = <&cluster_pd>; 371 i2c-analog-filter; 372 wakeup-source; 373 status = "disabled"; 374 }; 375 376 i2c2: i2c@40130000 { 377 compatible = "st,stm32mp25-i2c"; 378 reg = <0x40130000 0x400>; 379 #address-cells = <1>; 380 #size-cells = <0>; 381 interrupt-names = "event"; 382 interrupts-extended = <&exti1 22 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&rcc CK_KER_I2C2>; 384 resets = <&rcc I2C2_R>; 385 dmas = <&hpdma 30 0x20 0x3012>, 386 <&hpdma 31 0x20 0x3021>; 387 dma-names = "rx", "tx"; 388 access-controllers = <&rifsc 42>; 389 power-domains = <&cluster_pd>; 390 i2c-analog-filter; 391 wakeup-source; 392 status = "disabled"; 393 }; 394 395 i2c7: i2c@40180000 { 396 compatible = "st,stm32mp25-i2c"; 397 reg = <0x40180000 0x400>; 398 #address-cells = <1>; 399 #size-cells = <0>; 400 interrupt-names = "event"; 401 interrupts-extended = <&exti1 50 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&rcc CK_KER_I2C7>; 403 resets = <&rcc I2C7_R>; 404 dmas = <&hpdma 45 0x20 0x3012>, 405 <&hpdma 46 0x20 0x3021>; 406 dma-names = "rx", "tx"; 407 access-controllers = <&rifsc 47>; 408 power-domains = <&cluster_pd>; 409 i2c-analog-filter; 410 wakeup-source; 411 status = "disabled"; 412 }; 413 414 usart6: serial@40220000 { 415 compatible = "st,stm32h7-uart"; 416 reg = <0x40220000 0x400>; 417 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&rcc CK_KER_USART6>; 419 dmas = <&hpdma 19 0x20 0x10012>, 420 <&hpdma 20 0x20 0x3021>; 421 dma-names = "rx", "tx"; 422 access-controllers = <&rifsc 36>; 423 status = "disabled"; 424 }; 425 426 i2s1: audio-controller@40230000 { 427 compatible = "st,stm32mp25-i2s"; 428 reg = <0x40230000 0x400>; 429 #sound-dai-cells = <0>; 430 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 431 clocks = <&rcc CK_BUS_SPI1>, <&rcc CK_KER_SPI1>; 432 clock-names = "pclk", "i2sclk"; 433 resets = <&rcc SPI1_R>; 434 dmas = <&hpdma 49 0x43 0x12>, 435 <&hpdma 50 0x43 0x21>; 436 dma-names = "rx", "tx"; 437 access-controllers = <&rifsc 22>; 438 status = "disabled"; 439 }; 440 441 spi1: spi@40230000 { 442 compatible = "st,stm32mp25-spi"; 443 reg = <0x40230000 0x400>; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 447 clocks = <&rcc CK_KER_SPI1>; 448 resets = <&rcc SPI1_R>; 449 dmas = <&hpdma 49 0x20 0x3012>, 450 <&hpdma 50 0x20 0x3021>; 451 dma-names = "rx", "tx"; 452 access-controllers = <&rifsc 22>; 453 power-domains = <&cluster_pd>; 454 status = "disabled"; 455 }; 456 457 spi4: spi@40240000 { 458 compatible = "st,stm32mp25-spi"; 459 reg = <0x40240000 0x400>; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&rcc CK_KER_SPI4>; 464 resets = <&rcc SPI4_R>; 465 dmas = <&hpdma 55 0x20 0x3012>, 466 <&hpdma 56 0x20 0x3021>; 467 dma-names = "rx", "tx"; 468 access-controllers = <&rifsc 25>; 469 power-domains = <&cluster_pd>; 470 status = "disabled"; 471 }; 472 473 spi5: spi@40280000 { 474 compatible = "st,stm32mp25-spi"; 475 reg = <0x40280000 0x400>; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&rcc CK_KER_SPI5>; 480 resets = <&rcc SPI5_R>; 481 dmas = <&hpdma 57 0x20 0x3012>, 482 <&hpdma 58 0x20 0x3021>; 483 dma-names = "rx", "tx"; 484 access-controllers = <&rifsc 26>; 485 power-domains = <&cluster_pd>; 486 status = "disabled"; 487 }; 488 489 sai1: sai@40290000 { 490 compatible = "st,stm32mp25-sai"; 491 reg = <0x40290000 0x4>, <0x4029a3f0 0x10>; 492 ranges = <0 0x40290000 0x400>; 493 #address-cells = <1>; 494 #size-cells = <1>; 495 clocks = <&rcc CK_BUS_SAI1>; 496 clock-names = "pclk"; 497 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 498 resets = <&rcc SAI1_R>; 499 access-controllers = <&rifsc 49>; 500 status = "disabled"; 501 502 sai1a: audio-controller@40290004 { 503 compatible = "st,stm32-sai-sub-a"; 504 reg = <0x4 0x20>; 505 #sound-dai-cells = <0>; 506 clocks = <&rcc CK_KER_SAI1>; 507 clock-names = "sai_ck"; 508 dmas = <&hpdma 73 0x43 0x21>; 509 status = "disabled"; 510 }; 511 512 sai1b: audio-controller@40290024 { 513 compatible = "st,stm32-sai-sub-b"; 514 reg = <0x24 0x20>; 515 #sound-dai-cells = <0>; 516 clocks = <&rcc CK_KER_SAI1>; 517 clock-names = "sai_ck"; 518 dmas = <&hpdma 74 0x43 0x12>; 519 status = "disabled"; 520 }; 521 }; 522 523 sai2: sai@402a0000 { 524 compatible = "st,stm32mp25-sai"; 525 reg = <0x402a0000 0x4>, <0x402aa3f0 0x10>; 526 ranges = <0 0x402a0000 0x400>; 527 #address-cells = <1>; 528 #size-cells = <1>; 529 clocks = <&rcc CK_BUS_SAI2>; 530 clock-names = "pclk"; 531 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 532 resets = <&rcc SAI2_R>; 533 access-controllers = <&rifsc 50>; 534 status = "disabled"; 535 536 sai2a: audio-controller@402a0004 { 537 compatible = "st,stm32-sai-sub-a"; 538 reg = <0x4 0x20>; 539 #sound-dai-cells = <0>; 540 clocks = <&rcc CK_KER_SAI2>; 541 clock-names = "sai_ck"; 542 dmas = <&hpdma 75 0x43 0x21>; 543 status = "disabled"; 544 }; 545 546 sai2b: audio-controller@402a0024 { 547 compatible = "st,stm32-sai-sub-b"; 548 reg = <0x24 0x20>; 549 #sound-dai-cells = <0>; 550 clocks = <&rcc CK_KER_SAI2>; 551 clock-names = "sai_ck"; 552 dmas = <&hpdma 76 0x43 0x12>; 553 status = "disabled"; 554 }; 555 }; 556 557 sai3: sai@402b0000 { 558 compatible = "st,stm32mp25-sai"; 559 reg = <0x402b0000 0x4>, <0x402ba3f0 0x10>; 560 ranges = <0 0x402b0000 0x400>; 561 #address-cells = <1>; 562 #size-cells = <1>; 563 clocks = <&rcc CK_BUS_SAI3>; 564 clock-names = "pclk"; 565 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 566 resets = <&rcc SAI3_R>; 567 access-controllers = <&rifsc 51>; 568 status = "disabled"; 569 570 sai3a: audio-controller@402b0004 { 571 compatible = "st,stm32-sai-sub-a"; 572 reg = <0x4 0x20>; 573 #sound-dai-cells = <0>; 574 clocks = <&rcc CK_KER_SAI3>; 575 clock-names = "sai_ck"; 576 dmas = <&hpdma 77 0x43 0x21>; 577 status = "disabled"; 578 }; 579 580 sai3b: audio-controller@502b0024 { 581 compatible = "st,stm32-sai-sub-b"; 582 reg = <0x24 0x20>; 583 #sound-dai-cells = <0>; 584 clocks = <&rcc CK_KER_SAI3>; 585 clock-names = "sai_ck"; 586 dmas = <&hpdma 78 0x43 0x12>; 587 status = "disabled"; 588 }; 589 }; 590 591 usart1: serial@40330000 { 592 compatible = "st,stm32h7-uart"; 593 reg = <0x40330000 0x400>; 594 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&rcc CK_KER_USART1>; 596 dmas = <&hpdma 9 0x20 0x10012>, 597 <&hpdma 10 0x20 0x3021>; 598 dma-names = "rx", "tx"; 599 access-controllers = <&rifsc 31>; 600 status = "disabled"; 601 }; 602 603 sai4: sai@40340000 { 604 compatible = "st,stm32mp25-sai"; 605 reg = <0x40340000 0x4>, <0x4034a3f0 0x10>; 606 ranges = <0 0x40340000 0x400>; 607 #address-cells = <1>; 608 #size-cells = <1>; 609 clocks = <&rcc CK_BUS_SAI4>; 610 clock-names = "pclk"; 611 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 612 resets = <&rcc SAI4_R>; 613 access-controllers = <&rifsc 52>; 614 status = "disabled"; 615 616 sai4a: audio-controller@40340004 { 617 compatible = "st,stm32-sai-sub-a"; 618 reg = <0x4 0x20>; 619 #sound-dai-cells = <0>; 620 clocks = <&rcc CK_KER_SAI4>; 621 clock-names = "sai_ck"; 622 dmas = <&hpdma 79 0x63 0x21>; 623 status = "disabled"; 624 }; 625 626 sai4b: audio-controller@40340024 { 627 compatible = "st,stm32-sai-sub-b"; 628 reg = <0x24 0x20>; 629 #sound-dai-cells = <0>; 630 clocks = <&rcc CK_KER_SAI4>; 631 clock-names = "sai_ck"; 632 dmas = <&hpdma 80 0x43 0x12>; 633 status = "disabled"; 634 }; 635 }; 636 637 uart7: serial@40370000 { 638 compatible = "st,stm32h7-uart"; 639 reg = <0x40370000 0x400>; 640 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 641 clocks = <&rcc CK_KER_UART7>; 642 dmas = <&hpdma 21 0x20 0x10012>, 643 <&hpdma 22 0x20 0x3021>; 644 dma-names = "rx", "tx"; 645 access-controllers = <&rifsc 37>; 646 status = "disabled"; 647 }; 648 649 rng: rng@42020000 { 650 compatible = "st,stm32mp25-rng"; 651 reg = <0x42020000 0x400>; 652 clocks = <&clk_rcbsec>, <&rcc CK_BUS_RNG>; 653 clock-names = "core", "bus"; 654 resets = <&rcc RNG_R>; 655 access-controllers = <&rifsc 92>; 656 status = "disabled"; 657 }; 658 659 spi8: spi@46020000 { 660 compatible = "st,stm32mp25-spi"; 661 reg = <0x46020000 0x400>; 662 #address-cells = <1>; 663 #size-cells = <0>; 664 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 665 clocks = <&rcc CK_KER_SPI8>; 666 resets = <&rcc SPI8_R>; 667 dmas = <&hpdma 171 0x20 0x3012>, 668 <&hpdma 172 0x20 0x3021>; 669 dma-names = "rx", "tx"; 670 access-controllers = <&rifsc 29>; 671 status = "disabled"; 672 }; 673 674 i2c8: i2c@46040000 { 675 compatible = "st,stm32mp25-i2c"; 676 reg = <0x46040000 0x400>; 677 #address-cells = <1>; 678 #size-cells = <0>; 679 interrupt-names = "event"; 680 interrupts-extended = <&exti2 25 IRQ_TYPE_LEVEL_HIGH>; 681 clocks = <&rcc CK_KER_I2C8>; 682 resets = <&rcc I2C8_R>; 683 dmas = <&hpdma 168 0x20 0x3012>, 684 <&hpdma 169 0x20 0x3021>; 685 dma-names = "rx", "tx"; 686 access-controllers = <&rifsc 48>; 687 power-domains = <&cluster_pd>; 688 i2c-analog-filter; 689 wakeup-source; 690 status = "disabled"; 691 }; 692 693 csi: csi@48020000 { 694 compatible = "st,stm32mp25-csi"; 695 reg = <0x48020000 0x2000>; 696 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 697 resets = <&rcc CSI_R>; 698 clocks = <&rcc CK_KER_CSI>, <&rcc CK_KER_CSITXESC>, 699 <&rcc CK_KER_CSIPHY>; 700 clock-names = "pclk", "txesc", "csi2phy"; 701 access-controllers = <&rifsc 86>; 702 power-domains = <&cluster_pd>; 703 status = "disabled"; 704 }; 705 706 dcmipp: dcmipp@48030000 { 707 compatible = "st,stm32mp25-dcmipp"; 708 reg = <0x48030000 0x1000>; 709 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 710 resets = <&rcc DCMIPP_R>; 711 clocks = <&rcc CK_BUS_DCMIPP>, <&rcc CK_KER_CSI>; 712 clock-names = "kclk", "mclk"; 713 access-controllers = <&rifsc 87>; 714 power-domains = <&cluster_pd>; 715 status = "disabled"; 716 }; 717 718 sdmmc1: mmc@48220000 { 719 compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; 720 reg = <0x48220000 0x400>, <0x44230400 0x8>; 721 arm,primecell-periphid = <0x00353180>; 722 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 723 clocks = <&rcc CK_KER_SDMMC1 >; 724 clock-names = "apb_pclk"; 725 resets = <&rcc SDMMC1_R>; 726 cap-sd-highspeed; 727 cap-mmc-highspeed; 728 max-frequency = <120000000>; 729 access-controllers = <&rifsc 76>; 730 status = "disabled"; 731 }; 732 733 ethernet1: ethernet@482c0000 { 734 compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20"; 735 reg = <0x482c0000 0x4000>; 736 reg-names = "stmmaceth"; 737 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 738 interrupt-names = "macirq"; 739 clock-names = "stmmaceth", 740 "mac-clk-tx", 741 "mac-clk-rx", 742 "ptp_ref", 743 "ethstp", 744 "eth-ck"; 745 clocks = <&rcc CK_ETH1_MAC>, 746 <&rcc CK_ETH1_TX>, 747 <&rcc CK_ETH1_RX>, 748 <&rcc CK_KER_ETH1PTP>, 749 <&rcc CK_ETH1_STP>, 750 <&rcc CK_KER_ETH1>; 751 snps,axi-config = <&stmmac_axi_config_1>; 752 snps,mixed-burst; 753 snps,mtl-rx-config = <&mtl_rx_setup_1>; 754 snps,mtl-tx-config = <&mtl_tx_setup_1>; 755 snps,pbl = <2>; 756 snps,tso; 757 st,syscon = <&syscfg 0x3000>; 758 access-controllers = <&rifsc 60>; 759 status = "disabled"; 760 761 mtl_rx_setup_1: rx-queues-config { 762 snps,rx-queues-to-use = <2>; 763 queue0 {}; 764 queue1 {}; 765 }; 766 767 mtl_tx_setup_1: tx-queues-config { 768 snps,tx-queues-to-use = <4>; 769 queue0 {}; 770 queue1 {}; 771 queue2 {}; 772 queue3 {}; 773 }; 774 775 stmmac_axi_config_1: stmmac-axi-config { 776 snps,blen = <0 0 0 0 16 8 4>; 777 snps,rd_osr_lmt = <0x7>; 778 snps,wr_osr_lmt = <0x7>; 779 }; 780 }; 781 }; 782 783 bsec: efuse@44000000 { 784 compatible = "st,stm32mp25-bsec"; 785 reg = <0x44000000 0x1000>; 786 #address-cells = <1>; 787 #size-cells = <1>; 788 789 part-number-otp@24 { 790 reg = <0x24 0x4>; 791 }; 792 793 package-otp@1e8 { 794 reg = <0x1e8 0x1>; 795 bits = <0 3>; 796 }; 797 }; 798 799 rcc: clock-controller@44200000 { 800 compatible = "st,stm32mp25-rcc"; 801 reg = <0x44200000 0x10000>; 802 #clock-cells = <1>; 803 #reset-cells = <1>; 804 clocks = <&scmi_clk CK_SCMI_HSE>, 805 <&scmi_clk CK_SCMI_HSI>, 806 <&scmi_clk CK_SCMI_MSI>, 807 <&scmi_clk CK_SCMI_LSE>, 808 <&scmi_clk CK_SCMI_LSI>, 809 <&scmi_clk CK_SCMI_HSE_DIV2>, 810 <&scmi_clk CK_SCMI_ICN_HS_MCU>, 811 <&scmi_clk CK_SCMI_ICN_LS_MCU>, 812 <&scmi_clk CK_SCMI_ICN_SDMMC>, 813 <&scmi_clk CK_SCMI_ICN_DDR>, 814 <&scmi_clk CK_SCMI_ICN_DISPLAY>, 815 <&scmi_clk CK_SCMI_ICN_HSL>, 816 <&scmi_clk CK_SCMI_ICN_NIC>, 817 <&scmi_clk CK_SCMI_ICN_VID>, 818 <&scmi_clk CK_SCMI_FLEXGEN_07>, 819 <&scmi_clk CK_SCMI_FLEXGEN_08>, 820 <&scmi_clk CK_SCMI_FLEXGEN_09>, 821 <&scmi_clk CK_SCMI_FLEXGEN_10>, 822 <&scmi_clk CK_SCMI_FLEXGEN_11>, 823 <&scmi_clk CK_SCMI_FLEXGEN_12>, 824 <&scmi_clk CK_SCMI_FLEXGEN_13>, 825 <&scmi_clk CK_SCMI_FLEXGEN_14>, 826 <&scmi_clk CK_SCMI_FLEXGEN_15>, 827 <&scmi_clk CK_SCMI_FLEXGEN_16>, 828 <&scmi_clk CK_SCMI_FLEXGEN_17>, 829 <&scmi_clk CK_SCMI_FLEXGEN_18>, 830 <&scmi_clk CK_SCMI_FLEXGEN_19>, 831 <&scmi_clk CK_SCMI_FLEXGEN_20>, 832 <&scmi_clk CK_SCMI_FLEXGEN_21>, 833 <&scmi_clk CK_SCMI_FLEXGEN_22>, 834 <&scmi_clk CK_SCMI_FLEXGEN_23>, 835 <&scmi_clk CK_SCMI_FLEXGEN_24>, 836 <&scmi_clk CK_SCMI_FLEXGEN_25>, 837 <&scmi_clk CK_SCMI_FLEXGEN_26>, 838 <&scmi_clk CK_SCMI_FLEXGEN_27>, 839 <&scmi_clk CK_SCMI_FLEXGEN_28>, 840 <&scmi_clk CK_SCMI_FLEXGEN_29>, 841 <&scmi_clk CK_SCMI_FLEXGEN_30>, 842 <&scmi_clk CK_SCMI_FLEXGEN_31>, 843 <&scmi_clk CK_SCMI_FLEXGEN_32>, 844 <&scmi_clk CK_SCMI_FLEXGEN_33>, 845 <&scmi_clk CK_SCMI_FLEXGEN_34>, 846 <&scmi_clk CK_SCMI_FLEXGEN_35>, 847 <&scmi_clk CK_SCMI_FLEXGEN_36>, 848 <&scmi_clk CK_SCMI_FLEXGEN_37>, 849 <&scmi_clk CK_SCMI_FLEXGEN_38>, 850 <&scmi_clk CK_SCMI_FLEXGEN_39>, 851 <&scmi_clk CK_SCMI_FLEXGEN_40>, 852 <&scmi_clk CK_SCMI_FLEXGEN_41>, 853 <&scmi_clk CK_SCMI_FLEXGEN_42>, 854 <&scmi_clk CK_SCMI_FLEXGEN_43>, 855 <&scmi_clk CK_SCMI_FLEXGEN_44>, 856 <&scmi_clk CK_SCMI_FLEXGEN_45>, 857 <&scmi_clk CK_SCMI_FLEXGEN_46>, 858 <&scmi_clk CK_SCMI_FLEXGEN_47>, 859 <&scmi_clk CK_SCMI_FLEXGEN_48>, 860 <&scmi_clk CK_SCMI_FLEXGEN_49>, 861 <&scmi_clk CK_SCMI_FLEXGEN_50>, 862 <&scmi_clk CK_SCMI_FLEXGEN_51>, 863 <&scmi_clk CK_SCMI_FLEXGEN_52>, 864 <&scmi_clk CK_SCMI_FLEXGEN_53>, 865 <&scmi_clk CK_SCMI_FLEXGEN_54>, 866 <&scmi_clk CK_SCMI_FLEXGEN_55>, 867 <&scmi_clk CK_SCMI_FLEXGEN_56>, 868 <&scmi_clk CK_SCMI_FLEXGEN_57>, 869 <&scmi_clk CK_SCMI_FLEXGEN_58>, 870 <&scmi_clk CK_SCMI_FLEXGEN_59>, 871 <&scmi_clk CK_SCMI_FLEXGEN_60>, 872 <&scmi_clk CK_SCMI_FLEXGEN_61>, 873 <&scmi_clk CK_SCMI_FLEXGEN_62>, 874 <&scmi_clk CK_SCMI_FLEXGEN_63>, 875 <&scmi_clk CK_SCMI_ICN_APB1>, 876 <&scmi_clk CK_SCMI_ICN_APB2>, 877 <&scmi_clk CK_SCMI_ICN_APB3>, 878 <&scmi_clk CK_SCMI_ICN_APB4>, 879 <&scmi_clk CK_SCMI_ICN_APBDBG>, 880 <&scmi_clk CK_SCMI_TIMG1>, 881 <&scmi_clk CK_SCMI_TIMG2>, 882 <&scmi_clk CK_SCMI_PLL3>, 883 <&clk_dsi_txbyte>; 884 access-controllers = <&rifsc 156>; 885 }; 886 887 exti1: interrupt-controller@44220000 { 888 compatible = "st,stm32mp1-exti", "syscon"; 889 reg = <0x44220000 0x400>; 890 interrupt-controller; 891 #interrupt-cells = <2>; 892 interrupts-extended = 893 <&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 894 <&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 895 <&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 896 <&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 897 <&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 898 <&intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 899 <&intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 900 <&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 901 <&intc GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 902 <&intc GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 903 <&intc GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 904 <&intc GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 905 <&intc GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 906 <&intc GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 907 <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 908 <&intc GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 909 <&intc GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 910 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 911 <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 912 <&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 913 <0>, /* EXTI_20 */ 914 <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 915 <&intc GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 916 <&intc GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 917 <&intc GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 918 <&intc GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 919 <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 920 <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 921 <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 922 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 923 <&intc GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 924 <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 925 <&intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 926 <&intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 927 <&intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 928 <0>, 929 <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 930 <&intc GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 931 <&intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 932 <&intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 933 <&intc GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 934 <&intc GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 935 <&intc GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 936 <&intc GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 937 <&intc GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 938 <&intc GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 939 <&intc GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 940 <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 941 <&intc GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 942 <&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 943 <&intc GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 944 <0>, 945 <0>, 946 <0>, 947 <0>, 948 <0>, 949 <0>, 950 <0>, 951 <0>, 952 <&intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 953 <0>, /* EXTI_60 */ 954 <&intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 955 <0>, 956 <0>, 957 <&intc GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 958 <0>, 959 <0>, 960 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 961 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 962 <0>, 963 <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ 964 <0>, 965 <&intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 966 <&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 967 <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 968 <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 969 <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 970 <&intc GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 971 <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 972 <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 973 <0>, /* EXTI_80 */ 974 <0>, 975 <0>, 976 <&intc GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 977 <&intc GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 978 }; 979 980 syscfg: syscon@44230000 { 981 compatible = "st,stm32mp23-syscfg", "syscon"; 982 reg = <0x44230000 0x10000>; 983 #clock-cells = <0>; 984 }; 985 986 pinctrl: pinctrl@44240000 { 987 compatible = "st,stm32mp257-pinctrl"; 988 ranges = <0 0x44240000 0xa0400>; 989 #address-cells = <1>; 990 #size-cells = <1>; 991 interrupt-parent = <&exti1>; 992 st,syscfg = <&exti1 0x60 0xff>; 993 pins-are-numbered; 994 995 gpioa: gpio@44240000 { 996 reg = <0x0 0x400>; 997 gpio-controller; 998 #gpio-cells = <2>; 999 interrupt-controller; 1000 #interrupt-cells = <2>; 1001 clocks = <&scmi_clk CK_SCMI_GPIOA>; 1002 st,bank-name = "GPIOA"; 1003 status = "disabled"; 1004 }; 1005 1006 gpiob: gpio@44250000 { 1007 reg = <0x10000 0x400>; 1008 gpio-controller; 1009 #gpio-cells = <2>; 1010 interrupt-controller; 1011 #interrupt-cells = <2>; 1012 clocks = <&scmi_clk CK_SCMI_GPIOB>; 1013 st,bank-name = "GPIOB"; 1014 status = "disabled"; 1015 }; 1016 1017 gpioc: gpio@44260000 { 1018 reg = <0x20000 0x400>; 1019 gpio-controller; 1020 #gpio-cells = <2>; 1021 interrupt-controller; 1022 #interrupt-cells = <2>; 1023 clocks = <&scmi_clk CK_SCMI_GPIOC>; 1024 st,bank-name = "GPIOC"; 1025 status = "disabled"; 1026 }; 1027 1028 gpiod: gpio@44270000 { 1029 reg = <0x30000 0x400>; 1030 gpio-controller; 1031 #gpio-cells = <2>; 1032 interrupt-controller; 1033 #interrupt-cells = <2>; 1034 clocks = <&scmi_clk CK_SCMI_GPIOD>; 1035 st,bank-name = "GPIOD"; 1036 status = "disabled"; 1037 }; 1038 1039 gpioe: gpio@44280000 { 1040 reg = <0x40000 0x400>; 1041 gpio-controller; 1042 #gpio-cells = <2>; 1043 interrupt-controller; 1044 #interrupt-cells = <2>; 1045 clocks = <&scmi_clk CK_SCMI_GPIOE>; 1046 st,bank-name = "GPIOE"; 1047 status = "disabled"; 1048 }; 1049 1050 gpiof: gpio@44290000 { 1051 reg = <0x50000 0x400>; 1052 gpio-controller; 1053 #gpio-cells = <2>; 1054 interrupt-controller; 1055 #interrupt-cells = <2>; 1056 clocks = <&scmi_clk CK_SCMI_GPIOF>; 1057 st,bank-name = "GPIOF"; 1058 status = "disabled"; 1059 }; 1060 1061 gpiog: gpio@442a0000 { 1062 reg = <0x60000 0x400>; 1063 gpio-controller; 1064 #gpio-cells = <2>; 1065 interrupt-controller; 1066 #interrupt-cells = <2>; 1067 clocks = <&scmi_clk CK_SCMI_GPIOG>; 1068 st,bank-name = "GPIOG"; 1069 status = "disabled"; 1070 }; 1071 1072 gpioh: gpio@442b0000 { 1073 reg = <0x70000 0x400>; 1074 gpio-controller; 1075 #gpio-cells = <2>; 1076 interrupt-controller; 1077 #interrupt-cells = <2>; 1078 clocks = <&scmi_clk CK_SCMI_GPIOH>; 1079 st,bank-name = "GPIOH"; 1080 status = "disabled"; 1081 }; 1082 1083 gpioi: gpio@442c0000 { 1084 reg = <0x80000 0x400>; 1085 gpio-controller; 1086 #gpio-cells = <2>; 1087 interrupt-controller; 1088 #interrupt-cells = <2>; 1089 clocks = <&scmi_clk CK_SCMI_GPIOI>; 1090 st,bank-name = "GPIOI"; 1091 status = "disabled"; 1092 }; 1093 }; 1094 1095 rtc: rtc@46000000 { 1096 compatible = "st,stm32mp25-rtc"; 1097 reg = <0x46000000 0x400>; 1098 clocks = <&scmi_clk CK_SCMI_RTC>, 1099 <&scmi_clk CK_SCMI_RTCCK>; 1100 clock-names = "pclk", "rtc_ck"; 1101 interrupts-extended = <&exti2 17 IRQ_TYPE_LEVEL_HIGH>; 1102 status = "disabled"; 1103 }; 1104 1105 pinctrl_z: pinctrl@46200000 { 1106 compatible = "st,stm32mp257-z-pinctrl"; 1107 ranges = <0 0x46200000 0x400>; 1108 #address-cells = <1>; 1109 #size-cells = <1>; 1110 interrupt-parent = <&exti1>; 1111 st,syscfg = <&exti1 0x60 0xff>; 1112 pins-are-numbered; 1113 1114 gpioz: gpio@46200000 { 1115 reg = <0 0x400>; 1116 gpio-controller; 1117 #gpio-cells = <2>; 1118 interrupt-controller; 1119 #interrupt-cells = <2>; 1120 clocks = <&scmi_clk CK_SCMI_GPIOZ>; 1121 st,bank-name = "GPIOZ"; 1122 st,bank-ioport = <11>; 1123 status = "disabled"; 1124 }; 1125 1126 }; 1127 1128 exti2: interrupt-controller@46230000 { 1129 compatible = "st,stm32mp1-exti", "syscon"; 1130 reg = <0x46230000 0x400>; 1131 interrupt-controller; 1132 #interrupt-cells = <2>; 1133 interrupts-extended = 1134 <&intc GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 1135 <&intc GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1136 <&intc GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1137 <&intc GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1138 <&intc GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1139 <&intc GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1140 <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1141 <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1142 <&intc GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1143 <&intc GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1144 <&intc GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 1145 <&intc GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1146 <&intc GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1147 <&intc GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1148 <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1149 <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1150 <&intc GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1151 <&intc GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1152 <0>, 1153 <0>, 1154 <0>, /* EXTI_20 */ 1155 <&intc GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1156 <&intc GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1157 <0>, 1158 <0>, 1159 <&intc GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1160 <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1161 <&intc GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 1162 <0>, 1163 <&intc GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1164 <&intc GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 1165 <&intc GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1166 <0>, 1167 <&intc GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1168 <&intc GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 1169 <0>, 1170 <0>, 1171 <&intc GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 1172 <0>, 1173 <0>, 1174 <&intc GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 1175 <0>, 1176 <0>, 1177 <&intc GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1178 <0>, 1179 <0>, 1180 <&intc GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1181 <0>, 1182 <&intc GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 1183 <&intc GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1184 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 1185 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1186 <&intc GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 1187 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1188 <0>, 1189 <0>, 1190 <0>, 1191 <0>, 1192 <0>, 1193 <0>, 1194 <0>, /* EXTI_60 */ 1195 <&intc GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 1196 <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1197 <0>, 1198 <&intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1199 <&intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1200 <&intc GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1201 <&intc GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1202 <0>, 1203 <0>, 1204 <&intc GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ 1205 }; 1206 1207 ltdc: display-controller@48010000 { 1208 compatible = "st,stm32mp251-ltdc"; 1209 reg = <0x48010000 0x400>; 1210 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1212 clocks = <&rcc CK_KER_LTDC>, <&rcc CK_BUS_LTDC>; 1213 clock-names = "lcd", "bus"; 1214 resets = <&rcc LTDC_R>; 1215 access-controllers = <&rifsc 80>; 1216 status = "disabled"; 1217 }; 1218 1219 intc: interrupt-controller@4ac10000 { 1220 compatible = "arm,gic-400"; 1221 reg = <0x4ac10000 0x1000>, 1222 <0x4ac20000 0x20000>, 1223 <0x4ac40000 0x20000>, 1224 <0x4ac60000 0x20000>; 1225 #interrupt-cells = <3>; 1226 interrupt-controller; 1227 }; 1228 }; 1229}; 1230