1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Spreadtrum Whale2 platform peripherals 4 * 5 * Copyright (C) 2016, Spreadtrum Communications Inc. 6 */ 7 8#include <dt-bindings/clock/sprd,sc9860-clk.h> 9 10/ { 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 soc: soc { 16 compatible = "simple-bus"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 ranges; 20 21 ap_ahb_regs: syscon@20210000 { 22 compatible = "syscon"; 23 reg = <0 0x20210000 0 0x10000>; 24 }; 25 26 pmu_regs: syscon@402b0000 { 27 compatible = "syscon"; 28 reg = <0 0x402b0000 0 0x10000>; 29 }; 30 31 aon_regs: syscon@402e0000 { 32 compatible = "syscon"; 33 reg = <0 0x402e0000 0 0x10000>; 34 }; 35 36 ana_regs: syscon@40400000 { 37 compatible = "syscon"; 38 reg = <0 0x40400000 0 0x10000>; 39 }; 40 41 agcp_regs: syscon@415e0000 { 42 compatible = "syscon"; 43 reg = <0 0x415e0000 0 0x1000000>; 44 }; 45 46 vsp_regs: syscon@61100000 { 47 compatible = "syscon"; 48 reg = <0 0x61100000 0 0x10000>; 49 }; 50 51 cam_regs: syscon@62100000 { 52 compatible = "syscon"; 53 reg = <0 0x62100000 0 0x10000>; 54 }; 55 56 disp_regs: syscon@63100000 { 57 compatible = "syscon"; 58 reg = <0 0x63100000 0 0x10000>; 59 }; 60 61 ap_apb_regs: syscon@70b00000 { 62 compatible = "syscon"; 63 reg = <0 0x70b00000 0 0x40000>; 64 }; 65 66 ap-apb@70000000 { 67 compatible = "simple-bus"; 68 #address-cells = <1>; 69 #size-cells = <1>; 70 ranges = <0 0x0 0x70000000 0x10000000>; 71 72 uart0: serial@0 { 73 compatible = "sprd,sc9860-uart", 74 "sprd,sc9836-uart"; 75 reg = <0x0 0x100>; 76 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 77 clocks = <&apapb_gate CLK_UART0_EB>, 78 <&ap_clk CLK_UART0>, 79 <&ext_26m>; 80 clock-names = "enable", "uart", "source"; 81 status = "disabled"; 82 }; 83 84 uart1: serial@100000 { 85 compatible = "sprd,sc9860-uart", 86 "sprd,sc9836-uart"; 87 reg = <0x100000 0x100>; 88 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 89 clocks = <&apapb_gate CLK_UART1_EB>, 90 <&ap_clk CLK_UART1>, 91 <&ext_26m>; 92 clock-names = "enable", "uart", "source"; 93 status = "disabled"; 94 }; 95 96 uart2: serial@200000 { 97 compatible = "sprd,sc9860-uart", 98 "sprd,sc9836-uart"; 99 reg = <0x200000 0x100>; 100 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 101 clocks = <&apapb_gate CLK_UART2_EB>, 102 <&ap_clk CLK_UART2>, 103 <&ext_26m>; 104 clock-names = "enable", "uart", "source"; 105 status = "disabled"; 106 }; 107 108 uart3: serial@300000 { 109 compatible = "sprd,sc9860-uart", 110 "sprd,sc9836-uart"; 111 reg = <0x300000 0x100>; 112 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 113 clocks = <&apapb_gate CLK_UART3_EB>, 114 <&ap_clk CLK_UART3>, 115 <&ext_26m>; 116 clock-names = "enable", "uart", "source"; 117 status = "disabled"; 118 }; 119 }; 120 121 ap-ahb { 122 compatible = "simple-bus"; 123 #address-cells = <2>; 124 #size-cells = <2>; 125 ranges; 126 127 ap_dma: dma-controller@20100000 { 128 compatible = "sprd,sc9860-dma"; 129 reg = <0 0x20100000 0 0x4000>; 130 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 131 #dma-cells = <1>; 132 /* For backwards compatibility: */ 133 #dma-channels = <32>; 134 dma-channels = <32>; 135 clocks = <&apahb_gate CLK_DMA_EB>; 136 clock-names = "enable"; 137 }; 138 139 sdio3: mmc@50430000 { 140 compatible = "sprd,sdhci-r11"; 141 reg = <0 0x50430000 0 0x1000>; 142 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 143 144 clocks = <&aon_prediv CLK_EMMC_2X>, 145 <&apahb_gate CLK_EMMC_EB>, 146 <&aon_gate CLK_EMMC_2X_EN>; 147 clock-names = "sdio", "enable", "2x_enable"; 148 assigned-clocks = <&aon_prediv CLK_EMMC_2X>; 149 assigned-clock-parents = <&clk_l0_409m6>; 150 151 sprd,phy-delay-mmc-hs400 = <0x44 0x7f 0x2e 0x2e>; 152 sprd,phy-delay-mmc-hs200 = <0x0 0x8c 0x8c 0x8c>; 153 sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x14 0x14>; 154 sprd,phy-delay-mmc-hs400es = <0x3f 0x3f 0x2e 0x2e>; 155 vmmc-supply = <&vddemmccore>; 156 bus-width = <8>; 157 non-removable; 158 no-sdio; 159 no-sd; 160 cap-mmc-hw-reset; 161 mmc-hs400-enhanced-strobe; 162 mmc-hs400-1_8v; 163 mmc-hs200-1_8v; 164 mmc-ddr-1_8v; 165 }; 166 }; 167 168 aon { 169 compatible = "simple-bus"; 170 #address-cells = <2>; 171 #size-cells = <2>; 172 ranges; 173 174 adi_bus: spi@40030000 { 175 compatible = "sprd,sc9860-adi"; 176 reg = <0 0x40030000 0 0x10000>; 177 hwlocks = <&hwlock 0>; 178 hwlock-names = "adi"; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 }; 182 183 timer@40050000 { 184 compatible = "sprd,sc9860-timer"; 185 reg = <0 0x40050000 0 0x20>; 186 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 187 clocks = <&ext_32k>; 188 }; 189 190 timer@40050020 { 191 compatible = "sprd,sc9860-suspend-timer"; 192 reg = <0 0x40050020 0 0x20>; 193 clocks = <&ext_32k>; 194 }; 195 196 hwlock: hwspinlock@40500000 { 197 compatible = "sprd,hwspinlock-r3p0"; 198 reg = <0 0x40500000 0 0x1000>; 199 #hwlock-cells = <1>; 200 clocks = <&aon_gate CLK_SPLK_EB>; 201 clock-names = "enable"; 202 }; 203 204 eic_debounce: gpio@40210000 { 205 compatible = "sprd,sc9860-eic-debounce"; 206 reg = <0 0x40210000 0 0x80>; 207 gpio-controller; 208 #gpio-cells = <2>; 209 interrupt-controller; 210 #interrupt-cells = <2>; 211 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 212 }; 213 214 eic_latch: gpio@40210080 { 215 compatible = "sprd,sc9860-eic-latch"; 216 reg = <0 0x40210080 0 0x20>; 217 gpio-controller; 218 #gpio-cells = <2>; 219 interrupt-controller; 220 #interrupt-cells = <2>; 221 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 222 }; 223 224 eic_async: gpio@402100a0 { 225 compatible = "sprd,sc9860-eic-async"; 226 reg = <0 0x402100a0 0 0x20>; 227 gpio-controller; 228 #gpio-cells = <2>; 229 interrupt-controller; 230 #interrupt-cells = <2>; 231 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 232 }; 233 234 eic_sync: gpio@402100c0 { 235 compatible = "sprd,sc9860-eic-sync"; 236 reg = <0 0x402100c0 0 0x20>; 237 gpio-controller; 238 #gpio-cells = <2>; 239 interrupt-controller; 240 #interrupt-cells = <2>; 241 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 242 }; 243 244 ap_gpio: gpio@40280000 { 245 compatible = "sprd,sc9860-gpio"; 246 reg = <0 0x40280000 0 0x1000>; 247 gpio-controller; 248 #gpio-cells = <2>; 249 interrupt-controller; 250 #interrupt-cells = <2>; 251 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 252 }; 253 254 pin_controller: pinctrl@402a0000 { 255 compatible = "sprd,sc9860-pinctrl"; 256 reg = <0 0x402a0000 0 0x10000>; 257 }; 258 259 watchdog@40310000 { 260 compatible = "sprd,sp9860-wdt"; 261 reg = <0 0x40310000 0 0x1000>; 262 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 263 timeout-sec = <12>; 264 clocks = <&aon_gate CLK_APCPU_WDG_EB>, 265 <&aon_gate CLK_AP_WDG_RTC_EB>; 266 clock-names = "enable", "rtc_enable"; 267 }; 268 }; 269 270 agcp { 271 compatible = "simple-bus"; 272 #address-cells = <2>; 273 #size-cells = <2>; 274 ranges; 275 276 agcp_dma: dma-controller@41580000 { 277 compatible = "sprd,sc9860-dma"; 278 reg = <0 0x41580000 0 0x4000>; 279 #dma-cells = <1>; 280 /* For backwards compatibility: */ 281 #dma-channels = <32>; 282 dma-channels = <32>; 283 clocks = <&agcp_gate CLK_AGCP_DMAAP_EB>, 284 <&agcp_gate CLK_AGCP_AP_ASHB_EB>; 285 clock-names = "enable", "ashb_eb"; 286 }; 287 }; 288 }; 289 290 ext_32k: ext_32k { 291 compatible = "fixed-clock"; 292 #clock-cells = <0>; 293 clock-frequency = <32768>; 294 clock-output-names = "ext-32k"; 295 }; 296 297 ext_26m: ext_26m { 298 compatible = "fixed-clock"; 299 #clock-cells = <0>; 300 clock-frequency = <26000000>; 301 clock-output-names = "ext-26m"; 302 }; 303 304 ext_rco_100m: ext_rco_100m { 305 compatible = "fixed-clock"; 306 #clock-cells = <0>; 307 clock-frequency = <100000000>; 308 clock-output-names = "ext-rco-100m"; 309 }; 310 311 clk_l0_409m6: clk_l0_409m6 { 312 compatible = "fixed-clock"; 313 #clock-cells = <0>; 314 clock-frequency = <409600000>; 315 clock-output-names = "ext-409m6"; 316 }; 317}; 318